arc_builtin.h 8.3 KB

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  1. /* ------------------------------------------
  2. * Copyright (c) 2016, Synopsys, Inc. All rights reserved.
  3. * Redistribution and use in source and binary forms, with or without modification,
  4. * are permitted provided that the following conditions are met:
  5. * 1) Redistributions of source code must retain the above copyright notice, this
  6. * list of conditions and the following disclaimer.
  7. * 2) Redistributions in binary form must reproduce the above copyright notice,
  8. * this list of conditions and the following disclaimer in the documentation and/or
  9. * other materials provided with the distribution.
  10. * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
  11. * be used to endorse or promote products derived from this software without
  12. * specific prior written permission.
  13. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  14. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  15. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  17. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  19. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  20. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  21. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  22. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23. *
  24. * \version 2016.05
  25. * \date 2014-06-12
  26. * \author Wayne Ren(Wei.Ren@synopsys.com)
  27. --------------------------------------------- */
  28. /**
  29. * \file
  30. * \ingroup ARC_HAL_BUILTIN
  31. * \brief header file of builtin and helper functions
  32. *
  33. * The Metaware toolchain and the GNU toolchain are supported. The details please go to see the file.
  34. */
  35. /**
  36. * \addtogroup ARC_HAL_BUILTIN
  37. * @{
  38. */
  39. #ifndef _ARC_HAL_BUILTIN_H_
  40. #define _ARC_HAL_BUILTIN_H_
  41. #include "inc/embARC_toolchain.h"
  42. #ifdef __cplusplus
  43. extern "C" {
  44. #endif
  45. #if defined (__MW__) /* Metaware toolchain */
  46. #define _arc_nop _nop /*!< no operation, generate a nop instruction produces a single NOP instruction in the compiled code */
  47. #define _arc_brk _brk /*!< generate a brk instruction */
  48. #define _arc_clri _clri /*!< generate a clri instruction */
  49. #define _arc_seti(c) _seti(c) /*!< generate a seti instruction */
  50. #define _arc_core_write(regno, val) _core_write(val, regno) /*!< write core register */
  51. #define _arc_core_read(regno) _core_read(regno) /*!< read core register */
  52. #define _arc_lr_reg(aux) _lr(aux) /*!< read auxiliary register */
  53. #define _arc_sr_reg(aux, val) _sr(val, aux) /*!< write auxiliary register */
  54. #define _arc_sleep(a) _sleep(a) /*!< generate a sleep instruction */
  55. #define _arc_flag(a) _flag(a) /*!< generate a flag instruction */
  56. #define _arc_kflag(a)
  57. #define _arc_sync _sync /*!< generate a sync instruction */
  58. /*
  59. * !< _arc_usually (expr) evaluates expression expr and
  60. * informs the compiler that the value is usually true.
  61. */
  62. #define _arc_usually(a) _Usually((a))
  63. /*
  64. * !< _arc_rarely (expr) evaluates expression expr and
  65. * informs the compiler that the value is rarely true.
  66. */
  67. #define _arc_rarely(a) _Rarely((a))
  68. #if 0
  69. /**
  70. * \brief Reverses the byte order of the 16-bit operand,
  71. * reversing the endianness of the value.
  72. * Not for ARC HS family
  73. */
  74. #define _arc_swap16(a) _swap16(a)
  75. /**
  76. * \brief Reverses the byte order of the 32-bit operand,
  77. * reversing the endianness of the value.
  78. * Not for ARC HS family
  79. */
  80. #define _arc_swap32(a) _swap32(a)
  81. #else
  82. Inline uint32_t _arc_swap32(uint32_t val) {
  83. register uint32_t v;
  84. __asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val));
  85. return v;
  86. }
  87. Inline uint16_t _arc_swap16(uint32_t val) {
  88. register uint32_t temp;
  89. register uint32_t v;
  90. __asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val));
  91. __asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp));
  92. return (unsigned short)v;
  93. }
  94. #endif
  95. /**
  96. * \brief Each call to _swi() generates one
  97. * software interrupt instruction (SWI) for processors
  98. * to support the SWI instruction.
  99. */
  100. #define _arc_swi _swi
  101. /* \todo add more builtin functions of metaware tool */
  102. #elif defined (__GNU__) /* GNU toolchain */
  103. #define _arc_nop __builtin_arc_nop
  104. #define _arc_brk __builtin_arc_brk
  105. #define _arc_seti(c) __builtin_arc_seti(c)
  106. #define _arc_core_write(regno, val) __builtin_arc_core_write(regno,val)
  107. #define _arc_core_read(regno) __builtin_arc_core_read(regno)
  108. #define _arc_flag(a) __builtin_arc_flag(a)
  109. #define _arc_kflag(a) __builtin_arc_kflag(a)
  110. #define _arc_lr_reg(aux) __builtin_arc_lr(aux)
  111. /* don't uncomment this now */
  112. //#define _arc_sr_reg(aux, val) __builtin_arc_sr(aux, val)
  113. #define _arc_sleep(a) __builtin_arc_sleep(a)
  114. //#define _arc_sync __builtin_arc_sync
  115. /**
  116. * \brief _arc_usually (expr) evaluates expression expr and
  117. * informs the compiler that the value is usually true.
  118. */
  119. #define _arc_usually(a) __builtin_expect((int)(a), 1)
  120. /**
  121. * \brief _arc_rarely (expr) evaluates expression expr and
  122. * informs the compiler that the value is rarely true.
  123. */
  124. #define _arc_rarely(a) __builtin_expect((int)(a), 0)
  125. /**
  126. * \brief Each call to _swi() generates one
  127. * software interrupt instruction (SWI) for processors
  128. * to support the SWI instruction.
  129. */
  130. #define _arc_swi __builtin_arc_swi
  131. Inline uint32_t _arc_clri(void) {
  132. register uint32_t v;
  133. __asm__ volatile ("clri %0" :"=r"(v));
  134. return v;
  135. }
  136. /* \todo add more builtin functions of gnu tool */
  137. Inline uint32_t _arc_swap32(uint32_t val) {
  138. register uint32_t v;
  139. __asm__ volatile ("swape %0, %1" :"=r"(v): "r"(val));
  140. return v;
  141. }
  142. Inline uint16_t _arc_swap16(uint32_t val) {
  143. register uint32_t temp;
  144. register uint32_t v;
  145. __asm__ volatile ("swape %0, %1" :"=r"(temp): "r"(val));
  146. __asm__ volatile ("lsr16 %0, %1" :"=r"(v): "r"(temp));
  147. return (unsigned short)v;
  148. }
  149. Inline void _arc_sync(void) {
  150. __asm__ volatile ("sync");
  151. }
  152. /**
  153. * \note Following is a workaround for arc gcc
  154. * built-in function __builtin_arc_sr.
  155. * But it is wrong in GCC arc-4.8-R3-rc3 and shouldn't be used.
  156. */
  157. /*
  158. * The auxiliary register address is specified as a long immediate operand by caller.
  159. * e.g.
  160. * write_aux_reg(0x69, some_val);
  161. * This generates the tightest code.
  162. */
  163. #define write_aux_reg(reg_imm, val) \
  164. ({ \
  165. Asm( \
  166. " sr %0, [%1] \n" \
  167. : \
  168. : "ir"(val), "r"(reg_imm)); \
  169. })
  170. #define _arc_sr_reg(aux, val) write_aux_reg(aux, val)
  171. #endif
  172. /* \todo add more helper functions here, such as memory operation */
  173. #define _arc_aux_read(aux) _arc_lr_reg(aux)
  174. #define _arc_aux_write(aux, val) _arc_sr_reg(aux, val)
  175. /**
  176. * \name cache related helper function
  177. * @{
  178. */
  179. /**
  180. * \brief read memory and bypass the cache
  181. * \param[in] ptr memory address
  182. * \return value in the memory
  183. */
  184. Inline uint32_t _arc_read_uncached_32(void *ptr)
  185. {
  186. uint32_t __ret;
  187. Asm("ld.di %0, [%1]":"=r"(__ret):"r"(ptr));
  188. return __ret;
  189. }
  190. /**
  191. * \brief write memory and bypass the cache
  192. * \param[in] ptr memory address
  193. * \param[in] data vaule to be written
  194. */
  195. Inline void _arc_write_uncached_32(void *ptr, uint32_t data)
  196. {
  197. Asm("st.di %0, [%1]":: "r"(data), "r"(ptr));
  198. }
  199. /**
  200. * \brief read memory with cache
  201. * \param[in] ptr memory address
  202. * \returns value in the memory
  203. */
  204. Inline uint32_t _arc_read_cached_32(void *ptr)
  205. {
  206. uint32_t __ret;
  207. Asm("ld %0, [%1]":"=r"(__ret):"r"(ptr));
  208. return __ret;
  209. }
  210. /**
  211. * \brief read memory with cache
  212. * \param[in] ptr memory address
  213. * \param[in] data vaule to be written
  214. * \return description
  215. */
  216. Inline void _arc_write_cached_32(void *ptr, uint32_t data)
  217. {
  218. Asm("st %0, [%1]":: "r"(data), "r"(ptr));
  219. }
  220. /**
  221. * \brief go to main function with proper arguments
  222. * \param argc argument count
  223. * \param argv argument content array
  224. * \retval return value of main function
  225. */
  226. Inline int32_t _arc_goto_main(int argc, char **argv) {
  227. int __ret;
  228. __asm__ volatile(
  229. "mov %%r0, %1\n"
  230. "mov %%r1, %2\n"
  231. "push_s %%blink\n"
  232. "jl main\n"
  233. "pop_s %%blink\n"
  234. "mov %0, %%r0"
  235. :"=r"(__ret): "r"(argc), "r"(argv));
  236. return (int)__ret;
  237. }
  238. #ifdef __cplusplus
  239. }
  240. #endif
  241. #if defined(LIB_SECURESHIELD) && defined(LIB_SECURESHIELD_OVERRIDES) && (SECURESHIELD_VERSION == 1)
  242. #define OVERRIDE_ARC_HAL_BUILTIN_H
  243. #include "secureshield_overrides.h"
  244. #endif
  245. /** @} */
  246. #endif /* _ARC_HAL_BUILTIN_H_ */
  247. /** @} */