drv_uart.c 11 KB

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  1. /*
  2. * Copyright (c) 2006-2024, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023/06/25 flyingcys first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include "board.h"
  14. #include "drv_uart.h"
  15. #include "drv_pinmux.h"
  16. #include "drv_ioremap.h"
  17. #define DBG_TAG "DRV.UART"
  18. #define DBG_LVL DBG_WARNING
  19. #include <rtdbg.h>
  20. /*
  21. * Divide positive or negative dividend by positive divisor and round
  22. * to closest integer. Result is undefined for negative divisors and
  23. * for negative dividends if the divisor variable type is unsigned.
  24. */
  25. #define DIV_ROUND_CLOSEST(x, divisor)( \
  26. { \
  27. typeof(x) __x = x; \
  28. typeof(divisor) __d = divisor; \
  29. (((typeof(x))-1) > 0 || \
  30. ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
  31. (((__x) + ((__d) / 2)) / (__d)) : \
  32. (((__x) - ((__d) / 2)) / (__d)); \
  33. } \
  34. )
  35. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  36. struct hw_uart_device
  37. {
  38. rt_ubase_t hw_base;
  39. rt_uint32_t irqno;
  40. };
  41. #define BSP_DEFINE_UART_DEVICE(no) \
  42. static struct hw_uart_device _uart##no##_device = \
  43. { \
  44. UART##no##_BASE, \
  45. UART##no##_IRQ \
  46. }; \
  47. static struct rt_serial_device _serial##no;
  48. #ifdef BSP_USING_UART0
  49. BSP_DEFINE_UART_DEVICE(0);
  50. #endif
  51. #ifdef BSP_USING_UART1
  52. BSP_DEFINE_UART_DEVICE(1);
  53. #endif
  54. #ifdef BSP_USING_UART2
  55. BSP_DEFINE_UART_DEVICE(2);
  56. #endif
  57. #ifdef BSP_USING_UART3
  58. BSP_DEFINE_UART_DEVICE(3);
  59. #endif
  60. rt_inline rt_uint32_t dw8250_read32(rt_ubase_t addr, rt_ubase_t offset)
  61. {
  62. return *((volatile rt_uint32_t *)(addr + (offset << UART_REG_SHIFT)));
  63. }
  64. rt_inline void dw8250_write32(rt_ubase_t addr, rt_ubase_t offset, rt_uint32_t value)
  65. {
  66. *((volatile rt_uint32_t *)(addr + (offset << UART_REG_SHIFT))) = value;
  67. if (offset == UART_LCR)
  68. {
  69. int tries = 1000;
  70. /* Make sure LCR write wasn't ignored */
  71. while (tries--)
  72. {
  73. unsigned int lcr = dw8250_read32(addr, UART_LCR);
  74. if ((value & ~UART_LCR_STKP) == (lcr & ~UART_LCR_STKP))
  75. {
  76. return;
  77. }
  78. dw8250_write32(addr, UART_FCR, UART_FCR_DEFVAL);
  79. dw8250_read32(addr, UART_RX);
  80. *((volatile rt_uint32_t *)(addr + (offset << UART_REG_SHIFT))) = value;
  81. }
  82. }
  83. }
  84. static void dw8250_uart_setbrg(rt_ubase_t addr, int baud_divisor)
  85. {
  86. /* to keep serial format, read lcr before writing BKSE */
  87. int lcr_val = dw8250_read32(addr, UART_LCR) & ~UART_LCR_BKSE;
  88. dw8250_write32(addr, UART_LCR, UART_LCR_BKSE | lcr_val);
  89. dw8250_write32(addr, UART_DLL, baud_divisor & 0xff);
  90. dw8250_write32(addr, UART_DLM, (baud_divisor >> 8) & 0xff);
  91. dw8250_write32(addr, UART_LCR, lcr_val);
  92. }
  93. static rt_err_t dw8250_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  94. {
  95. rt_base_t base;
  96. struct hw_uart_device *uart;
  97. int clock_divisor;
  98. int last_ier_state;
  99. RT_ASSERT(serial != RT_NULL);
  100. uart = (struct hw_uart_device *)serial->parent.user_data;
  101. base = uart->hw_base;
  102. while (!(dw8250_read32(base, UART_LSR) & UART_LSR_TEMT));
  103. last_ier_state = dw8250_read32(base, UART_IER);
  104. dw8250_write32(base, UART_IER, 0);
  105. dw8250_write32(base, UART_MCR, UART_MCRVAL);
  106. dw8250_write32(base, UART_FCR, UART_FCR_DEFVAL);
  107. /* initialize serial config to 8N1 before writing baudrate */
  108. dw8250_write32(base, UART_LCR, UART_LCR_8N1);
  109. clock_divisor = DIV_ROUND_CLOSEST(UART_INPUT_CLK, 16 * serial->config.baud_rate);
  110. dw8250_uart_setbrg(base, clock_divisor);
  111. dw8250_write32(base, UART_IER, last_ier_state);
  112. return RT_EOK;
  113. }
  114. static rt_err_t dw8250_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  115. {
  116. struct hw_uart_device *uart;
  117. RT_ASSERT(serial != RT_NULL);
  118. uart = (struct hw_uart_device *)serial->parent.user_data;
  119. switch (cmd)
  120. {
  121. case RT_DEVICE_CTRL_CLR_INT:
  122. /* Disable rx irq */
  123. dw8250_write32(uart->hw_base, UART_IER, !UART_IER_RDI);
  124. rt_hw_interrupt_mask(uart->irqno);
  125. break;
  126. case RT_DEVICE_CTRL_SET_INT:
  127. /* Enable rx irq */
  128. dw8250_write32(uart->hw_base, UART_IER, UART_IER_RDI);
  129. rt_hw_interrupt_umask(uart->irqno);
  130. break;
  131. }
  132. return RT_EOK;
  133. }
  134. static int dw8250_uart_putc(struct rt_serial_device *serial, char c)
  135. {
  136. rt_base_t base;
  137. struct hw_uart_device *uart;
  138. RT_ASSERT(serial != RT_NULL);
  139. uart = (struct hw_uart_device *)serial->parent.user_data;
  140. base = uart->hw_base;
  141. while ((dw8250_read32(base, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY);
  142. dw8250_write32(base, UART_TX, c);
  143. return 1;
  144. }
  145. static int dw8250_uart_getc(struct rt_serial_device *serial)
  146. {
  147. int ch = -1;
  148. rt_base_t base;
  149. struct hw_uart_device *uart;
  150. RT_ASSERT(serial != RT_NULL);
  151. uart = (struct hw_uart_device *)serial->parent.user_data;
  152. base = uart->hw_base;
  153. if (dw8250_read32(base, UART_LSR) & UART_LSR_DR)
  154. {
  155. ch = dw8250_read32(base, UART_RX) & 0xff;
  156. }
  157. return ch;
  158. }
  159. static const struct rt_uart_ops _uart_ops =
  160. {
  161. dw8250_uart_configure,
  162. dw8250_uart_control,
  163. dw8250_uart_putc,
  164. dw8250_uart_getc,
  165. };
  166. static void rt_hw_uart_isr(int irqno, void *param)
  167. {
  168. unsigned int iir, status;
  169. struct rt_serial_device *serial = (struct rt_serial_device *)param;
  170. struct hw_uart_device *uart = (struct hw_uart_device *)serial->parent.user_data;
  171. iir = dw8250_read32(uart->hw_base, UART_IIR);
  172. /* If don't do this in non-DMA mode then the "RX TIMEOUT" interrupt will fire forever. */
  173. if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)
  174. {
  175. status = dw8250_read32(uart->hw_base, UART_LSR);
  176. if (!(status & (UART_LSR_DR | UART_LSR_BI)))
  177. {
  178. dw8250_read32(uart->hw_base, UART_RX);
  179. }
  180. }
  181. if (!(iir & UART_IIR_NO_INT))
  182. {
  183. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  184. }
  185. if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY)
  186. {
  187. /* Clear the USR */
  188. dw8250_read32(uart->hw_base, UART_USR);
  189. return;
  190. }
  191. }
  192. #if defined(BOARD_TYPE_MILKV_DUO)
  193. #ifdef BSP_USING_UART0
  194. static const char *pinname_whitelist_uart0_rx[] = {
  195. "UART0_RX",
  196. NULL,
  197. };
  198. static const char *pinname_whitelist_uart0_tx[] = {
  199. "UART0_TX",
  200. NULL,
  201. };
  202. #endif
  203. #ifdef BSP_USING_UART1
  204. static const char *pinname_whitelist_uart1_rx[] = {
  205. "IIC0_SDA",
  206. "UART0_RX",
  207. NULL,
  208. };
  209. static const char *pinname_whitelist_uart1_tx[] = {
  210. "IIC0_SCL",
  211. "UART0_TX",
  212. NULL,
  213. };
  214. #endif
  215. #ifdef BSP_USING_UART2
  216. static const char *pinname_whitelist_uart2_rx[] = {
  217. "IIC0_SDA",
  218. "SD1_D1",
  219. NULL,
  220. };
  221. static const char *pinname_whitelist_uart2_tx[] = {
  222. "IIC0_SCL",
  223. "SD1_D2",
  224. NULL,
  225. };
  226. #endif
  227. #ifdef BSP_USING_UART3
  228. static const char *pinname_whitelist_uart3_rx[] = {
  229. "SD1_D1",
  230. NULL,
  231. };
  232. static const char *pinname_whitelist_uart3_tx[] = {
  233. "SD1_D2",
  234. NULL,
  235. };
  236. #endif
  237. #ifdef BSP_USING_UART4
  238. static const char *pinname_whitelist_uart4_rx[] = {
  239. "SD1_GPIO0",
  240. NULL,
  241. };
  242. static const char *pinname_whitelist_uart4_tx[] = {
  243. "SD1_GPIO1",
  244. NULL,
  245. };
  246. #endif
  247. #elif defined(BOARD_TYPE_MILKV_DUO256M)
  248. #ifdef BSP_USING_UART0
  249. static const char *pinname_whitelist_uart0_rx[] = {
  250. "UART0_RX",
  251. NULL,
  252. };
  253. static const char *pinname_whitelist_uart0_tx[] = {
  254. "UART0_TX",
  255. NULL,
  256. };
  257. #endif
  258. #ifdef BSP_USING_UART1
  259. static const char *pinname_whitelist_uart1_rx[] = {
  260. "IIC0_SDA",
  261. "JTAG_CPU_TCK",
  262. "UART0_RX",
  263. NULL,
  264. };
  265. static const char *pinname_whitelist_uart1_tx[] = {
  266. "IIC0_SCL",
  267. "JTAG_CPU_TMS",
  268. "UART0_TX",
  269. NULL,
  270. };
  271. #endif
  272. #ifdef BSP_USING_UART2
  273. static const char *pinname_whitelist_uart2_rx[] = {
  274. "IIC0_SDA",
  275. "SD1_D1",
  276. NULL,
  277. };
  278. static const char *pinname_whitelist_uart2_tx[] = {
  279. "IIC0_SCL",
  280. "SD1_D2",
  281. NULL,
  282. };
  283. #endif
  284. #ifdef BSP_USING_UART3
  285. static const char *pinname_whitelist_uart3_rx[] = {
  286. "SD1_D1",
  287. NULL,
  288. };
  289. static const char *pinname_whitelist_uart3_tx[] = {
  290. "SD1_D2",
  291. NULL,
  292. };
  293. #endif
  294. #ifdef BSP_USING_UART4
  295. static const char *pinname_whitelist_uart4_rx[] = {
  296. NULL,
  297. };
  298. static const char *pinname_whitelist_uart4_tx[] = {
  299. NULL,
  300. };
  301. #endif
  302. #elif defined(BOARD_TYPE_MILKV_DUOS)
  303. #ifdef BSP_USING_UART0
  304. static const char *pinname_whitelist_uart0_rx[] = {
  305. "UART0_RX",
  306. NULL,
  307. };
  308. static const char *pinname_whitelist_uart0_tx[] = {
  309. "UART0_TX",
  310. NULL,
  311. };
  312. #endif
  313. #ifdef BSP_USING_UART1
  314. static const char *pinname_whitelist_uart1_rx[] = {
  315. "JTAG_CPU_TCK",
  316. "UART0_RX",
  317. NULL,
  318. };
  319. static const char *pinname_whitelist_uart1_tx[] = {
  320. "JTAG_CPU_TMS",
  321. "UART0_TX",
  322. "IIC0_SCL",
  323. NULL,
  324. };
  325. #endif
  326. #ifdef BSP_USING_UART2
  327. static const char *pinname_whitelist_uart2_rx[] = {
  328. "VIVO_D9",
  329. "VIVO_D5",
  330. "VIVO_CLK",
  331. "PWR_GPIO1",
  332. NULL,
  333. };
  334. static const char *pinname_whitelist_uart2_tx[] = {
  335. "VIVO_D10",
  336. "VIVO_D6",
  337. "VIVO_D2",
  338. "IIC0_SCL",
  339. "PWR_GPIO0",
  340. NULL,
  341. };
  342. #endif
  343. #ifdef BSP_USING_UART3
  344. static const char *pinname_whitelist_uart3_rx[] = {
  345. "ADC2",
  346. NULL,
  347. };
  348. static const char *pinname_whitelist_uart3_tx[] = {
  349. "ADC3",
  350. NULL,
  351. };
  352. #endif
  353. #ifdef BSP_USING_UART4
  354. static const char *pinname_whitelist_uart4_rx[] = {
  355. NULL,
  356. };
  357. static const char *pinname_whitelist_uart4_tx[] = {
  358. NULL,
  359. };
  360. #endif
  361. #else
  362. #error "Unsupported board type!"
  363. #endif
  364. int rt_hw_uart_init(void)
  365. {
  366. struct hw_uart_device* uart;
  367. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  368. config.baud_rate = 115200;
  369. #define BSP_INSTALL_UART_DEVICE(no) \
  370. uart = &_uart##no##_device; \
  371. _serial##no.ops = &_uart_ops; \
  372. _serial##no.config = config; \
  373. rt_hw_serial_register(&_serial##no, "uart" #no, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); \
  374. rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial##no, "uart" #no);
  375. #ifdef BSP_USING_UART0
  376. pinmux_config(BSP_UART0_RX_PINNAME, UART0_RX, pinname_whitelist_uart0_rx);
  377. pinmux_config(BSP_UART0_TX_PINNAME, UART0_TX, pinname_whitelist_uart0_tx);
  378. BSP_INSTALL_UART_DEVICE(0);
  379. uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000);
  380. #endif
  381. #ifdef BSP_USING_UART1
  382. pinmux_config(BSP_UART1_RX_PINNAME, UART1_RX, pinname_whitelist_uart1_rx);
  383. pinmux_config(BSP_UART1_TX_PINNAME, UART1_TX, pinname_whitelist_uart1_tx);
  384. BSP_INSTALL_UART_DEVICE(1);
  385. uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000);
  386. #endif
  387. #ifdef BSP_USING_UART2
  388. pinmux_config(BSP_UART2_RX_PINNAME, UART2_RX, pinname_whitelist_uart2_rx);
  389. pinmux_config(BSP_UART2_TX_PINNAME, UART2_TX, pinname_whitelist_uart2_tx);
  390. BSP_INSTALL_UART_DEVICE(2);
  391. uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000);
  392. #endif
  393. #ifdef BSP_USING_UART3
  394. pinmux_config(BSP_UART3_RX_PINNAME, UART3_RX, pinname_whitelist_uart3_rx);
  395. pinmux_config(BSP_UART3_TX_PINNAME, UART3_TX, pinname_whitelist_uart3_tx);
  396. BSP_INSTALL_UART_DEVICE(3);
  397. uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000);
  398. #endif
  399. #ifdef BSP_USING_UART4
  400. pinmux_config(BSP_UART4_RX_PINNAME, UART4_RX, pinname_whitelist_uart4_rx);
  401. pinmux_config(BSP_UART4_TX_PINNAME, UART4_TX, pinname_whitelist_uart4_tx);
  402. BSP_INSTALL_UART_DEVICE(4);
  403. uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000);
  404. #endif
  405. return 0;
  406. }