board.c 4.9 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2012-11-20 Bernard the first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <finsh.h>
  13. #include "board.h"
  14. #include <mmu.h>
  15. #include <interrupt.h>
  16. #ifdef RT_USING_VMM
  17. #include <vmm.h>
  18. static rt_uint32_t DMTIMER = 0;
  19. #define TIMER_HW_BASE (DMTIMER)
  20. #else
  21. #define TIMER_HW_BASE AM33XX_DMTIMER_7_REGS
  22. #endif
  23. #define DMTIMER_TCLR_AR (0x00000002u)
  24. #define DMTIMER_TCLR_CE (0x00000040u)
  25. #define DMTIMER_TCLR_PRE (0x00000020u)
  26. #define DMTIMER_TCLR_ST (0x00000001u)
  27. #define DMTIMER_IRQENABLE_SET_OVF_EN_FLAG (0x00000002u)
  28. #define DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG (0x00000002u)
  29. #define CM_DPLL_CLKSEL_CLK_CLKSEL (0x00000003u)
  30. #define CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3 (0x2u)
  31. #define CM_PER_CLKCTRL_MODULEMODE_ENABLE (0x2u)
  32. #define CM_PER_CLKCTRL_MODULEMODE (0x00000003u)
  33. #define CM_PER_CLKCTRL_IDLEST (0x00030000u)
  34. #define CM_PER_CLKCTRL_IDLEST_FUNC (0x0u)
  35. #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
  36. #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00004000u)
  37. #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (1<<13)
  38. static void rt_hw_timer_isr(int vector, void* param)
  39. {
  40. rt_tick_increase();
  41. DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
  42. }
  43. static void timer_clk_init(void)
  44. {
  45. unsigned long prcm_base;
  46. #ifdef RT_USING_VMM
  47. prcm_base = vmm_find_iomap("PRCM");
  48. #else
  49. prcm_base = AM33XX_PRCM_REGS;
  50. #endif
  51. /* software forced wakeup */
  52. CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
  53. /* Waiting for the L4LS clock */
  54. while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
  55. ;
  56. /* Select the clock source for the Timer2 instance. */
  57. CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
  58. /* 32k clock source */
  59. CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
  60. while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
  61. CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
  62. /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
  63. CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
  64. /* Waiting for MODULEMODE field to reflect the written value. */
  65. while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
  66. CM_PER_CLKCTRL_MODULEMODE_ENABLE);
  67. /*
  68. * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register
  69. * for the module is fully functional.
  70. */
  71. while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
  72. CM_PER_CLKCTRL_IDLEST_FUNC);
  73. /* Waiting for the L4LS clock */
  74. while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
  75. /* Waiting for the TIMER7 clock */
  76. while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
  77. }
  78. int rt_hw_timer_init(void)
  79. {
  80. rt_uint32_t counter;
  81. #ifdef RT_USING_VMM
  82. DMTIMER = vmm_find_iomap("TIMER7");
  83. #endif
  84. timer_clk_init();
  85. /* soft reset the timer */
  86. DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
  87. while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1)
  88. ;
  89. /* calculate count */
  90. counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
  91. /* set initial count */
  92. DMTIMER_TCRR(TIMER_HW_BASE) = counter;
  93. /* set reload count */
  94. DMTIMER_TLDR(TIMER_HW_BASE) = counter;
  95. /* set mode: auto reload */
  96. DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
  97. /* interrupt enable for match */
  98. DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
  99. DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
  100. rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
  101. rt_hw_interrupt_control(TINT7, 0, 0);
  102. rt_hw_interrupt_umask(TINT7);
  103. while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
  104. ;
  105. /* start timer */
  106. DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
  107. while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
  108. ;
  109. return 0;
  110. }
  111. INIT_BOARD_EXPORT(rt_hw_timer_init);
  112. /**
  113. * This function will initialize beaglebone board
  114. */
  115. void rt_hw_board_init(void)
  116. {
  117. rt_hw_mmu_init();
  118. /* init hardware interrupt */
  119. rt_hw_interrupt_init();
  120. /* Heap initialization */
  121. #if defined(RT_USING_HEAP)
  122. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  123. #endif
  124. rt_components_board_init();
  125. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  126. }
  127. void rt_hw_cpu_reset(void)
  128. {
  129. unsigned long prcm_base;
  130. #ifdef RT_USING_VMM
  131. prcm_base = vmm_find_iomap("PRCM");
  132. #else
  133. prcm_base = AM33XX_PRCM_REGS;
  134. #endif
  135. REG32(PRM_DEVICE(prcm_base)) = 0x1;
  136. RT_ASSERT(0);
  137. }
  138. MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reboot the cpu);