apm32f10x_dmc.h 7.2 KB

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  1. /*!
  2. * @file apm32f10x_dmc.h
  3. *
  4. * @brief This file contains all the prototypes,enumeration and macros for the DMC peripheral
  5. *
  6. * @version V1.0.1
  7. *
  8. * @date 2021-03-23
  9. *
  10. */
  11. #ifndef __APM32F10X_DMC_H
  12. #define __APM32F10X_DMC_H
  13. #include "apm32f10x.h"
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. /** @addtogroup Peripherals_Library Standard Peripheral Library
  18. @{
  19. */
  20. /** @addtogroup DMC_Driver DMC Driver
  21. @{
  22. */
  23. /** @addtogroup DMC_Enumerations Enumerations
  24. @{
  25. */
  26. /**
  27. * @brief Bank Address Width
  28. */
  29. typedef enum
  30. {
  31. DMC_BANK_WIDTH_1,
  32. DMC_BANK_WIDTH_2
  33. }DMC_BANK_WIDTH_T;
  34. /**
  35. * @brief Row Address Width
  36. */
  37. typedef enum
  38. {
  39. DMC_ROW_WIDTH_11 = 0x0A,
  40. DMC_ROW_WIDTH_12,
  41. DMC_ROW_WIDTH_13,
  42. DMC_ROW_WIDTH_14,
  43. DMC_ROW_WIDTH_15,
  44. DMC_ROW_WIDTH_16
  45. }DMC_ROW_WIDTH_T;
  46. /**
  47. * @brief Column Address Width
  48. */
  49. typedef enum
  50. {
  51. DMC_COL_WIDTH_8 = 0x07,
  52. DMC_COL_WIDTH_9,
  53. DMC_COL_WIDTH_10,
  54. DMC_COL_WIDTH_11,
  55. DMC_COL_WIDTH_12,
  56. DMC_COL_WIDTH_13,
  57. DMC_COL_WIDTH_14,
  58. DMC_COL_WIDTH_15
  59. }DMC_COL_WIDTH_T;
  60. /**
  61. * @brief CAS Latency Select
  62. */
  63. typedef enum
  64. {
  65. DMC_CAS_LATENCY_1,
  66. DMC_CAS_LATENCY_2,
  67. DMC_CAS_LATENCY_3,
  68. DMC_CAS_LATENCY_4
  69. }DMC_CAS_LATENCY_T;
  70. /**
  71. * @brief RAS Minimun Time Select
  72. */
  73. typedef enum
  74. {
  75. DMC_RAS_MINIMUM_1,
  76. DMC_RAS_MINIMUM_2,
  77. DMC_RAS_MINIMUM_3,
  78. DMC_RAS_MINIMUM_4,
  79. DMC_RAS_MINIMUM_5,
  80. DMC_RAS_MINIMUM_6,
  81. DMC_RAS_MINIMUM_7,
  82. DMC_RAS_MINIMUM_8,
  83. DMC_RAS_MINIMUM_9,
  84. DMC_RAS_MINIMUM_10,
  85. DMC_RAS_MINIMUM_11,
  86. DMC_RAS_MINIMUM_12,
  87. DMC_RAS_MINIMUM_13,
  88. DMC_RAS_MINIMUM_14,
  89. DMC_RAS_MINIMUM_15,
  90. DMC_RAS_MINIMUM_16
  91. }DMC_RAS_MINIMUM_T;
  92. /**
  93. * @brief RAS To CAS Delay Time Select
  94. */
  95. typedef enum
  96. {
  97. DMC_DELAY_TIME_1,
  98. DMC_DELAY_TIME_2,
  99. DMC_DELAY_TIME_3,
  100. DMC_DELAY_TIME_4,
  101. DMC_DELAY_TIME_5,
  102. DMC_DELAY_TIME_6,
  103. DMC_DELAY_TIME_7,
  104. DMC_DELAY_TIME_8
  105. }DMC_DELAY_TIME_T;
  106. /**
  107. * @brief Precharge Period Select
  108. */
  109. typedef enum
  110. {
  111. DMC_PRECHARGE_1,
  112. DMC_PRECHARGE_2,
  113. DMC_PRECHARGE_3,
  114. DMC_PRECHARGE_4,
  115. DMC_PRECHARGE_5,
  116. DMC_PRECHARGE_6,
  117. DMC_PRECHARGE_7,
  118. DMC_PRECHARGE_8
  119. }DMC_PRECHARGE_T;
  120. /**
  121. * @brief Last Data Next Precharge For Write Time Select
  122. */
  123. typedef enum
  124. {
  125. DMC_NEXT_PRECHARGE_1,
  126. DMC_NEXT_PRECHARGE_2,
  127. DMC_NEXT_PRECHARGE_3,
  128. DMC_NEXT_PRECHARGE_4
  129. }DMC_NEXT_PRECHARGE_T;
  130. /**
  131. * @brief Auto-Refresh Period Select
  132. */
  133. typedef enum
  134. {
  135. DMC_AUTO_REFRESH_1,
  136. DMC_AUTO_REFRESH_2,
  137. DMC_AUTO_REFRESH_3,
  138. DMC_AUTO_REFRESH_4,
  139. DMC_AUTO_REFRESH_5,
  140. DMC_AUTO_REFRESH_6,
  141. DMC_AUTO_REFRESH_7,
  142. DMC_AUTO_REFRESH_8,
  143. DMC_AUTO_REFRESH_9,
  144. DMC_AUTO_REFRESH_10,
  145. DMC_AUTO_REFRESH_11,
  146. DMC_AUTO_REFRESH_12,
  147. DMC_AUTO_REFRESH_13,
  148. DMC_AUTO_REFRESH_14,
  149. DMC_AUTO_REFRESH_15,
  150. DMC_AUTO_REFRESH_16,
  151. }DMC_AUTO_REFRESH_T;
  152. /**
  153. * @brief Active-to-active Command Period Select
  154. */
  155. typedef enum
  156. {
  157. DMC_ATA_CMD_1,
  158. DMC_ATA_CMD_2,
  159. DMC_ATA_CMD_3,
  160. DMC_ATA_CMD_4,
  161. DMC_ATA_CMD_5,
  162. DMC_ATA_CMD_6,
  163. DMC_ATA_CMD_7,
  164. DMC_ATA_CMD_8,
  165. DMC_ATA_CMD_9,
  166. DMC_ATA_CMD_10,
  167. DMC_ATA_CMD_11,
  168. DMC_ATA_CMD_12,
  169. DMC_ATA_CMD_13,
  170. DMC_ATA_CMD_14,
  171. DMC_ATA_CMD_15,
  172. DMC_ATA_CMD_16,
  173. }DMC_ATA_CMD_T;
  174. /**
  175. * @brief Clock PHASE
  176. */
  177. typedef enum
  178. {
  179. DMC_CLK_PHASE_NORMAL,
  180. DMC_CLK_PHASE_REVERSE
  181. }DMC_CLK_PHASE_T;
  182. /**
  183. * @brief DMC Memory Size
  184. */
  185. typedef enum
  186. {
  187. DMC_MEMORY_SIZE_0,
  188. DMC_MEMORY_SIZE_64KB,
  189. DMC_MEMORY_SIZE_128KB,
  190. DMC_MEMORY_SIZE_256KB,
  191. DMC_MEMORY_SIZE_512KB,
  192. DMC_MEMORY_SIZE_1MB,
  193. DMC_MEMORY_SIZE_2MB,
  194. DMC_MEMORY_SIZE_4MB,
  195. DMC_MEMORY_SIZE_8MB,
  196. DMC_MEMORY_SIZE_16MB,
  197. DMC_MEMORY_SIZE_32MB,
  198. DMC_MEMORY_SIZE_64MB,
  199. DMC_MEMORY_SIZE_128MB,
  200. DMC_MEMORY_SIZE_256MB,
  201. }DMC_MEMORY_SIZE_T;
  202. /**
  203. * @brief Open Banks Of Number
  204. */
  205. typedef enum
  206. {
  207. DMC_BANK_NUMBER_1,
  208. DMC_BANK_NUMBER_2,
  209. DMC_BANK_NUMBER_3,
  210. DMC_BANK_NUMBER_4,
  211. DMC_BANK_NUMBER_5,
  212. DMC_BANK_NUMBER_6,
  213. DMC_BANK_NUMBER_7,
  214. DMC_BANK_NUMBER_8,
  215. DMC_BANK_NUMBER_9,
  216. DMC_BANK_NUMBER_10,
  217. DMC_BANK_NUMBER_11,
  218. DMC_BANK_NUMBER_12,
  219. DMC_BANK_NUMBER_13,
  220. DMC_BANK_NUMBER_14,
  221. DMC_BANK_NUMBER_15,
  222. DMC_BANK_NUMBER_16,
  223. }DMC_BANK_NUMBER_T;
  224. /**
  225. * @brief Full refresh type
  226. */
  227. typedef enum
  228. {
  229. DMC_REFRESH_ROW_ONE, //!< Refresh one row
  230. DMC_REFRESH_ROW_ALL, //!< Refresh all row
  231. }DMC_REFRESH_T;
  232. /**
  233. * @brief Precharge type
  234. */
  235. typedef enum
  236. {
  237. DMC_PRECHARGE_IM, //!< Immediate precharge
  238. DMC_PRECHARGE_DELAY, //!< Delayed precharge
  239. }DMC_PRECHARE_T;
  240. /**@} end of group DMC_Enumerations*/
  241. /** @addtogroup DMC_Structure Data Structure
  242. @{
  243. */
  244. /**
  245. * @brief Timing config definition
  246. */
  247. typedef struct
  248. {
  249. uint32_t latencyCAS : 2; //!< DMC_CAS_LATENCY_T
  250. uint32_t tRAS : 4; //!< DMC_RAS_MINIMUM_T
  251. uint32_t tRCD : 3; //!< DMC_DELAY_TIME_T
  252. uint32_t tRP : 3; //!< DMC_PRECHARGE_T
  253. uint32_t tWR : 2; //!< DMC_NEXT_PRECHARGE_T
  254. uint32_t tARP : 4; //!< DMC_AUTO_REFRESH_T
  255. uint32_t tCMD : 4; //!< DMC_ATA_CMD_T
  256. uint32_t tXSR : 9; //!< auto-refresh commands, can be 0x000 to 0x1FF
  257. uint16_t tRFP : 16; //!< Refresh period, can be 0x0000 to 0xFFFF
  258. }DMC_TimingConfig_T;
  259. /**
  260. * @brief Config struct definition
  261. */
  262. typedef struct
  263. {
  264. DMC_MEMORY_SIZE_T memorySize; //!< Memory size(byte)
  265. DMC_BANK_WIDTH_T bankWidth; //!< Number of bank bits
  266. DMC_ROW_WIDTH_T rowWidth; //!< Number of row address bits
  267. DMC_COL_WIDTH_T colWidth; //!< Number of col address bits
  268. DMC_CLK_PHASE_T clkPhase; //!< Clock phase
  269. DMC_TimingConfig_T timing; //!< Timing
  270. }DMC_Config_T;
  271. /**@} end of group DMC_Structure*/
  272. /** @addtogroup DMC_Fuctions Fuctions
  273. @{
  274. */
  275. /** Enable / Disable */
  276. void DMC_Enable(void);
  277. void DMC_Disable(void);
  278. void DMC_EnableInit(void);
  279. /** Global config */
  280. void DMC_Config(DMC_Config_T *dmcConfig);
  281. void DMC_ConfigStructInit(DMC_Config_T *dmcConfig);
  282. /** Address */
  283. void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
  284. void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
  285. /** Timing */
  286. void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig);
  287. void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig);
  288. void DMC_ConfigStableTimePowerup(uint16_t stableTime);
  289. void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
  290. void DMC_ConfigRefreshPeriod(uint16_t period);
  291. /** Refresh mode */
  292. void DMC_EixtSlefRefreshMode(void);
  293. void DMC_EnterSlefRefreshMode(void);
  294. /** Config */
  295. void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
  296. void DMC_EnableUpdateMode(void);
  297. void DMC_EnterPowerdownMode(void);
  298. void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh);
  299. void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
  300. void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
  301. void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
  302. void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
  303. /** read flag */
  304. uint8_t DMC_ReadSelfRefreshStatus(void);
  305. /**@} end of group DMC_Fuctions*/
  306. /**@} end of group DMC_Driver*/
  307. /**@} end of group Peripherals_Library*/
  308. #ifdef __cplusplus
  309. }
  310. #endif
  311. #endif /* __APM32F10X_DMC_H */