apm32f10x_rcm.h 8.0 KB

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  1. /*!
  2. * @file apm32f10x_rcm.h
  3. *
  4. * @brief This file contains all the functions prototypes for the RCM firmware library
  5. *
  6. * @version V1.0.1
  7. *
  8. * @date 2021-03-23
  9. *
  10. */
  11. #ifndef __APM32F10X_RCM_H
  12. #define __APM32F10X_RCM_H
  13. #include "apm32f10x.h"
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. /** @addtogroup Peripherals_Library Standard Peripheral Library
  18. @{
  19. */
  20. /** @addtogroup RCM_Driver RCM Driver
  21. @{
  22. */
  23. /** @addtogroup RCM_Enumerations Enumerations
  24. @{
  25. */
  26. /**
  27. * @brief HSE state
  28. */
  29. typedef enum
  30. {
  31. RCM_HSE_CLOSE, //!< CLOSE HSE
  32. RCM_HSE_OPEN, //!< OPEN HSE
  33. RCM_HSE_BYPASS, //!< HSE BYPASS
  34. } RCM_HSE_T;
  35. /**
  36. * @brief PLL multiplication factor
  37. */
  38. typedef enum
  39. {
  40. RCM_PLLMF_2,
  41. RCM_PLLMF_3,
  42. RCM_PLLMF_4,
  43. RCM_PLLMF_5,
  44. RCM_PLLMF_6,
  45. RCM_PLLMF_7,
  46. RCM_PLLMF_8,
  47. RCM_PLLMF_9,
  48. RCM_PLLMF_10,
  49. RCM_PLLMF_11,
  50. RCM_PLLMF_12,
  51. RCM_PLLMF_13,
  52. RCM_PLLMF_14,
  53. RCM_PLLMF_15,
  54. RCM_PLLMF_16,
  55. } RCM_PLLMF_T;
  56. /**
  57. * @brief System clock select
  58. */
  59. typedef enum
  60. {
  61. RCM_SYSCLK_SEL_HSI,
  62. RCM_SYSCLK_SEL_HSE,
  63. RCM_SYSCLK_SEL_PLL
  64. } RCM_SYSCLK_SEL_T;
  65. /**
  66. * @brief AHB divider Number
  67. */
  68. typedef enum
  69. {
  70. RCM_AHB_DIV_1 = 7,
  71. RCM_AHB_DIV_2,
  72. RCM_AHB_DIV_4,
  73. RCM_AHB_DIV_8,
  74. RCM_AHB_DIV_16,
  75. RCM_AHB_DIV_64,
  76. RCM_AHB_DIV_128,
  77. RCM_AHB_DIV_256,
  78. RCM_AHB_DIV_512,
  79. } RCM_AHB_DIV_T;
  80. /**
  81. * @brief APB divider Number
  82. */
  83. typedef enum
  84. {
  85. RCM_APB_DIV_1 = 3,
  86. RCM_APB_DIV_2,
  87. RCM_APB_DIV_4,
  88. RCM_APB_DIV_8,
  89. RCM_APB_DIV_16
  90. } RCM_APB_DIV_T;
  91. /**
  92. * @brief USB divider Number
  93. */
  94. typedef enum
  95. {
  96. RCM_USB_DIV_1_5,
  97. RCM_USB_DIV_1,
  98. RCM_USB_DIV_2,
  99. RCM_USB_DIV_2_5 //!< (Only for High-density devices for APM32F103xx)
  100. } RCM_USB_DIV_T;
  101. /**
  102. * @brief FPU divider Number
  103. */
  104. typedef enum
  105. {
  106. RCM_FPU_DIV_1,
  107. RCM_FPU_DIV_2,
  108. } RCM_FPU_DIV_T;
  109. /**
  110. * @brief ADC divider Number
  111. */
  112. typedef enum
  113. {
  114. RCM_PCLK2_DIV_2,
  115. RCM_PCLK2_DIV_4,
  116. RCM_PCLK2_DIV_6,
  117. RCM_PCLK2_DIV_8,
  118. } RCM_PCLK2_DIV_T;
  119. /**
  120. * @brief LSE State
  121. */
  122. typedef enum
  123. {
  124. RCM_LSE_CLOSE,
  125. RCM_LSE_OPEN,
  126. RCM_LSE_BYPASS
  127. } RCM_LSE_T;
  128. /**
  129. * @brief RTC clock select
  130. */
  131. typedef enum
  132. {
  133. RCM_RTCCLK_LSE = 1,
  134. RCM_RTCCLK_LSI,
  135. RCM_RTCCLK_HSE_DIV_128
  136. } RCM_RTCCLK_T;
  137. /**
  138. * @brief Clock output control
  139. */
  140. typedef enum
  141. {
  142. RCM_MCOCLK_NO_CLOCK = 3,
  143. RCM_MCOCLK_SYSCLK,
  144. RCM_MCOCLK_HSI,
  145. RCM_MCOCLK_HSE,
  146. RCM_MCOCLK_PLLCLK_DIV_2,
  147. } RCM_MCOCLK_T;
  148. /**
  149. * @brief PLL entry clock select
  150. */
  151. typedef enum
  152. {
  153. RCM_PLLSEL_HSI_DIV_2 = 0,
  154. RCM_PLLSEL_HSE = 1,
  155. RCM_PLLSEL_HSE_DIV2 = 3,
  156. } RCM_PLLSEL_T;
  157. /**
  158. * @brief RCM Interrupt Source
  159. */
  160. typedef enum
  161. {
  162. RCM_INT_LSIRDY = BIT0, //!< LSI ready interrupt
  163. RCM_INT_LSERDY = BIT1, //!< LSE ready interrupt
  164. RCM_INT_HSIRDY = BIT2, //!< HSI ready interrupt
  165. RCM_INT_HSERDY = BIT3, //!< HSE ready interrupt
  166. RCM_INT_PLLRDY = BIT4, //!< PLL ready interrupt
  167. RCM_INT_CSS = BIT7 //!< Clock security system interrupt
  168. } RCM_INT_T;
  169. /**
  170. * @brief AHB peripheral
  171. */
  172. typedef enum
  173. {
  174. RCM_AHB_PERIPH_DMA1 = BIT0,
  175. RCM_AHB_PERIPH_DMA2 = BIT1,
  176. RCM_AHB_PERIPH_SRAM = BIT2,
  177. RCM_AHB_PERIPH_FPU = BIT3,
  178. RCM_AHB_PERIPH_FMC = BIT4,
  179. RCM_AHB_PERIPH_QSPI = BIT5,
  180. RCM_AHB_PERIPH_CRC = BIT6,
  181. RCM_AHB_PERIPH_EMMC = BIT8,
  182. RCM_AHB_PERIPH_SDIO = BIT10,
  183. } RCM_AHB_PERIPH_T;
  184. /**
  185. * @brief AHB2 peripheral
  186. */
  187. typedef enum
  188. {
  189. RCM_APB2_PERIPH_AFIO = BIT0,
  190. RCM_APB2_PERIPH_GPIOA = BIT2,
  191. RCM_APB2_PERIPH_GPIOB = BIT3,
  192. RCM_APB2_PERIPH_GPIOC = BIT4,
  193. RCM_APB2_PERIPH_GPIOD = BIT5,
  194. RCM_APB2_PERIPH_GPIOE = BIT6,
  195. RCM_APB2_PERIPH_GPIOF = BIT7,
  196. RCM_APB2_PERIPH_GPIOG = BIT8,
  197. RCM_APB2_PERIPH_ADC1 = BIT9,
  198. RCM_APB2_PERIPH_ADC2 = BIT10,
  199. RCM_APB2_PERIPH_TMR1 = BIT11,
  200. RCM_APB2_PERIPH_SPI1 = BIT12,
  201. RCM_APB2_PERIPH_TMR8 = BIT13,
  202. RCM_APB2_PERIPH_USART1 = BIT14,
  203. RCM_APB2_PERIPH_ADC3 = BIT15,
  204. } RCM_APB2_PERIPH_T;
  205. /**
  206. * @brief AHB1 peripheral
  207. */
  208. typedef enum
  209. {
  210. RCM_APB1_PERIPH_TMR2 = BIT0,
  211. RCM_APB1_PERIPH_TMR3 = BIT1,
  212. RCM_APB1_PERIPH_TMR4 = BIT2,
  213. RCM_APB1_PERIPH_TMR5 = BIT3,
  214. RCM_APB1_PERIPH_TMR6 = BIT4,
  215. RCM_APB1_PERIPH_TMR7 = BIT5,
  216. RCM_APB1_PERIPH_WWDT = BIT11,
  217. RCM_APB1_PERIPH_SPI2 = BIT14,
  218. RCM_APB1_PERIPH_SPI3 = BIT15,
  219. RCM_APB1_PERIPH_USART2 = BIT17,
  220. RCM_APB1_PERIPH_USART3 = BIT18,
  221. RCM_APB1_PERIPH_UART4 = BIT19,
  222. RCM_APB1_PERIPH_UART5 = BIT20,
  223. RCM_APB1_PERIPH_I2C1 = BIT21,
  224. RCM_APB1_PERIPH_I2C2 = BIT22,
  225. RCM_APB1_PERIPH_USB = BIT23,
  226. RCM_APB1_PERIPH_CAN1 = BIT25,
  227. RCM_APB1_PERIPH_CAN2 = BIT26,
  228. RCM_APB1_PERIPH_BAKR = BIT27,
  229. RCM_APB1_PERIPH_PMU = BIT28,
  230. RCM_APB1_PERIPH_DAC = BIT29,
  231. } RCM_APB1_PERIPH_T;
  232. /**
  233. * @brief RCM FLAG define
  234. */
  235. typedef enum
  236. {
  237. RCM_FLAG_HSIRDY = 0x001, //!< HSI Ready Flag
  238. RCM_FLAG_HSERDY = 0x011, //!< HSE Ready Flag
  239. RCM_FLAG_PLLRDY = 0x019, //!< PLL Ready Flag
  240. RCM_FLAG_LSERDY = 0x101, //!< LSE Ready Flag
  241. RCM_FLAG_LSIRDY = 0x201, //!< LSI Ready Flag
  242. RCM_FLAG_PINRST = 0x21A, //!< PIN reset flag
  243. RCM_FLAG_PORRST = 0x21B, //!< POR/PDR reset flag
  244. RCM_FLAG_SWRST = 0x21C, //!< Software reset flag
  245. RCM_FLAG_IWDTRST = 0x21D, //!< Independent watchdog reset flag
  246. RCM_FLAG_WWDTRST = 0x21E, //!< Window watchdog reset flag
  247. RCM_FLAG_LPRRST = 0x21F, //!< Low-power reset flag
  248. } RCM_FLAG_T;
  249. /**@} end of group RCM_Enumerations*/
  250. /** @addtogroup RCM_Fuctions Fuctions
  251. @{
  252. */
  253. /** Function description */
  254. /** RCM Reset */
  255. void RCM_Reset(void);
  256. /** HSE clock */
  257. void RCM_ConfigHSE(RCM_HSE_T state);
  258. uint8_t RCM_WaitHSEReady(void);
  259. /** HSI clock */
  260. void RCM_SetHSITrim(uint8_t HSITrim);
  261. void RCM_EnableHSI(void);
  262. void RCM_DisableHSI(void);
  263. /** LSE and LSI clock */
  264. void RCM_ConfigLSE(RCM_LSE_T state);
  265. void RCM_EnableLSI(void);
  266. void RCM_DisableLSI(void);
  267. /** PLL clock */
  268. void RCM_ConfigPLL(RCM_PLLSEL_T pllSelect, RCM_PLLMF_T pllMf);
  269. void RCM_EnablePLL(void);
  270. void RCM_DisablePLL(void);
  271. /** Clock Security System */
  272. void RCM_EnableCSS(void);
  273. void RCM_DisableCSS(void);
  274. void RCM_ConfigMCO(RCM_MCOCLK_T mcoClock);
  275. void RCM_ConfigSYSCLK(RCM_SYSCLK_SEL_T sysClkSelect);
  276. RCM_SYSCLK_SEL_T RCM_ReadSYSCLKSource(void);
  277. /** Config clock prescaler of AHB, APB1, APB2, USB and ADC */
  278. void RCM_ConfigAHB(RCM_AHB_DIV_T AHBDiv);
  279. void RCM_ConfigAPB1(RCM_APB_DIV_T APB1Div);
  280. void RCM_ConfigAPB2(RCM_APB_DIV_T APB2Div);
  281. void RCM_ConfigUSBCLK(RCM_USB_DIV_T USBDiv);
  282. void RCM_ConfigFPUCLK(RCM_FPU_DIV_T FPUDiv);
  283. void RCM_ConfigADCCLK(RCM_PCLK2_DIV_T ADCDiv);
  284. /** RTC clock */
  285. void RCM_ConfigRTCCLK(RCM_RTCCLK_T rtcClkSelect);
  286. void RCM_EnableRTCCLK(void);
  287. void RCM_DisableRTCCLK(void);
  288. /** Reads the clock frequency */
  289. uint32_t RCM_ReadSYSCLKFreq(void);
  290. uint32_t RCM_ReadHCLKFreq(void);
  291. void RCM_ReadPCLKFreq(uint32_t* PCLK1, uint32_t* PCLK2);
  292. uint32_t RCM_ReadADCCLKFreq(void);
  293. /** Enable or disable Periph Clock */
  294. void RCM_EnableAHBPeriphClock(uint32_t AHBPeriph);
  295. void RCM_DisableAHBPeriphClock(uint32_t AHBPeriph);
  296. void RCM_EnableAPB2PeriphClock(uint32_t APB2Periph);
  297. void RCM_DisableAPB2PeriphClock(uint32_t APB2Periph);
  298. void RCM_EnableAPB1PeriphClock(uint32_t APB1Periph);
  299. void RCM_DisableAPB1PeriphClock(uint32_t APB1Periph);
  300. /** Enable or disable Periph Reset */
  301. void RCM_EnableAPB2PeriphReset(uint32_t APB2Periph);
  302. void RCM_DisableAPB2PeriphReset(uint32_t APB2Periph);
  303. void RCM_EnableAPB1PeriphReset(uint32_t APB1Periph);
  304. void RCM_DisableAPB1PeriphReset(uint32_t APB1Periph);
  305. /** Backup domain reset */
  306. void RCM_EnableBackupReset(void);
  307. void RCM_DisableBackupReset(void);
  308. /** Interrupts and flags */
  309. void RCM_EnableInterrupt(uint32_t interrupt);
  310. void RCM_DisableInterrupt(uint32_t interrupt);
  311. uint8_t RCM_ReadStatusFlag(RCM_FLAG_T flag);
  312. void RCM_ClearStatusFlag(void);
  313. uint8_t RCM_ReadIntFlag(RCM_INT_T flag);
  314. void RCM_ClearIntFlag(uint32_t flag);
  315. /**@} end of group RCM_Fuctions*/
  316. /**@} end of group RCM_Driver*/
  317. /**@} end of group Peripherals_Library*/
  318. #ifdef __cplusplus
  319. }
  320. #endif
  321. #endif /* __APM32F10X_RCM_H */