apm32f10x_dmc.c 12 KB

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  1. /*!
  2. * @file apm32f10x_dmc.c
  3. *
  4. * @brief This file contains all the functions for the DMC controler peripheral
  5. *
  6. * @version V1.0.4
  7. *
  8. * @date 2022-12-01
  9. *
  10. * @attention
  11. *
  12. * Copyright (C) 2020-2022 Geehy Semiconductor
  13. *
  14. * You may not use this file except in compliance with the
  15. * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  16. *
  17. * The program is only for reference, which is distributed in the hope
  18. * that it will be useful and instructional for customers to develop
  19. * their software. Unless required by applicable law or agreed to in
  20. * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  21. * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
  22. * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
  23. * and limitations under the License.
  24. */
  25. #ifdef APM32F10X_HD
  26. #include "apm32f10x_dmc.h"
  27. /** @addtogroup APM32F10x_StdPeriphDriver
  28. @{
  29. */
  30. /** @addtogroup DMC_Driver DMC Driver
  31. * @brief DMC driver modules
  32. @{
  33. */
  34. /** @defgroup DMC_Functions Functions
  35. @{
  36. */
  37. /*!
  38. * @brief DMC controler configuration
  39. *
  40. * @param dmcConfig: pointer to a DMC_Config_T structure
  41. *
  42. * @retval None
  43. */
  44. void DMC_Config(DMC_Config_T* dmcConfig)
  45. {
  46. DMC->SW_B.MCSW = 1;
  47. while (!DMC->CTRL1_B.INIT);
  48. DMC->CFG_B.BAWCFG = dmcConfig->bankWidth;
  49. DMC->CFG_B.RAWCFG = dmcConfig->rowWidth;
  50. DMC->CFG_B.CAWCFG = dmcConfig->colWidth;
  51. DMC->MASK_B.MSIZESEL = dmcConfig->memorySize;
  52. DMC->CTRL2_B.CPHACFG = dmcConfig->clkPhase;
  53. DMC_ConfigTiming(&dmcConfig->timing);
  54. DMC->CTRL1_B.MODESET = 1;
  55. while (!DMC->CTRL1_B.MODESET);
  56. DMC->CTRL2_B.RDDEN = 1;
  57. DMC->CTRL2_B.RDDCFG = 7;
  58. }
  59. /*!
  60. * @brief Fills each dmcConfig member with its default value
  61. *
  62. * @param dmcConfig: pointer to a DMC_Config_T structure
  63. *
  64. * @retval None
  65. */
  66. void DMC_ConfigStructInit(DMC_Config_T* dmcConfig)
  67. {
  68. dmcConfig->bankWidth = DMC_BANK_WIDTH_2;
  69. dmcConfig->clkPhase = DMC_CLK_PHASE_REVERSE;
  70. dmcConfig->colWidth = DMC_COL_WIDTH_10;
  71. dmcConfig->rowWidth = DMC_ROW_WIDTH_13;
  72. dmcConfig->memorySize = DMC_MEMORY_SIZE_8MB;
  73. DMC_ConfigTimingStructInit(&dmcConfig->timing);
  74. }
  75. /*!
  76. * @brief Timing configuration
  77. *
  78. * @param timingConfig: pointer to a DMC_TimingConfig_T structure
  79. *
  80. * @retval None
  81. */
  82. void DMC_ConfigTiming(DMC_TimingConfig_T* timingConfig)
  83. {
  84. DMC->TIM0_B.RASMINTSEL = timingConfig->tRAS;
  85. DMC->TIM0_B.DTIMSEL = timingConfig->tRCD;
  86. DMC->TIM0_B.PCPSEL = timingConfig->tRP;
  87. DMC->TIM0_B.WRTIMSEL = timingConfig->tWR;
  88. DMC->TIM0_B.ARPSEL = timingConfig->tARP;
  89. DMC->TIM0_B.ATACP = timingConfig->tCMD;
  90. DMC->TIM0_B.CASLSEL0 = timingConfig->latencyCAS & 0x03;
  91. DMC->TIM0_B.ECASLSEL1 = (timingConfig->latencyCAS >> 2) & 0x01;
  92. DMC->TIM0_B.XSR0 = timingConfig->tXSR & 0X0F;
  93. DMC->TIM0_B.EXSR1 = (timingConfig->tXSR >> 4) & 0X1F;
  94. DMC->REF_B.RCYCCFG = timingConfig->tRFP;
  95. }
  96. /*!
  97. * @brief Fills each config member with its default value
  98. *
  99. * @param timingConfig: pointer to a DMC_TimingConfig_T structure
  100. *
  101. * @retval None
  102. */
  103. void DMC_ConfigTimingStructInit(DMC_TimingConfig_T* timingConfig)
  104. {
  105. timingConfig->latencyCAS = DMC_CAS_LATENCY_3;
  106. timingConfig->tARP = DMC_AUTO_REFRESH_10;
  107. timingConfig->tRAS = DMC_RAS_MINIMUM_5;
  108. timingConfig->tCMD = DMC_ATA_CMD_7;
  109. timingConfig->tRCD = DMC_DELAY_TIME_2;
  110. timingConfig->tRP = DMC_PRECHARGE_2;
  111. timingConfig->tWR = DMC_NEXT_PRECHARGE_2;
  112. timingConfig->tXSR = 6;
  113. timingConfig->tRFP = 0xC3;
  114. }
  115. /*!
  116. * @brief Set number of bank bits
  117. *
  118. * @param bankWidth: Specifies the bank bits number
  119. * This parameter can be one of the following values:
  120. * @arg DMC_BANK_WIDTH_1
  121. * @arg DMC_BANK_WIDTH_2
  122. * @retval None
  123. */
  124. void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth)
  125. {
  126. DMC->CFG_B.BAWCFG = bankWidth;
  127. }
  128. /*!
  129. * @brief Set address bus width
  130. *
  131. * @param rowWidth: Specifies the row address bits number
  132. * This parameter can be one of the following values:
  133. * @arg DMC_ROW_WIDTH_11
  134. * @arg DMC_ROW_WIDTH_12
  135. * @arg DMC_ROW_WIDTH_13
  136. * @arg DMC_ROW_WIDTH_14
  137. * @arg DMC_ROW_WIDTH_15
  138. * @arg DMC_ROW_WIDTH_16
  139. * @param colWidth: Specifies the column address bits number
  140. * This parameter can be one of the following values:
  141. * @arg DMC_COL_WIDTH_8
  142. * @arg DMC_COL_WIDTH_9
  143. * @arg DMC_COL_WIDTH_10
  144. * @arg DMC_COL_WIDTH_11
  145. * @arg DMC_COL_WIDTH_12
  146. * @arg DMC_COL_WIDTH_13
  147. * @arg DMC_COL_WIDTH_14
  148. * @arg DMC_COL_WIDTH_15
  149. * @retval None
  150. */
  151. void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth)
  152. {
  153. DMC->CFG_B.RAWCFG = rowWidth;
  154. DMC->CFG_B.CAWCFG = colWidth;
  155. }
  156. /*!
  157. * @brief Set stable time after power up
  158. *
  159. * @param stableTime: Numper of the clock, can be 0x0000 to 0xFFFF
  160. *
  161. * @retval None
  162. */
  163. void DMC_ConfigStableTimePowerup(uint16_t stableTime)
  164. {
  165. DMC->TIM1_B.STBTIM = stableTime;
  166. }
  167. /*!
  168. * @brief Number of auto-refreshes during initialization
  169. *
  170. * @param num: Number of auto-refreshes can 1 to 16
  171. * This parameter can be one of the following values:
  172. * @arg DMC_AUTO_REFRESH_1
  173. * @arg DMC_AUTO_REFRESH_2
  174. * ......
  175. * @arg DMC_AUTO_REFRESH_15
  176. * @arg DMC_AUTO_REFRESH_16
  177. *
  178. * @retval None
  179. */
  180. void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num)
  181. {
  182. DMC->TIM1_B.ARNUMCFG = num;
  183. }
  184. /*!
  185. * @brief Number of DMC internal banks to be open at any time;
  186. *
  187. * @param num: Number of banks can 1 to 16
  188. * This parameter can be one of the following values:
  189. * @arg DMC_BANK_NUMBER_1
  190. * @arg DMC_BANK_NUMBER_2
  191. * ......
  192. * @arg DMC_BANK_NUMBER_15
  193. * @arg DMC_BANK_NUMBER_16
  194. * @retval None
  195. */
  196. void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num)
  197. {
  198. DMC->CTRL1_B.BANKNUMCFG = num;
  199. }
  200. /*!
  201. * @brief Read self-refresh status
  202. *
  203. * @param None
  204. *
  205. * @retval The status of self-refresh (SET or RESET)
  206. */
  207. uint8_t DMC_ReadSelfRefreshStatus(void)
  208. {
  209. uint8_t ret;
  210. ret = DMC->CTRL1_B.SRMFLG ? SET : RESET;
  211. return ret;
  212. }
  213. /*!
  214. * @brief Set update mode bit
  215. *
  216. * @param None
  217. *
  218. * @retval None
  219. */
  220. void DMC_EnableUpdateMode(void)
  221. {
  222. DMC->CTRL1_B.MODESET = 1;
  223. }
  224. /*!
  225. * @brief Enter power down mode
  226. *
  227. * @param None
  228. *
  229. * @retval None
  230. */
  231. void DMC_EnterPowerdownMode(void)
  232. {
  233. DMC->CTRL1_B.PDMEN = 1;
  234. }
  235. /*!
  236. * @brief Exit self-refresh mode
  237. *
  238. * @param None
  239. *
  240. * @retval None
  241. */
  242. void DMC_EixtSlefRefreshMode(void)
  243. {
  244. DMC->CTRL1_B.SRMEN = 0;
  245. }
  246. /*!
  247. * @brief Enter self-refresh mode
  248. *
  249. * @param None
  250. *
  251. * @retval None
  252. */
  253. void DMC_EnterSlefRefreshMode(void)
  254. {
  255. DMC->CTRL1_B.SRMEN = 1;
  256. }
  257. /*!
  258. * @brief Enable Accelerate Module
  259. *
  260. * @param None
  261. *
  262. * @retval None
  263. */
  264. void DMC_EnableAccelerateModule(void)
  265. {
  266. DMC->CTRL2_B.BUFFEN = BIT_SET;
  267. }
  268. /*!
  269. * @brief Disable Accelerate Module
  270. *
  271. * @param None
  272. *
  273. * @retval None
  274. */
  275. void DMC_DisableAccelerateModule(void)
  276. {
  277. DMC->CTRL2_B.BUFFEN = BIT_RESET;
  278. }
  279. /*!
  280. * @brief Init DMC
  281. *
  282. * @param None
  283. *
  284. * @retval None
  285. */
  286. void DMC_EnableInit(void)
  287. {
  288. DMC->CTRL1_B.INIT = 1;
  289. }
  290. /*!
  291. * @brief Set refresh type before enter self-refresh
  292. *
  293. * @param refresh: Specifies the refresh type
  294. * The parameter can be one of following values:
  295. * @arg DMC_REFRESH_ROW_ONE: Refresh one row
  296. * @arg DMC_REFRESH_ROW_ALL: Refresh all row
  297. *
  298. * @retval None
  299. */
  300. void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh)
  301. {
  302. DMC->CTRL1_B.FRBSREN = refresh;
  303. }
  304. /*!
  305. * @brief Set refresh type after exit self-refresh
  306. *
  307. * @param refresh: Specifies the refresh type
  308. * The parameter can be one of following values:
  309. * @arg DMC_REFRESH_ROW_ONE: Refresh one row
  310. * @arg DMC_REFRESH_ROW_ALL: Refresh all row
  311. *
  312. * @retval None
  313. */
  314. void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh)
  315. {
  316. DMC->CTRL1_B.FRASREN = refresh;
  317. }
  318. /*!
  319. * @brief Config precharge type
  320. *
  321. * @param precharge: Specifies the precharge type
  322. * The parameter can be one of following values:
  323. * @arg DMC_PRECHARGE_IM: Immediate precharge
  324. * @arg DMC_PRECHARGE_DELAY: Delayed precharge
  325. *
  326. * @retval None
  327. */
  328. void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge)
  329. {
  330. DMC->CTRL1_B.PCACFG = precharge;
  331. }
  332. /*!
  333. * @brief Config refresh period
  334. *
  335. * @param period: Specifies the refresh period, can be 0x0000 to 0xFFFF
  336. *
  337. * @retval None
  338. */
  339. void DMC_ConfigRefreshPeriod(uint16_t period)
  340. {
  341. DMC->REF_B.RCYCCFG = period;
  342. }
  343. /*!
  344. * @brief Config memory size
  345. *
  346. * @param memorySize: Specifies memory size
  347. * The parameter can be one of following values:
  348. * @arg DMC_MEMORY_SIZE_0: Memory size is no link
  349. * @arg DMC_MEMORY_SIZE_64KB: Memory size is 64KB
  350. * @arg DMC_MEMORY_SIZE_128KB: Memory size is 128KB
  351. * @arg DMC_MEMORY_SIZE_256KB: Memory size is 256KB
  352. * @arg DMC_MEMORY_SIZE_512KB: Memory size is 512KB
  353. * @arg DMC_MEMORY_SIZE_1MB: Memory size is 1MB
  354. * @arg DMC_MEMORY_SIZE_2MB: Memory size is 2MB
  355. * @arg DMC_MEMORY_SIZE_4MB: Memory size is 4MB
  356. * @arg DMC_MEMORY_SIZE_8MB: Memory size is 8MB
  357. * @arg DMC_MEMORY_SIZE_16MB: Memory size is 16MB
  358. * @arg DMC_MEMORY_SIZE_32MB: Memory size is 32MB
  359. * @arg DMC_MEMORY_SIZE_64MB: Memory size is 64MB
  360. * @arg DMC_MEMORY_SIZE_128MB: Memory size is 128MB
  361. * @arg DMC_MEMORY_SIZE_256MB: Memory size is 256MB
  362. *
  363. * @retval None
  364. */
  365. void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize)
  366. {
  367. DMC->MASK_B.MSIZESEL = memorySize;
  368. }
  369. /*!
  370. * @brief Enable DMC controler
  371. *
  372. * @param None
  373. *
  374. * @retval None
  375. */
  376. void DMC_Enable(void)
  377. {
  378. DMC->SW_B.MCSW = 1;
  379. }
  380. /*!
  381. * @brief Disable DMC controler
  382. *
  383. * @param None
  384. *
  385. * @retval None
  386. */
  387. void DMC_Disable(void)
  388. {
  389. DMC->SW_B.MCSW = 0;
  390. }
  391. /*!
  392. * @brief Set DMC clock phase
  393. *
  394. * @param clkPhase: Specifies clock phase
  395. * The parameter can be one of following values:
  396. * @arg DMC_CLK_PHASE_NORMAL: Clock phase is normal
  397. * @arg DMC_CLK_PHASE_REVERSE: Clock phase is reverse
  398. *
  399. * @retval None
  400. */
  401. void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase)
  402. {
  403. DMC->CTRL2_B.CPHACFG = clkPhase;
  404. }
  405. /*!
  406. * @brief Set DMC WRAP burst
  407. *
  408. * @param burst: WRAP burst Type Selection
  409. * The parameter can be one of following values:
  410. * @arg DMC_WRAPB_4: wrap4 burst transfer
  411. * @arg DMC_WRAPB_8: wrap8 burst transfer
  412. *
  413. * @retval None
  414. */
  415. void DMC_ConfigWRAPB(DMC_WRPB_T burst)
  416. {
  417. DMC->CTRL2_B.WRPBSEL = burst;
  418. }
  419. /**@} end of group DMC_Functions*/
  420. /**@} end of group DMC_Driver */
  421. /**@} end of group APM32F10x_StdPeriphDriver*/
  422. #endif //defined APM32F10X_HD