apm32s10x_dma.h 6.3 KB

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  1. /*!
  2. * @file apm32s10x_dma.h
  3. *
  4. * @brief This file contains all the functions prototypes for the DMA firmware library
  5. *
  6. * @version V1.0.1
  7. *
  8. * @date 2022-12-31
  9. *
  10. * @attention
  11. *
  12. * Copyright (C) 2022-2023 Geehy Semiconductor
  13. *
  14. * You may not use this file except in compliance with the
  15. * GEEHY COPYRIGHT NOTICE (GEEHY SOFTWARE PACKAGE LICENSE).
  16. *
  17. * The program is only for reference, which is distributed in the hope
  18. * that it will be usefull and instructional for customers to develop
  19. * their software. Unless required by applicable law or agreed to in
  20. * writing, the program is distributed on an "AS IS" BASIS, WITHOUT
  21. * ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
  22. * See the GEEHY SOFTWARE PACKAGE LICENSE for the governing permissions
  23. * and limitations under the License.
  24. */
  25. /* Define to prevent recursive inclusion */
  26. #ifndef __APM32S10X_DMA_H
  27. #define __APM32S10X_DMA_H
  28. #ifdef __cplusplus
  29. extern "C" {
  30. #endif
  31. /* Includes */
  32. #include "apm32s10x.h"
  33. /** @addtogroup APM32S10x_StdPeriphDriver
  34. @{
  35. */
  36. /** @addtogroup DMA_Driver DMA Driver
  37. @{
  38. */
  39. /** @defgroup DMA_Enumerations Enumerations
  40. @{
  41. */
  42. /**
  43. * @brief DMA Transmission direction
  44. */
  45. typedef enum
  46. {
  47. DMA_DIR_PERIPHERAL_SRC,
  48. DMA_DIR_PERIPHERAL_DST
  49. } DMA_DIR_T;
  50. /**
  51. * @brief DMA Peripheral address increment
  52. */
  53. typedef enum
  54. {
  55. DMA_PERIPHERAL_INC_DISABLE,
  56. DMA_PERIPHERAL_INC_ENABLE
  57. } DMA_PERIPHERAL_INC_T;
  58. /**
  59. * @brief DMA Memory address increment
  60. */
  61. typedef enum
  62. {
  63. DMA_MEMORY_INC_DISABLE,
  64. DMA_MEMORY_INC_ENABLE
  65. } DMA_MEMORY_INC_T;
  66. /**
  67. * @brief DMA Peripheral Data Size
  68. */
  69. typedef enum
  70. {
  71. DMA_PERIPHERAL_DATA_SIZE_BYTE,
  72. DMA_PERIPHERAL_DATA_SIZE_HALFWORD,
  73. DMA_PERIPHERAL_DATA_SIZE_WOED
  74. } DMA_PERIPHERAL_DATA_SIZE_T;
  75. /**
  76. * @brief DMA Memory Data Size
  77. */
  78. typedef enum
  79. {
  80. DMA_MEMORY_DATA_SIZE_BYTE,
  81. DMA_MEMORY_DATA_SIZE_HALFWORD,
  82. DMA_MEMORY_DATA_SIZE_WOED
  83. } DMA_MEMORY_DATA_SIZE_T;
  84. /**
  85. * @brief DMA Mode
  86. */
  87. typedef enum
  88. {
  89. DMA_MODE_NORMAL,
  90. DMA_MODE_CIRCULAR
  91. } DMA_LOOP_MODE_T;
  92. /**
  93. * @brief DMA priority level
  94. */
  95. typedef enum
  96. {
  97. DMA_PRIORITY_LOW,
  98. DMA_PRIORITY_MEDIUM,
  99. DMA_PRIORITY_HIGH,
  100. DMA_PRIORITY_VERYHIGH
  101. } DMA_PRIORITY_T;
  102. /**
  103. * @brief DMA Memory to Memory
  104. */
  105. typedef enum
  106. {
  107. DMA_M2MEN_DISABLE,
  108. DMA_M2MEN_ENABLE
  109. } DMA_M2MEN_T;
  110. /**
  111. * @brief DMA interrupt
  112. */
  113. typedef enum
  114. {
  115. DMA_INT_TC = 0x00000002,
  116. DMA_INT_HT = 0x00000004,
  117. DMA_INT_TERR = 0x00000008
  118. } DMA_INT_T;
  119. /**
  120. * @brief DMA Flag
  121. */
  122. typedef enum
  123. {
  124. DMA1_FLAG_GINT1 = 0x00000001,
  125. DMA1_FLAG_TC1 = 0x00000002,
  126. DMA1_FLAG_HT1 = 0x00000004,
  127. DMA1_FLAG_TERR1 = 0x00000008,
  128. DMA1_FLAG_GINT2 = 0x00000010,
  129. DMA1_FLAG_TC2 = 0x00000020,
  130. DMA1_FLAG_HT2 = 0x00000040,
  131. DMA1_FLAG_TERR2 = 0x00000080,
  132. DMA1_FLAG_GINT3 = 0x00000100,
  133. DMA1_FLAG_TC3 = 0x00000200,
  134. DMA1_FLAG_HT3 = 0x00000400,
  135. DMA1_FLAG_TERR3 = 0x00000800,
  136. DMA1_FLAG_GINT4 = 0x00001000,
  137. DMA1_FLAG_TC4 = 0x00002000,
  138. DMA1_FLAG_HT4 = 0x00004000,
  139. DMA1_FLAG_TERR4 = 0x00008000,
  140. DMA1_FLAG_GINT5 = 0x00010000,
  141. DMA1_FLAG_TC5 = 0x00020000,
  142. DMA1_FLAG_HT5 = 0x00040000,
  143. DMA1_FLAG_TERR5 = 0x00080000,
  144. DMA1_FLAG_GINT6 = 0x00100000,
  145. DMA1_FLAG_TC6 = 0x00200000,
  146. DMA1_FLAG_HT6 = 0x00400000,
  147. DMA1_FLAG_TERR6 = 0x00800000,
  148. DMA1_FLAG_GINT7 = 0x01000000,
  149. DMA1_FLAG_TC7 = 0x02000000,
  150. DMA1_FLAG_HT7 = 0x04000000,
  151. DMA1_FLAG_TERR7 = 0x08000000,
  152. } DMA_FLAG_T;
  153. /**
  154. * @brief DMA Interrupt Flag
  155. */
  156. typedef enum
  157. {
  158. DMA1_INT_FLAG_GINT1 = 0x00000001,
  159. DMA1_INT_FLAG_TC1 = 0x00000002,
  160. DMA1_INT_FLAG_HT1 = 0x00000004,
  161. DMA1_INT_FLAG_TERR1 = 0x00000008,
  162. DMA1_INT_FLAG_GINT2 = 0x00000010,
  163. DMA1_INT_FLAG_TC2 = 0x00000020,
  164. DMA1_INT_FLAG_HT2 = 0x00000040,
  165. DMA1_INT_FLAG_TERR2 = 0x00000080,
  166. DMA1_INT_FLAG_GINT3 = 0x00000100,
  167. DMA1_INT_FLAG_TC3 = 0x00000200,
  168. DMA1_INT_FLAG_HT3 = 0x00000400,
  169. DMA1_INT_FLAG_TERR3 = 0x00000800,
  170. DMA1_INT_FLAG_GINT4 = 0x00001000,
  171. DMA1_INT_FLAG_TC4 = 0x00002000,
  172. DMA1_INT_FLAG_HT4 = 0x00004000,
  173. DMA1_INT_FLAG_TERR4 = 0x00008000,
  174. DMA1_INT_FLAG_GINT5 = 0x00010000,
  175. DMA1_INT_FLAG_TC5 = 0x00020000,
  176. DMA1_INT_FLAG_HT5 = 0x00040000,
  177. DMA1_INT_FLAG_TERR5 = 0x00080000,
  178. DMA1_INT_FLAG_GINT6 = 0x00100000,
  179. DMA1_INT_FLAG_TC6 = 0x00200000,
  180. DMA1_INT_FLAG_HT6 = 0x00400000,
  181. DMA1_INT_FLAG_TERR6 = 0x00800000,
  182. DMA1_INT_FLAG_GINT7 = 0x01000000,
  183. DMA1_INT_FLAG_TC7 = 0x02000000,
  184. DMA1_INT_FLAG_HT7 = 0x04000000,
  185. DMA1_INT_FLAG_TERR7 = 0x08000000,
  186. } DMA_INT_FLAG_T;
  187. /**@} end of group DMA_Enumerations */
  188. /** @defgroup DMA_Structures Structures
  189. @{
  190. */
  191. /**
  192. * @brief DMA Configure structure definition
  193. */
  194. typedef struct
  195. {
  196. uint32_t peripheralBaseAddr;
  197. uint32_t memoryBaseAddr;
  198. DMA_DIR_T dir;
  199. uint32_t bufferSize;
  200. DMA_PERIPHERAL_INC_T peripheralInc;
  201. DMA_MEMORY_INC_T memoryInc;
  202. DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize;
  203. DMA_MEMORY_DATA_SIZE_T memoryDataSize;
  204. DMA_LOOP_MODE_T loopMode;
  205. DMA_PRIORITY_T priority;
  206. DMA_M2MEN_T M2M;
  207. } DMA_Config_T;
  208. /**@} end of group DMA_Structures */
  209. /** @defgroup DMA_Functions Functions
  210. @{
  211. */
  212. /* Reset and configuration */
  213. void DMA_Reset(DMA_Channel_T* channel);
  214. void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
  215. void DMA_ConfigStructInit(DMA_Config_T* dmaConfig);
  216. void DMA_Enable(DMA_Channel_T* channel);
  217. void DMA_Disable(DMA_Channel_T* channel);
  218. /* Data number */
  219. void DMA_ConfigDataNumber(DMA_Channel_T* channel, uint16_t dataNumber);
  220. uint16_t DMA_ReadDataNumber(DMA_Channel_T* channel);
  221. /* Interrupt and flag */
  222. void DMA_EnableInterrupt(DMA_Channel_T* channel, uint32_t interrupt);
  223. void DMA_DisableInterrupt(DMA_Channel_T* channel, uint32_t interrupt);
  224. uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
  225. void DMA_ClearStatusFlag(uint32_t flag);
  226. uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
  227. void DMA_ClearIntFlag(uint32_t flag);
  228. /**@} end of group DMA_Functions */
  229. /**@} end of group DMA_Driver */
  230. /**@} end of group APM32S10x_StdPeriphDriver */
  231. #ifdef __cplusplus
  232. }
  233. #endif
  234. #endif /* __APM32S10X_DMA_H */