dma_config.h 5.6 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023-01-31 shelton first version
  9. */
  10. #ifndef __DMA_CONFIG_H__
  11. #define __DMA_CONFIG_H__
  12. #include <rtthread.h>
  13. #ifdef __cplusplus
  14. extern "C" {
  15. #endif
  16. /* DMA1 channel1 */
  17. /* DMA1 channel2 */
  18. #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
  19. #define SPI1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler
  20. #define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  21. #define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL2
  22. #define SPI1_RX_DMA_IRQ DMA1_Channel3_2_IRQn
  23. #define SPI1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2
  24. #define SPI1_RX_DMA_REQ_ID DMA_FLEXIBLE_SPI1_RX
  25. #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL)
  26. #define UART1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler
  27. #define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  28. #define UART1_RX_DMA_CHANNEL DMA1_CHANNEL2
  29. #define UART1_RX_DMA_IRQ DMA1_Channel3_2_IRQn
  30. #define UART1_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL2
  31. #define UART1_RX_DMA_REQ_ID DMA_FLEXIBLE_UART1_RX
  32. #endif
  33. /* DMA1 channel3 */
  34. #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
  35. #define SPI1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler
  36. #define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  37. #define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL3
  38. #define SPI1_TX_DMA_IRQ DMA1_Channel3_2_IRQn
  39. #define SPI1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3
  40. #define SPI1_TX_DMA_REQ_ID DMA_FLEXIBLE_SPI1_TX
  41. #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL)
  42. #define UART1_TX_RX_DMA_IRQHandler DMA1_Channel3_2_IRQHandler
  43. #define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  44. #define UART1_TX_DMA_CHANNEL DMA1_CHANNEL3
  45. #define UART1_TX_DMA_IRQ DMA1_Channel3_2_IRQn
  46. #define UART1_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL3
  47. #define UART1_TX_DMA_REQ_ID DMA_FLEXIBLE_UART1_TX
  48. #endif
  49. /* DMA1 channel4 */
  50. #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL)
  51. #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  52. #define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  53. #define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL4
  54. #define SPI2_RX_DMA_IRQ DMA1_Channel7_4_IRQn
  55. #define SPI2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4
  56. #define SPI2_RX_DMA_REQ_ID DMA_FLEXIBLE_SPI2_RX
  57. #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
  58. #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  59. #define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  60. #define UART2_RX_DMA_CHANNEL DMA1_CHANNEL4
  61. #define UART2_RX_DMA_IRQ DMA1_Channel7_4_IRQn
  62. #define UART2_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL4
  63. #define UART2_RX_DMA_REQ_ID DMA_FLEXIBLE_UART2_RX
  64. #endif
  65. /* DMA1 channel5 */
  66. #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL)
  67. #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  68. #define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  69. #define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL5
  70. #define SPI2_TX_DMA_IRQ DMA1_Channel7_4_IRQn
  71. #define SPI2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5
  72. #define SPI2_TX_DMA_REQ_ID DMA_FLEXIBLE_SPI2_TX
  73. #elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL)
  74. #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  75. #define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  76. #define UART2_TX_DMA_CHANNEL DMA1_CHANNEL5
  77. #define UART2_TX_DMA_IRQ DMA1_Channel7_4_IRQn
  78. #define UART2_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL5
  79. #define UART2_TX_DMA_REQ_ID DMA_FLEXIBLE_UART2_TX
  80. #endif
  81. /* DMA1 channel6 */
  82. #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
  83. #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  84. #define SPI3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  85. #define SPI3_RX_DMA_CHANNEL DMA1_CHANNEL6
  86. #define SPI3_RX_DMA_IRQ DMA1_Channel7_4_IRQn
  87. #define SPI3_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL6
  88. #define SPI3_RX_DMA_REQ_ID DMA_FLEXIBLE_SPI3_RX
  89. #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL)
  90. #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  91. #define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  92. #define UART3_RX_DMA_CHANNEL DMA1_CHANNEL6
  93. #define UART3_RX_DMA_IRQ DMA1_Channel7_4_IRQn
  94. #define UART3_RX_DMA_FLEX_CHANNEL FLEX_CHANNEL6
  95. #define UART3_RX_DMA_REQ_ID DMA_FLEXIBLE_UART3_RX
  96. #endif
  97. /* DMA1 channel7 */
  98. #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
  99. #define SPI3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  100. #define SPI3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  101. #define SPI3_TX_DMA_CHANNEL DMA1_CHANNEL7
  102. #define SPI3_TX_DMA_IRQ DMA1_Channel7_4_IRQn
  103. #define SPI3_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL7
  104. #define SPI3_TX_DMA_REQ_ID DMA_FLEXIBLE_SPI3_TX
  105. #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_CHANNEL)
  106. #define UART3_2_TX_RX_DMA_IRQHandler DMA1_Channel7_4_IRQHandler
  107. #define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
  108. #define UART3_TX_DMA_CHANNEL DMA1_CHANNEL7
  109. #define UART3_TX_DMA_IRQ DMA1_Channel7_4_IRQn
  110. #define UART3_TX_DMA_FLEX_CHANNEL FLEX_CHANNEL7
  111. #define UART3_TX_DMA_REQ_ID DMA_FLEXIBLE_UART3_TX
  112. #endif
  113. #ifdef __cplusplus
  114. }
  115. #endif
  116. #endif /* __DMA_CONFIG_H__ */