drv_usart.c 28 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-05-16 shelton first version
  9. * 2022-11-10 shelton support uart dma
  10. * 2023-01-31 shelton add support f421/f425
  11. * 2023-04-08 shelton add support f423
  12. * 2023-10-18 shelton add support f402/f405
  13. */
  14. #include "drv_common.h"
  15. #include "drv_usart.h"
  16. #include "drv_config.h"
  17. #ifdef RT_USING_SERIAL
  18. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
  19. !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
  20. !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
  21. !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
  22. #error "Please define at least one BSP_USING_UARTx"
  23. #endif
  24. enum {
  25. #ifdef BSP_USING_UART1
  26. UART1_INDEX,
  27. #endif
  28. #ifdef BSP_USING_UART2
  29. UART2_INDEX,
  30. #endif
  31. #ifdef BSP_USING_UART3
  32. UART3_INDEX,
  33. #endif
  34. #ifdef BSP_USING_UART4
  35. UART4_INDEX,
  36. #endif
  37. #ifdef BSP_USING_UART5
  38. UART5_INDEX,
  39. #endif
  40. #ifdef BSP_USING_UART6
  41. UART6_INDEX,
  42. #endif
  43. #ifdef BSP_USING_UART7
  44. UART7_INDEX,
  45. #endif
  46. #ifdef BSP_USING_UART8
  47. UART8_INDEX,
  48. #endif
  49. };
  50. static struct at32_uart uart_config[] = {
  51. #ifdef BSP_USING_UART1
  52. UART1_CONFIG,
  53. #endif
  54. #ifdef BSP_USING_UART2
  55. UART2_CONFIG,
  56. #endif
  57. #ifdef BSP_USING_UART3
  58. UART3_CONFIG,
  59. #endif
  60. #ifdef BSP_USING_UART4
  61. UART4_CONFIG,
  62. #endif
  63. #ifdef BSP_USING_UART5
  64. UART5_CONFIG,
  65. #endif
  66. #ifdef BSP_USING_UART6
  67. UART6_CONFIG,
  68. #endif
  69. #ifdef BSP_USING_UART7
  70. UART7_CONFIG,
  71. #endif
  72. #ifdef BSP_USING_UART8
  73. UART8_CONFIG,
  74. #endif
  75. };
  76. #ifdef RT_SERIAL_USING_DMA
  77. static void at32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  78. #endif
  79. static rt_err_t at32_configure(struct rt_serial_device *serial,
  80. struct serial_configure *cfg) {
  81. usart_data_bit_num_type data_bit;
  82. usart_stop_bit_num_type stop_bit;
  83. usart_parity_selection_type parity_mode;
  84. usart_hardware_flow_control_type flow_control;
  85. RT_ASSERT(serial != RT_NULL);
  86. RT_ASSERT(cfg != RT_NULL);
  87. struct at32_uart *instance = rt_container_of(serial, struct at32_uart, serial);
  88. RT_ASSERT(instance != RT_NULL);
  89. at32_msp_usart_init((void *)instance->uart_x);
  90. usart_receiver_enable(instance->uart_x, TRUE);
  91. usart_transmitter_enable(instance->uart_x, TRUE);
  92. switch (cfg->data_bits) {
  93. case DATA_BITS_8:
  94. data_bit = USART_DATA_8BITS;
  95. break;
  96. case DATA_BITS_9:
  97. data_bit = USART_DATA_9BITS;
  98. break;
  99. default:
  100. data_bit = USART_DATA_8BITS;
  101. break;
  102. }
  103. switch (cfg->stop_bits) {
  104. case STOP_BITS_1:
  105. stop_bit = USART_STOP_1_BIT;
  106. break;
  107. case STOP_BITS_2:
  108. stop_bit = USART_STOP_2_BIT;
  109. break;
  110. default:
  111. stop_bit = USART_STOP_1_BIT;
  112. break;
  113. }
  114. switch (cfg->parity) {
  115. case PARITY_NONE:
  116. parity_mode = USART_PARITY_NONE;
  117. break;
  118. case PARITY_ODD:
  119. parity_mode = USART_PARITY_ODD;
  120. break;
  121. case PARITY_EVEN:
  122. parity_mode = USART_PARITY_EVEN;
  123. break;
  124. default:
  125. parity_mode = USART_PARITY_NONE;
  126. break;
  127. }
  128. switch (cfg->flowcontrol) {
  129. case RT_SERIAL_FLOWCONTROL_NONE:
  130. flow_control = USART_HARDWARE_FLOW_NONE;
  131. break;
  132. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  133. flow_control = USART_HARDWARE_FLOW_RTS_CTS;
  134. break;
  135. default:
  136. flow_control = USART_HARDWARE_FLOW_NONE;
  137. break;
  138. }
  139. #ifdef RT_SERIAL_USING_DMA
  140. if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
  141. instance->last_index = 0;
  142. }
  143. #endif
  144. usart_hardware_flow_control_set(instance->uart_x, flow_control);
  145. usart_parity_selection_config(instance->uart_x, parity_mode);
  146. usart_init(instance->uart_x, cfg->baud_rate, data_bit, stop_bit);
  147. usart_enable(instance->uart_x, TRUE);
  148. return RT_EOK;
  149. }
  150. static rt_err_t at32_control(struct rt_serial_device *serial, int cmd, void *arg) {
  151. struct at32_uart *instance;
  152. #ifdef RT_SERIAL_USING_DMA
  153. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  154. #endif
  155. RT_ASSERT(serial != RT_NULL);
  156. instance = rt_container_of(serial, struct at32_uart, serial);
  157. RT_ASSERT(instance != RT_NULL);
  158. switch (cmd) {
  159. case RT_DEVICE_CTRL_CLR_INT:
  160. nvic_irq_disable(instance->irqn);
  161. usart_interrupt_enable(instance->uart_x, USART_RDBF_INT, FALSE);
  162. #ifdef RT_SERIAL_USING_DMA
  163. /* disable DMA */
  164. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
  165. {
  166. nvic_irq_disable(instance->dma_rx->dma_irqn);
  167. dma_reset(instance->dma_rx->dma_channel);
  168. }
  169. else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
  170. {
  171. nvic_irq_disable(instance->dma_tx->dma_irqn);
  172. dma_reset(instance->dma_tx->dma_channel);
  173. }
  174. #endif
  175. break;
  176. case RT_DEVICE_CTRL_SET_INT:
  177. nvic_irq_enable(instance->irqn, 1, 0);
  178. usart_interrupt_enable(instance->uart_x, USART_RDBF_INT, TRUE);
  179. break;
  180. #ifdef RT_SERIAL_USING_DMA
  181. case RT_DEVICE_CTRL_CONFIG:
  182. at32_dma_config(serial, ctrl_arg);
  183. break;
  184. #endif
  185. }
  186. return RT_EOK;
  187. }
  188. static int at32_putc(struct rt_serial_device *serial, char ch) {
  189. struct at32_uart *instance;
  190. RT_ASSERT(serial != RT_NULL);
  191. instance = rt_container_of(serial, struct at32_uart, serial);
  192. RT_ASSERT(instance != RT_NULL);
  193. usart_data_transmit(instance->uart_x, (uint8_t)ch);
  194. while (usart_flag_get(instance->uart_x, USART_TDC_FLAG) == RESET);
  195. return 1;
  196. }
  197. static int at32_getc(struct rt_serial_device *serial) {
  198. int ch;
  199. struct at32_uart *instance;
  200. RT_ASSERT(serial != RT_NULL);
  201. instance = rt_container_of(serial, struct at32_uart, serial);
  202. RT_ASSERT(instance != RT_NULL);
  203. ch = -1;
  204. if (usart_flag_get(instance->uart_x, USART_RDBF_FLAG) != RESET) {
  205. ch = usart_data_receive(instance->uart_x) & 0xff;
  206. }
  207. return ch;
  208. }
  209. #ifdef RT_SERIAL_USING_DMA
  210. static void _uart_dma_receive(struct at32_uart *instance, rt_uint8_t *buffer, rt_uint32_t size)
  211. {
  212. dma_channel_type* dma_channel = instance->dma_rx->dma_channel;
  213. dma_channel->dtcnt = size;
  214. dma_channel->paddr = (rt_uint32_t)&(instance->uart_x->dt);
  215. dma_channel->maddr = (rt_uint32_t)buffer;
  216. /* enable usart interrupt */
  217. usart_interrupt_enable(instance->uart_x, USART_PERR_INT, TRUE);
  218. usart_interrupt_enable(instance->uart_x, USART_IDLE_INT, TRUE);
  219. /* enable transmit complete interrupt */
  220. dma_interrupt_enable(dma_channel, DMA_FDT_INT, TRUE);
  221. /* enable dma receive */
  222. usart_dma_receiver_enable(instance->uart_x, TRUE);
  223. /* enable dma channel */
  224. dma_channel_enable(dma_channel, TRUE);
  225. }
  226. static void _uart_dma_transmit(struct at32_uart *instance, rt_uint8_t *buffer, rt_uint32_t size)
  227. {
  228. /* wait before transfer complete */
  229. while(instance->dma_tx->dma_done == RT_FALSE);
  230. dma_channel_type *dma_channel = instance->dma_tx->dma_channel;
  231. dma_channel->dtcnt = size;
  232. dma_channel->paddr = (rt_uint32_t)&(instance->uart_x->dt);
  233. dma_channel->maddr = (rt_uint32_t)buffer;
  234. /* enable transmit complete interrupt */
  235. dma_interrupt_enable(dma_channel, DMA_FDT_INT, TRUE);
  236. /* enable dma transmit */
  237. usart_dma_transmitter_enable(instance->uart_x, TRUE);
  238. /* mark dma flag */
  239. instance->dma_tx->dma_done = RT_FALSE;
  240. /* enable dma channel */
  241. dma_channel_enable(dma_channel, TRUE);
  242. }
  243. static void at32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  244. {
  245. dma_init_type dma_init_struct;
  246. dma_channel_type *dma_channel = NULL;
  247. struct rt_serial_rx_fifo *rx_fifo;
  248. struct at32_uart *instance;
  249. struct dma_config *dma_config;
  250. RT_ASSERT(serial != RT_NULL);
  251. instance = rt_container_of(serial, struct at32_uart, serial);
  252. RT_ASSERT(instance != RT_NULL);
  253. RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
  254. if (RT_DEVICE_FLAG_DMA_RX == flag)
  255. {
  256. dma_channel = instance->dma_rx->dma_channel;
  257. dma_config = instance->dma_rx;
  258. }
  259. else /* RT_DEVICE_FLAG_DMA_TX == flag */
  260. {
  261. dma_channel = instance->dma_tx->dma_channel;
  262. dma_config = instance->dma_tx;
  263. }
  264. crm_periph_clock_enable(dma_config->dma_clock, TRUE);
  265. dma_default_para_init(&dma_init_struct);
  266. dma_init_struct.peripheral_inc_enable = FALSE;
  267. dma_init_struct.memory_inc_enable = TRUE;
  268. dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
  269. dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
  270. dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
  271. if (RT_DEVICE_FLAG_DMA_RX == flag)
  272. {
  273. dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
  274. dma_init_struct.loop_mode_enable = TRUE;
  275. }
  276. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  277. {
  278. dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
  279. dma_init_struct.loop_mode_enable = FALSE;
  280. }
  281. dma_reset(dma_channel);
  282. dma_init(dma_channel, &dma_init_struct);
  283. #if defined (SOC_SERIES_AT32F425)
  284. dma_flexible_config(dma_config->dma_x, dma_config->flex_channel, \
  285. (dma_flexible_request_type)dma_config->request_id);
  286. #endif
  287. #if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
  288. defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
  289. defined (SOC_SERIES_AT32F405)
  290. dmamux_enable(dma_config->dma_x, TRUE);
  291. dmamux_init(dma_config->dmamux_channel, (dmamux_requst_id_sel_type)dma_config->request_id);
  292. #endif
  293. /* enable interrupt */
  294. if (flag == RT_DEVICE_FLAG_DMA_RX)
  295. {
  296. rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  297. /* start dma transfer */
  298. _uart_dma_receive(instance, rx_fifo->buffer, serial->config.bufsz);
  299. }
  300. /* dma irq should set in dma tx mode */
  301. nvic_irq_enable(dma_config->dma_irqn, 0, 0);
  302. nvic_irq_enable(instance->irqn, 1, 0);
  303. }
  304. static rt_ssize_t at32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  305. {
  306. struct at32_uart *instance;
  307. RT_ASSERT(serial != RT_NULL);
  308. instance = rt_container_of(serial, struct at32_uart, serial);
  309. RT_ASSERT(instance != RT_NULL);
  310. RT_ASSERT(buf != RT_NULL);
  311. if (size == 0)
  312. {
  313. return 0;
  314. }
  315. if (RT_SERIAL_DMA_TX == direction)
  316. {
  317. _uart_dma_transmit(instance, buf, size);
  318. }
  319. return size;
  320. }
  321. #endif
  322. static const struct rt_uart_ops at32_uart_ops = {
  323. at32_configure,
  324. at32_control,
  325. at32_putc,
  326. at32_getc,
  327. #ifdef RT_SERIAL_USING_DMA
  328. at32_dma_transmit,
  329. #endif
  330. };
  331. #ifdef RT_SERIAL_USING_DMA
  332. void dma_rx_isr(struct rt_serial_device *serial)
  333. {
  334. volatile rt_uint32_t reg_sts = 0, index = 0;
  335. rt_size_t recv_total_index, recv_len;
  336. rt_base_t level;
  337. struct at32_uart *instance;
  338. RT_ASSERT(serial != RT_NULL);
  339. instance = rt_container_of(serial, struct at32_uart, serial);
  340. RT_ASSERT(instance != RT_NULL);
  341. reg_sts = instance->dma_rx->dma_x->sts;
  342. index = instance->dma_rx->channel_index;
  343. if (((reg_sts & (DMA_FDT_FLAG << (4 * (index - 1)))) != RESET) ||
  344. ((reg_sts & (DMA_HDT_FLAG << (4 * (index - 1)))) != RESET))
  345. {
  346. /* clear dma flag */
  347. instance->dma_rx->dma_x->clr |= (rt_uint32_t)(DMA_FDT_FLAG << (4 * (index - 1))) | (DMA_HDT_FLAG << (4 * (index - 1)));
  348. level = rt_hw_interrupt_disable();
  349. recv_total_index = serial->config.bufsz - dma_data_number_get(instance->dma_rx->dma_channel);
  350. if (recv_total_index == 0)
  351. {
  352. recv_len = serial->config.bufsz - instance->last_index;
  353. }
  354. else
  355. {
  356. recv_len = recv_total_index - instance->last_index;
  357. }
  358. instance->last_index = recv_total_index;
  359. rt_hw_interrupt_enable(level);
  360. if (recv_len)
  361. {
  362. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  363. }
  364. }
  365. }
  366. void dma_tx_isr(struct rt_serial_device *serial)
  367. {
  368. volatile rt_uint32_t reg_sts = 0, index = 0;
  369. rt_size_t trans_total_index;
  370. rt_base_t level;
  371. struct at32_uart *instance;
  372. RT_ASSERT(serial != RT_NULL);
  373. instance = rt_container_of(serial, struct at32_uart, serial);
  374. RT_ASSERT(instance != RT_NULL);
  375. reg_sts = instance->dma_tx->dma_x->sts;
  376. index = instance->dma_tx->channel_index;
  377. if ((reg_sts & (DMA_FDT_FLAG << (4 * (index - 1)))) != RESET)
  378. {
  379. /* mark dma flag */
  380. instance->dma_tx->dma_done = RT_TRUE;
  381. /* clear dma flag */
  382. instance->dma_tx->dma_x->clr |= (rt_uint32_t)(DMA_FDT_FLAG << (4 * (index - 1)));
  383. /* disable dma tx channel */
  384. dma_channel_enable(instance->dma_tx->dma_channel, FALSE);
  385. level = rt_hw_interrupt_disable();
  386. trans_total_index = dma_data_number_get(instance->dma_tx->dma_channel);
  387. rt_hw_interrupt_enable(level);
  388. if (trans_total_index == 0)
  389. {
  390. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
  391. }
  392. }
  393. }
  394. #endif
  395. static void usart_isr(struct rt_serial_device *serial) {
  396. struct at32_uart *instance;
  397. #ifdef RT_SERIAL_USING_DMA
  398. rt_size_t recv_total_index, recv_len;
  399. rt_base_t level;
  400. #endif
  401. RT_ASSERT(serial != RT_NULL);
  402. instance = rt_container_of(serial, struct at32_uart, serial);
  403. RT_ASSERT(instance != RT_NULL);
  404. if (usart_flag_get(instance->uart_x, USART_RDBF_FLAG) != RESET) {
  405. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  406. }
  407. #ifdef RT_SERIAL_USING_DMA
  408. else if (usart_flag_get(instance->uart_x, USART_IDLEF_FLAG) != RESET)
  409. {
  410. /* clear idle flag */
  411. usart_data_receive(instance->uart_x);
  412. level = rt_hw_interrupt_disable();
  413. recv_total_index = serial->config.bufsz - dma_data_number_get(instance->dma_rx->dma_channel);
  414. recv_len = recv_total_index - instance->last_index;
  415. instance->last_index = recv_total_index;
  416. rt_hw_interrupt_enable(level);
  417. if (recv_len)
  418. {
  419. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  420. }
  421. }
  422. #endif
  423. else
  424. {
  425. if (usart_flag_get(instance->uart_x, USART_CTSCF_FLAG) != RESET) {
  426. usart_flag_clear(instance->uart_x, USART_CTSCF_FLAG);
  427. }
  428. if (usart_flag_get(instance->uart_x, USART_BFF_FLAG) != RESET) {
  429. usart_flag_clear(instance->uart_x, USART_BFF_FLAG);
  430. }
  431. if (usart_flag_get(instance->uart_x, USART_TDC_FLAG) != RESET) {
  432. usart_flag_clear(instance->uart_x, USART_TDC_FLAG);
  433. }
  434. }
  435. }
  436. #ifdef BSP_USING_UART1
  437. void UART1_IRQHandler(void) {
  438. rt_interrupt_enter();
  439. usart_isr(&uart_config[UART1_INDEX].serial);
  440. rt_interrupt_leave();
  441. }
  442. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  443. void UART1_RX_DMA_IRQHandler(void)
  444. {
  445. /* enter interrupt */
  446. rt_interrupt_enter();
  447. dma_rx_isr(&uart_config[UART1_INDEX].serial);
  448. /* leave interrupt */
  449. rt_interrupt_leave();
  450. }
  451. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  452. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  453. void UART1_TX_DMA_IRQHandler(void)
  454. {
  455. /* enter interrupt */
  456. rt_interrupt_enter();
  457. dma_tx_isr(&uart_config[UART1_INDEX].serial);
  458. /* leave interrupt */
  459. rt_interrupt_leave();
  460. }
  461. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  462. #endif
  463. #ifdef BSP_USING_UART2
  464. void UART2_IRQHandler(void) {
  465. rt_interrupt_enter();
  466. usart_isr(&uart_config[UART2_INDEX].serial);
  467. rt_interrupt_leave();
  468. }
  469. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  470. void UART2_RX_DMA_IRQHandler(void)
  471. {
  472. /* enter interrupt */
  473. rt_interrupt_enter();
  474. dma_rx_isr(&uart_config[UART2_INDEX].serial);
  475. /* leave interrupt */
  476. rt_interrupt_leave();
  477. }
  478. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  479. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  480. void UART2_TX_DMA_IRQHandler(void)
  481. {
  482. /* enter interrupt */
  483. rt_interrupt_enter();
  484. dma_tx_isr(&uart_config[UART2_INDEX].serial);
  485. /* leave interrupt */
  486. rt_interrupt_leave();
  487. }
  488. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  489. #endif
  490. #ifdef BSP_USING_UART3
  491. void UART3_IRQHandler(void) {
  492. rt_interrupt_enter();
  493. usart_isr(&uart_config[UART3_INDEX].serial);
  494. rt_interrupt_leave();
  495. }
  496. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  497. void UART3_RX_DMA_IRQHandler(void)
  498. {
  499. /* enter interrupt */
  500. rt_interrupt_enter();
  501. dma_rx_isr(&uart_config[UART3_INDEX].serial);
  502. /* leave interrupt */
  503. rt_interrupt_leave();
  504. }
  505. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA) */
  506. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  507. void UART3_TX_DMA_IRQHandler(void)
  508. {
  509. /* enter interrupt */
  510. rt_interrupt_enter();
  511. dma_tx_isr(&uart_config[UART3_INDEX].serial);
  512. /* leave interrupt */
  513. rt_interrupt_leave();
  514. }
  515. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA) */
  516. #endif
  517. #ifdef BSP_USING_UART4
  518. void UART4_IRQHandler(void) {
  519. rt_interrupt_enter();
  520. usart_isr(&uart_config[UART4_INDEX].serial);
  521. rt_interrupt_leave();
  522. }
  523. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  524. void UART4_RX_DMA_IRQHandler(void)
  525. {
  526. /* enter interrupt */
  527. rt_interrupt_enter();
  528. dma_rx_isr(&uart_config[UART4_INDEX].serial);
  529. /* leave interrupt */
  530. rt_interrupt_leave();
  531. }
  532. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA) */
  533. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  534. void UART4_TX_DMA_IRQHandler(void)
  535. {
  536. /* enter interrupt */
  537. rt_interrupt_enter();
  538. dma_tx_isr(&uart_config[UART4_INDEX].serial);
  539. /* leave interrupt */
  540. rt_interrupt_leave();
  541. }
  542. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART14_TX_USING_DMA) */
  543. #endif
  544. #ifdef BSP_USING_UART5
  545. void UART5_IRQHandler(void) {
  546. rt_interrupt_enter();
  547. usart_isr(&uart_config[UART5_INDEX].serial);
  548. rt_interrupt_leave();
  549. }
  550. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  551. void UART5_RX_DMA_IRQHandler(void)
  552. {
  553. /* enter interrupt */
  554. rt_interrupt_enter();
  555. dma_rx_isr(&uart_config[UART5_INDEX].serial);
  556. /* leave interrupt */
  557. rt_interrupt_leave();
  558. }
  559. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  560. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  561. void UART5_TX_DMA_IRQHandler(void)
  562. {
  563. /* enter interrupt */
  564. rt_interrupt_enter();
  565. dma_tx_isr(&uart_config[UART5_INDEX].serial);
  566. /* leave interrupt */
  567. rt_interrupt_leave();
  568. }
  569. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  570. #endif
  571. #ifdef BSP_USING_UART6
  572. void UART6_IRQHandler(void) {
  573. rt_interrupt_enter();
  574. usart_isr(&uart_config[UART6_INDEX].serial);
  575. rt_interrupt_leave();
  576. }
  577. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  578. void UART6_RX_DMA_IRQHandler(void)
  579. {
  580. /* enter interrupt */
  581. rt_interrupt_enter();
  582. dma_rx_isr(&uart_config[UART6_INDEX].serial);
  583. /* leave interrupt */
  584. rt_interrupt_leave();
  585. }
  586. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  587. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  588. void UART6_TX_DMA_IRQHandler(void)
  589. {
  590. /* enter interrupt */
  591. rt_interrupt_enter();
  592. dma_tx_isr(&uart_config[UART6_INDEX].serial);
  593. /* leave interrupt */
  594. rt_interrupt_leave();
  595. }
  596. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  597. #endif
  598. #ifdef BSP_USING_UART7
  599. void UART7_IRQHandler(void) {
  600. rt_interrupt_enter();
  601. usart_isr(&uart_config[UART7_INDEX].serial);
  602. rt_interrupt_leave();
  603. }
  604. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  605. void UART7_RX_DMA_IRQHandler(void)
  606. {
  607. /* enter interrupt */
  608. rt_interrupt_enter();
  609. dma_rx_isr(&uart_config[UART7_INDEX].serial);
  610. /* leave interrupt */
  611. rt_interrupt_leave();
  612. }
  613. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  614. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  615. void UART7_TX_DMA_IRQHandler(void)
  616. {
  617. /* enter interrupt */
  618. rt_interrupt_enter();
  619. dma_tx_isr(&uart_config[UART7_INDEX].serial);
  620. /* leave interrupt */
  621. rt_interrupt_leave();
  622. }
  623. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  624. #endif
  625. #ifdef BSP_USING_UART8
  626. void UART8_IRQHandler(void) {
  627. rt_interrupt_enter();
  628. usart_isr(&uart_config[UART8_INDEX].serial);
  629. rt_interrupt_leave();
  630. }
  631. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  632. void UART8_RX_DMA_IRQHandler(void)
  633. {
  634. /* enter interrupt */
  635. rt_interrupt_enter();
  636. dma_rx_isr(&uart_config[UART8_INDEX].serial);
  637. /* leave interrupt */
  638. rt_interrupt_leave();
  639. }
  640. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  641. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  642. void UART8_TX_DMA_IRQHandler(void)
  643. {
  644. /* enter interrupt */
  645. rt_interrupt_enter();
  646. dma_tx_isr(&uart_config[UART8_INDEX].serial);
  647. /* leave interrupt */
  648. rt_interrupt_leave();
  649. }
  650. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  651. #endif
  652. #if defined (SOC_SERIES_AT32F421)
  653. void UART1_TX_RX_DMA_IRQHandler(void)
  654. {
  655. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  656. UART1_TX_DMA_IRQHandler();
  657. #endif
  658. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  659. UART1_RX_DMA_IRQHandler();
  660. #endif
  661. }
  662. void UART2_TX_RX_DMA_IRQHandler(void)
  663. {
  664. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  665. UART2_TX_DMA_IRQHandler();
  666. #endif
  667. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  668. UART2_RX_DMA_IRQHandler();
  669. #endif
  670. }
  671. #endif
  672. #if defined (SOC_SERIES_AT32F425)
  673. #if defined(BSP_USING_UART3) || defined(BSP_USING_UART4)
  674. void USART4_3_IRQHandler(void)
  675. {
  676. #if defined(BSP_USING_UART3)
  677. UART3_IRQHandler();
  678. #endif
  679. #if defined(BSP_USING_UART4)
  680. UART4_IRQHandler();
  681. #endif
  682. }
  683. #endif
  684. void UART1_TX_RX_DMA_IRQHandler(void)
  685. {
  686. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  687. UART1_TX_DMA_IRQHandler();
  688. #endif
  689. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  690. UART1_RX_DMA_IRQHandler();
  691. #endif
  692. }
  693. void UART3_2_TX_RX_DMA_IRQHandler(void)
  694. {
  695. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  696. UART2_TX_DMA_IRQHandler();
  697. #endif
  698. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  699. UART2_RX_DMA_IRQHandler();
  700. #endif
  701. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  702. UART3_TX_DMA_IRQHandler();
  703. #endif
  704. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  705. UART3_RX_DMA_IRQHandler();
  706. #endif
  707. }
  708. #endif
  709. #if defined (RT_SERIAL_USING_DMA)
  710. static void _dma_base_channel_check(struct at32_uart *instance)
  711. {
  712. dma_channel_type *rx_channel = instance->dma_rx->dma_channel;
  713. dma_channel_type *tx_channel = instance->dma_tx->dma_channel;
  714. instance->dma_rx->dma_done = RT_TRUE;
  715. instance->dma_rx->dma_x = (dma_type *)((rt_uint32_t)rx_channel & ~0xFF);
  716. instance->dma_rx->channel_index = ((((rt_uint32_t)rx_channel & 0xFF) - 8) / 0x14) + 1;
  717. instance->dma_tx->dma_done = RT_TRUE;
  718. instance->dma_tx->dma_x = (dma_type *)((rt_uint32_t)tx_channel & ~0xFF);
  719. instance->dma_tx->channel_index = ((((rt_uint32_t)tx_channel & 0xFF) - 8) / 0x14) + 1;
  720. }
  721. #endif
  722. static void at32_uart_get_dma_config(void)
  723. {
  724. #ifdef BSP_USING_UART1
  725. uart_config[UART1_INDEX].uart_dma_flag = 0;
  726. #ifdef BSP_UART1_RX_USING_DMA
  727. uart_config[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  728. static struct dma_config uart1_dma_rx = UART1_RX_DMA_CONFIG;
  729. uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
  730. #endif
  731. #ifdef BSP_UART1_TX_USING_DMA
  732. uart_config[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  733. static struct dma_config uart1_dma_tx = UART1_TX_DMA_CONFIG;
  734. uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx;
  735. #endif
  736. #endif
  737. #ifdef BSP_USING_UART2
  738. uart_config[UART2_INDEX].uart_dma_flag = 0;
  739. #ifdef BSP_UART2_RX_USING_DMA
  740. uart_config[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  741. static struct dma_config uart2_dma_rx = UART2_RX_DMA_CONFIG;
  742. uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
  743. #endif
  744. #ifdef BSP_UART2_TX_USING_DMA
  745. uart_config[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  746. static struct dma_config uart2_dma_tx = UART2_TX_DMA_CONFIG;
  747. uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx;
  748. #endif
  749. #endif
  750. #ifdef BSP_USING_UART3
  751. uart_config[UART3_INDEX].uart_dma_flag = 0;
  752. #ifdef BSP_UART3_RX_USING_DMA
  753. uart_config[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  754. static struct dma_config uart3_dma_rx = UART3_RX_DMA_CONFIG;
  755. uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
  756. #endif
  757. #ifdef BSP_UART3_TX_USING_DMA
  758. uart_config[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  759. static struct dma_config uart3_dma_tx = UART3_TX_DMA_CONFIG;
  760. uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx;
  761. #endif
  762. #endif
  763. #ifdef BSP_USING_UART4
  764. uart_config[UART4_INDEX].uart_dma_flag = 0;
  765. #ifdef BSP_UART4_RX_USING_DMA
  766. uart_config[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  767. static struct dma_config uart4_dma_rx = UART4_RX_DMA_CONFIG;
  768. uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
  769. #endif
  770. #ifdef BSP_UART4_TX_USING_DMA
  771. uart_config[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  772. static struct dma_config uart4_dma_tx = UART4_TX_DMA_CONFIG;
  773. uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
  774. #endif
  775. #endif
  776. #ifdef BSP_USING_UART5
  777. uart_config[UART5_INDEX].uart_dma_flag = 0;
  778. #ifdef BSP_UART5_RX_USING_DMA
  779. uart_config[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  780. static struct dma_config uart5_dma_rx = UART5_RX_DMA_CONFIG;
  781. uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
  782. #endif
  783. #ifdef BSP_UART5_TX_USING_DMA
  784. uart_config[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  785. static struct dma_config uart5_dma_tx = UART5_TX_DMA_CONFIG;
  786. uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx;
  787. #endif
  788. #endif
  789. #ifdef BSP_USING_UART6
  790. uart_config[UART6_INDEX].uart_dma_flag = 0;
  791. #ifdef BSP_UART6_RX_USING_DMA
  792. uart_config[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  793. static struct dma_config uart6_dma_rx = UART6_RX_DMA_CONFIG;
  794. uart_config[UART6_INDEX].dma_rx = &uart6_dma_rx;
  795. #endif
  796. #ifdef BSP_UART6_TX_USING_DMA
  797. uart_config[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  798. static struct dma_config uart6_dma_tx = UART6_TX_DMA_CONFIG;
  799. uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx;
  800. #endif
  801. #endif
  802. #ifdef BSP_USING_UART7
  803. uart_config[UART7_INDEX].uart_dma_flag = 0;
  804. #ifdef BSP_UART7_RX_USING_DMA
  805. uart_config[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  806. static struct dma_config uart7_dma_rx = UART7_RX_DMA_CONFIG;
  807. uart_config[UART7_INDEX].dma_rx = &uart7_dma_rx;
  808. #endif
  809. #ifdef BSP_UART7_TX_USING_DMA
  810. uart_config[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  811. static struct dma_config uart7_dma_tx = UART7_TX_DMA_CONFIG;
  812. uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
  813. #endif
  814. #endif
  815. #ifdef BSP_USING_UART8
  816. uart_config[UART8_INDEX].uart_dma_flag = 0;
  817. #ifdef BSP_UART8_RX_USING_DMA
  818. uart_config[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  819. static struct dma_config uart8_dma_rx = UART8_RX_DMA_CONFIG;
  820. uart_config[UART8_INDEX].dma_rx = &uart8_dma_rx;
  821. #endif
  822. #ifdef BSP_UART8_TX_USING_DMA
  823. uart_config[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  824. static struct dma_config uart8_dma_tx = UART8_TX_DMA_CONFIG;
  825. uart_config[UART8_INDEX].dma_tx = &uart8_dma_tx;
  826. #endif
  827. #endif
  828. }
  829. int rt_hw_usart_init(void) {
  830. rt_size_t obj_num;
  831. int index;
  832. obj_num = sizeof(uart_config) / sizeof(struct at32_uart);
  833. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  834. rt_err_t result = 0;
  835. at32_uart_get_dma_config();
  836. for (index = 0; index < obj_num; index++) {
  837. uart_config[index].serial.ops = &at32_uart_ops;
  838. uart_config[index].serial.config = config;
  839. #if defined (RT_SERIAL_USING_DMA)
  840. /* search dma base and channel index */
  841. _dma_base_channel_check(&uart_config[index]);
  842. #endif
  843. /* register uart device */
  844. result = rt_hw_serial_register(&uart_config[index].serial,
  845. uart_config[index].name,
  846. RT_DEVICE_FLAG_RDWR |
  847. RT_DEVICE_FLAG_INT_RX |
  848. uart_config[index].uart_dma_flag ,
  849. &uart_config[index]);
  850. RT_ASSERT(result == RT_EOK);
  851. }
  852. return result;
  853. }
  854. #endif /* BSP_USING_SERIAL */