drv_spi.c 11 KB

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  1. /*
  2. * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Licensed under the Apache License, Version 2.0 (the License); you may
  7. * not use this file except in compliance with the License.
  8. * You may obtain a copy of the License at
  9. *
  10. * www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing, software
  13. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  14. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15. * See the License for the specific language governing permissions and
  16. * limitations under the License.
  17. *
  18. * Change Logs:
  19. * Date Author Notes
  20. * 2019-11-01 wangyq update libraries
  21. * 2020-01-14 wangyq the first version
  22. * 2021-04-20 liuhy the second version
  23. */
  24. #include <rtthread.h>
  25. #include <rtdevice.h>
  26. #include <string.h>
  27. #include <rthw.h>
  28. #include "board.h"
  29. #include "drv_spi.h"
  30. #ifdef RT_USING_SPI
  31. #define SPITIMEOUT 0xFFFF
  32. rt_err_t spi_configure(struct rt_spi_device *device,
  33. struct rt_spi_configuration *cfg)
  34. {
  35. spi_handle_t *hspi;
  36. hspi = (spi_handle_t *)device->bus->parent.user_data;
  37. hspi->init.ss_en = DISABLE;
  38. hspi->init.crc_calc = DISABLE;
  39. hspi->init.frame = SPI_FRAME_MOTOROLA;
  40. /* config spi mode */
  41. if (cfg->mode & RT_SPI_SLAVE)
  42. {
  43. hspi->init.mode = SPI_MODE_SLAVER;
  44. }
  45. else
  46. {
  47. hspi->init.mode = SPI_MODE_MASTER;
  48. }
  49. if (cfg->mode & RT_SPI_3WIRE)
  50. {
  51. hspi->init.dir = SPI_DIRECTION_1LINE;
  52. }
  53. else
  54. {
  55. hspi->init.dir = SPI_DIRECTION_2LINES;
  56. }
  57. if (cfg->data_width == 8)
  58. {
  59. hspi->init.data_size = SPI_DATA_SIZE_8;
  60. }
  61. else if (cfg->data_width == 16)
  62. {
  63. hspi->init.data_size = SPI_DATA_SIZE_16;
  64. }
  65. if (cfg->mode & RT_SPI_CPHA)
  66. {
  67. hspi->init.phase = SPI_CPHA_SECOND;
  68. }
  69. else
  70. {
  71. hspi->init.phase = SPI_CPHA_FIRST;
  72. }
  73. if (cfg->mode & RT_SPI_MSB)
  74. {
  75. hspi->init.first_bit = SPI_FIRSTBIT_MSB;
  76. }
  77. else
  78. {
  79. hspi->init.first_bit = SPI_FIRSTBIT_LSB;
  80. }
  81. if (cfg->mode & RT_SPI_CPOL)
  82. {
  83. hspi->init.polarity = SPI_CPOL_HIGH;
  84. }
  85. else
  86. {
  87. hspi->init.polarity = SPI_CPOL_LOW;
  88. }
  89. if (cfg->mode & RT_SPI_NO_CS)
  90. {
  91. hspi->init.ss_en = DISABLE;
  92. }
  93. else
  94. {
  95. hspi->init.ss_en = ENABLE;
  96. }
  97. /* config spi clock */
  98. if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
  99. {
  100. /* pclk1 max speed 48MHz, spi master max speed 10MHz */
  101. if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
  102. {
  103. hspi->init.baud = SPI_BAUD_2;
  104. }
  105. else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
  106. {
  107. hspi->init.baud = SPI_BAUD_4;
  108. }
  109. else
  110. {
  111. hspi->init.baud = SPI_BAUD_8;
  112. }
  113. }
  114. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
  115. {
  116. /* pclk1 max speed 48MHz, spi master max speed 10MHz */
  117. if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
  118. {
  119. hspi->init.baud = SPI_BAUD_4;
  120. }
  121. else
  122. {
  123. hspi->init.baud = SPI_BAUD_8;
  124. }
  125. }
  126. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
  127. {
  128. hspi->init.baud = SPI_BAUD_8;
  129. }
  130. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
  131. {
  132. hspi->init.baud = SPI_BAUD_16;
  133. }
  134. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
  135. {
  136. hspi->init.baud = SPI_BAUD_32;
  137. }
  138. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
  139. {
  140. hspi->init.baud = SPI_BAUD_64;
  141. }
  142. else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
  143. {
  144. hspi->init.baud = SPI_BAUD_128;
  145. }
  146. else
  147. {
  148. hspi->init.baud = SPI_BAUD_256;
  149. }
  150. ald_spi_init(hspi);
  151. return RT_EOK;
  152. }
  153. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  154. {
  155. rt_err_t res;
  156. spi_handle_t *hspi;
  157. struct es32f3_hw_spi_cs *cs;
  158. RT_ASSERT(device != RT_NULL);
  159. RT_ASSERT(device->bus != RT_NULL);
  160. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  161. hspi = (spi_handle_t *)device->bus->parent.user_data;
  162. cs = device->parent.user_data;
  163. if (message->cs_take)
  164. {
  165. rt_pin_write(cs->pin, ES_SPI_CS_LEVEL);
  166. }
  167. if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL)
  168. {
  169. /* send & receive */
  170. if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
  171. {
  172. res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
  173. (rt_int32_t)message->length, SPITIMEOUT);
  174. }
  175. else
  176. {
  177. /* only send data */
  178. if (message->recv_buf == RT_NULL)
  179. {
  180. res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
  181. }
  182. /* only receive data */
  183. if (message->send_buf == RT_NULL)
  184. {
  185. res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
  186. }
  187. }
  188. if (message->cs_release)
  189. {
  190. rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL);
  191. }
  192. if (res != RT_EOK)
  193. return -RT_ERROR;
  194. else
  195. return message->length;
  196. }
  197. else
  198. {
  199. if (message->cs_release)
  200. {
  201. rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL);
  202. }
  203. return RT_EOK;
  204. }
  205. }
  206. const struct rt_spi_ops es32f3_spi_ops =
  207. {
  208. spi_configure,
  209. spixfer,
  210. };
  211. rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
  212. {
  213. int result;
  214. /* define spi Instance */
  215. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  216. RT_ASSERT(spi_device != RT_NULL);
  217. struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs));
  218. RT_ASSERT(cs_pin != RT_NULL);
  219. cs_pin->pin = pin;
  220. rt_pin_mode(pin, PIN_MODE_OUTPUT);
  221. rt_pin_write(pin, 1);
  222. result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  223. #ifdef BSP_USING_SPI0
  224. if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0);
  225. #endif
  226. #ifdef BSP_USING_SPI1
  227. if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1);
  228. #endif
  229. #ifdef BSP_USING_SPI2
  230. if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI2_BUS)))SPI_BUS_CONFIG(spi_device->config,2);
  231. #endif
  232. return result;
  233. }
  234. #ifdef BSP_USING_SPI0
  235. static struct rt_spi_bus _spi_bus0;
  236. static spi_handle_t _spi0;
  237. #endif
  238. #ifdef BSP_USING_SPI1
  239. static struct rt_spi_bus _spi_bus1;
  240. static spi_handle_t _spi1;
  241. #endif
  242. #ifdef BSP_USING_SPI2
  243. static struct rt_spi_bus _spi_bus2;
  244. static spi_handle_t _spi2;
  245. #endif
  246. int rt_hw_spi_init(void)
  247. {
  248. int result = RT_EOK;
  249. struct rt_spi_bus *spi_bus;
  250. spi_handle_t *spi;
  251. gpio_init_t gpio_instruct;
  252. gpio_instruct.pupd = GPIO_PUSH_UP_DOWN;
  253. gpio_instruct.odos = GPIO_PUSH_PULL;
  254. gpio_instruct.podrv = GPIO_OUT_DRIVE_6;
  255. gpio_instruct.nodrv = GPIO_OUT_DRIVE_6;
  256. gpio_instruct.type = GPIO_TYPE_TTL;
  257. gpio_instruct.flt = GPIO_FILTER_DISABLE;
  258. #ifdef BSP_USING_SPI0
  259. _spi0.perh = SPI0;
  260. spi_bus = &_spi_bus0;
  261. spi = &_spi0;
  262. /* SPI0 gpio init */
  263. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  264. #if defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN)
  265. gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC;
  266. ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct);
  267. #endif
  268. #if defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN)
  269. gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC;
  270. ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct);
  271. #endif
  272. gpio_instruct.mode = GPIO_MODE_INPUT;
  273. #if defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN)
  274. gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC;
  275. ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct);
  276. #endif
  277. spi_bus->parent.user_data = spi;
  278. result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f3_spi_ops);
  279. if (result != RT_EOK)
  280. {
  281. return result;
  282. }
  283. result = es32f3_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0);
  284. if (result != RT_EOK)
  285. {
  286. return result;
  287. }
  288. #endif
  289. #ifdef BSP_USING_SPI1
  290. _spi1.perh = SPI1;
  291. spi_bus = &_spi_bus1;
  292. spi = &_spi1;
  293. /* SPI1 gpio init */
  294. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  295. #if defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN)
  296. gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC;
  297. ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct);
  298. #endif
  299. #if defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN)
  300. gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC;
  301. ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct);
  302. #endif
  303. gpio_instruct.mode = GPIO_MODE_INPUT;
  304. #if defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN)
  305. gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC;
  306. ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct);
  307. #endif
  308. spi_bus->parent.user_data = spi;
  309. result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f3_spi_ops);
  310. if (result != RT_EOK)
  311. {
  312. return result;
  313. }
  314. result = es32f3_spi_device_attach(ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0);
  315. if (result != RT_EOK)
  316. {
  317. return result;
  318. }
  319. #endif
  320. #ifdef BSP_USING_SPI2
  321. _spi2.perh = SPI2;
  322. spi_bus = &_spi_bus2;
  323. spi = &_spi2;
  324. /* SPI2 gpio init */
  325. gpio_instruct.mode = GPIO_MODE_OUTPUT;
  326. #if defined(ES_SPI2_SCK_GPIO_FUNC)&&defined(ES_SPI2_SCK_GPIO_PORT)&&defined(ES_SPI2_SCK_GPIO_PIN)
  327. gpio_instruct.func = ES_SPI2_SCK_GPIO_FUNC;
  328. ald_gpio_init(ES_SPI2_SCK_GPIO_PORT, ES_SPI2_SCK_GPIO_PIN, &gpio_instruct);
  329. #endif
  330. #if defined(ES_SPI2_MOSI_GPIO_FUNC)&&defined(ES_SPI2_MOSI_GPIO_PORT)&&defined(ES_SPI2_MOSI_GPIO_PIN)
  331. gpio_instruct.func = ES_SPI2_MOSI_GPIO_FUNC;
  332. ald_gpio_init(ES_SPI2_MOSI_GPIO_PORT, ES_SPI2_MOSI_GPIO_PIN, &gpio_instruct);
  333. #endif
  334. gpio_instruct.mode = GPIO_MODE_INPUT;
  335. #if defined(ES_SPI2_MISO_GPIO_FUNC)&&defined(ES_SPI2_MISO_GPIO_PORT)&&defined(ES_SPI2_MISO_GPIO_PIN)
  336. gpio_instruct.func = ES_SPI2_MISO_GPIO_FUNC;
  337. ald_gpio_init(ES_SPI2_MISO_GPIO_PORT, ES_SPI2_MISO_GPIO_PIN, &gpio_instruct);
  338. #endif
  339. spi_bus->parent.user_data = spi;
  340. result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI2_BUS, &es32f3_spi_ops);
  341. if (result != RT_EOK)
  342. {
  343. return result;
  344. }
  345. result = es32f3_spi_device_attach(ES_SPI2_NSS_PIN, ES_DEVICE_NAME_SPI2_BUS, ES_DEVICE_NAME_SPI1_DEV0);
  346. if (result != RT_EOK)
  347. {
  348. return result;
  349. }
  350. #endif
  351. return result;
  352. }
  353. INIT_BOARD_EXPORT(rt_hw_spi_init);
  354. #endif