drv_spi.c 11 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-12-20 BruceOu first implementation
  9. */
  10. #include "drv_spi.h"
  11. #ifdef RT_USING_SPI
  12. #if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4)
  13. #define LOG_TAG "drv.spi"
  14. #include <rtdbg.h>
  15. #ifdef BSP_USING_SPI0
  16. static struct rt_spi_bus spi_bus0;
  17. #endif
  18. #ifdef BSP_USING_SPI1
  19. static struct rt_spi_bus spi_bus1;
  20. #endif
  21. #ifdef BSP_USING_SPI2
  22. static struct rt_spi_bus spi_bus2;
  23. #endif
  24. #ifdef BSP_USING_SPI3
  25. static struct rt_spi_bus spi_bus3;
  26. #endif
  27. #ifdef BSP_USING_SPI4
  28. static struct rt_spi_bus spi_bus4;
  29. #endif
  30. static const struct gd32_spi spi_bus_obj[] = {
  31. #ifdef BSP_USING_SPI0
  32. {
  33. SPI0,
  34. "spi0",
  35. RCU_SPI0,
  36. RCU_GPIOA,
  37. &spi_bus0,
  38. GPIOA,
  39. #if defined SOC_SERIES_GD32F4xx
  40. GPIO_AF_5,
  41. #endif
  42. GPIO_PIN_5,
  43. GPIO_PIN_6,
  44. GPIO_PIN_7,
  45. },
  46. #endif /* BSP_USING_SPI0 */
  47. #ifdef BSP_USING_SPI1
  48. {
  49. SPI1,
  50. "spi1",
  51. RCU_SPI1,
  52. RCU_GPIOB,
  53. &spi_bus1,
  54. GPIOB,
  55. #if defined SOC_SERIES_GD32F4xx
  56. GPIO_AF_5,
  57. #endif
  58. GPIO_PIN_12,
  59. GPIO_PIN_14,
  60. GPIO_PIN_15,
  61. },
  62. #endif /* BSP_USING_SPI1 */
  63. #ifdef BSP_USING_SPI2
  64. {
  65. SPI2,
  66. "spi2",
  67. RCU_SPI2,
  68. RCU_GPIOB,
  69. &spi_bus2,
  70. GPIOB,
  71. #if defined SOC_SERIES_GD32F4xx
  72. GPIO_AF_6,
  73. #endif
  74. GPIO_PIN_3,
  75. GPIO_PIN_4,
  76. GPIO_PIN_5,
  77. },
  78. #endif /* BSP_USING_SPI2 */
  79. #ifdef BSP_USING_SPI3
  80. {
  81. SPI2,
  82. "spi2",
  83. RCU_SPI3,
  84. RCU_GPIOE,
  85. &spi_bus3,
  86. GPIOB,
  87. #if defined SOC_SERIES_GD32F4xx
  88. GPIO_AF_5,
  89. #endif
  90. GPIO_PIN_2,
  91. GPIO_PIN_5,
  92. GPIO_PIN_6,
  93. },
  94. #endif /* BSP_USING_SPI3 */
  95. #ifdef BSP_USING_SPI4
  96. {
  97. SPI4,
  98. "spi4",
  99. RCU_SPI4,
  100. RCU_GPIOF,
  101. &spi_bus4,
  102. GPIOF,
  103. #if defined SOC_SERIES_GD32F4xx
  104. GPIO_AF_5,
  105. #endif
  106. GPIO_PIN_7,
  107. GPIO_PIN_8,
  108. GPIO_PIN_9,
  109. }
  110. #endif /* BSP_USING_SPI4 */
  111. };
  112. /* private rt-thread spi ops function */
  113. static rt_err_t spi_configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
  114. static rt_uint32_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message);
  115. static struct rt_spi_ops gd32_spi_ops =
  116. {
  117. .configure = spi_configure,
  118. .xfer = spixfer,
  119. };
  120. /**
  121. * @brief SPI Initialization
  122. * @param gd32_spi: SPI BUS
  123. * @retval None
  124. */
  125. static void gd32_spi_init(struct gd32_spi *gd32_spi)
  126. {
  127. /* enable SPI clock */
  128. rcu_periph_clock_enable(gd32_spi->spi_clk);
  129. rcu_periph_clock_enable(gd32_spi->gpio_clk);
  130. #if defined SOC_SERIES_GD32F4xx
  131. /*GPIO pin configuration*/
  132. gpio_af_set(gd32_spi->spi_port, gd32_spi->alt_func_num, gd32_spi->sck_pin | gd32_spi->mosi_pin | gd32_spi->miso_pin);
  133. gpio_mode_set(gd32_spi->spi_port, GPIO_MODE_AF, GPIO_PUPD_NONE, gd32_spi->sck_pin | gd32_spi->mosi_pin | gd32_spi->miso_pin);
  134. gpio_output_options_set(gd32_spi->spi_port, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, gd32_spi->sck_pin | gd32_spi->mosi_pin | gd32_spi->miso_pin);
  135. #else
  136. /* Init SPI SCK MOSI */
  137. gpio_init(gd32_spi->spi_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, gd32_spi->sck_pin | gd32_spi->mosi_pin);
  138. /* Init SPI MISO */
  139. gpio_init(gd32_spi->spi_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, gd32_spi->miso_pin);
  140. #endif
  141. }
  142. static rt_err_t spi_configure(struct rt_spi_device* device,
  143. struct rt_spi_configuration* configuration)
  144. {
  145. struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
  146. struct gd32_spi *spi_device = (struct gd32_spi *)spi_bus->parent.user_data;
  147. spi_parameter_struct spi_init_struct;
  148. uint32_t spi_periph = spi_device->spi_periph;
  149. RT_ASSERT(device != RT_NULL);
  150. RT_ASSERT(configuration != RT_NULL);
  151. //Init SPI
  152. gd32_spi_init(spi_device);
  153. /* data_width */
  154. if(configuration->data_width <= 8)
  155. {
  156. spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
  157. }
  158. else if(configuration->data_width <= 16)
  159. {
  160. spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
  161. }
  162. else
  163. {
  164. return -RT_EIO;
  165. }
  166. /* baudrate */
  167. {
  168. rcu_clock_freq_enum spi_src;
  169. uint32_t spi_apb_clock;
  170. uint32_t max_hz;
  171. max_hz = configuration->max_hz;
  172. LOG_D("sys freq: %d\n", rcu_clock_freq_get(CK_SYS));
  173. LOG_D("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2));
  174. LOG_D("max freq: %d\n", max_hz);
  175. if (spi_periph == SPI1 || spi_periph == SPI2)
  176. {
  177. spi_src = CK_APB1;
  178. }
  179. else
  180. {
  181. spi_src = CK_APB2;
  182. }
  183. spi_apb_clock = rcu_clock_freq_get(spi_src);
  184. if(max_hz >= spi_apb_clock/2)
  185. {
  186. spi_init_struct.prescale = SPI_PSC_2;
  187. }
  188. else if (max_hz >= spi_apb_clock/4)
  189. {
  190. spi_init_struct.prescale = SPI_PSC_4;
  191. }
  192. else if (max_hz >= spi_apb_clock/8)
  193. {
  194. spi_init_struct.prescale = SPI_PSC_8;
  195. }
  196. else if (max_hz >= spi_apb_clock/16)
  197. {
  198. spi_init_struct.prescale = SPI_PSC_16;
  199. }
  200. else if (max_hz >= spi_apb_clock/32)
  201. {
  202. spi_init_struct.prescale = SPI_PSC_32;
  203. }
  204. else if (max_hz >= spi_apb_clock/64)
  205. {
  206. spi_init_struct.prescale = SPI_PSC_64;
  207. }
  208. else if (max_hz >= spi_apb_clock/128)
  209. {
  210. spi_init_struct.prescale = SPI_PSC_128;
  211. }
  212. else
  213. {
  214. /* min prescaler 256 */
  215. spi_init_struct.prescale = SPI_PSC_256;
  216. }
  217. } /* baudrate */
  218. switch(configuration->mode & RT_SPI_MODE_3)
  219. {
  220. case RT_SPI_MODE_0:
  221. spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
  222. break;
  223. case RT_SPI_MODE_1:
  224. spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
  225. break;
  226. case RT_SPI_MODE_2:
  227. spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
  228. break;
  229. case RT_SPI_MODE_3:
  230. spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
  231. break;
  232. }
  233. /* MSB or LSB */
  234. if(configuration->mode & RT_SPI_MSB)
  235. {
  236. spi_init_struct.endian = SPI_ENDIAN_MSB;
  237. }
  238. else
  239. {
  240. spi_init_struct.endian = SPI_ENDIAN_LSB;
  241. }
  242. spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
  243. spi_init_struct.device_mode = SPI_MASTER;
  244. spi_init_struct.nss = SPI_NSS_SOFT;
  245. spi_crc_off(spi_periph);
  246. /* init SPI */
  247. spi_init(spi_periph, &spi_init_struct);
  248. /* Enable SPI_MASTER */
  249. spi_enable(spi_periph);
  250. return RT_EOK;
  251. };
  252. static rt_uint32_t spixfer(struct rt_spi_device* device, struct rt_spi_message* message)
  253. {
  254. struct rt_spi_bus * gd32_spi_bus = (struct rt_spi_bus *)device->bus;
  255. struct gd32_spi *spi_device = (struct gd32_spi *)gd32_spi_bus->parent.user_data;
  256. struct rt_spi_configuration * config = &device->config;
  257. struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
  258. uint32_t spi_periph = spi_device->spi_periph;
  259. RT_ASSERT(device != NULL);
  260. RT_ASSERT(message != NULL);
  261. /* take CS */
  262. if(message->cs_take)
  263. {
  264. gpio_bit_reset(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
  265. LOG_D("spi take cs\n");
  266. }
  267. {
  268. if(config->data_width <= 8)
  269. {
  270. const rt_uint8_t * send_ptr = message->send_buf;
  271. rt_uint8_t * recv_ptr = message->recv_buf;
  272. rt_uint32_t size = message->length;
  273. LOG_D("spi poll transfer start: %d\n", size);
  274. while(size--)
  275. {
  276. rt_uint8_t data = 0xFF;
  277. if(send_ptr != RT_NULL)
  278. {
  279. data = *send_ptr++;
  280. }
  281. // Todo: replace register read/write by gd32f4 lib
  282. //Wait until the transmit buffer is empty
  283. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
  284. // Send the byte
  285. spi_i2s_data_transmit(spi_periph, data);
  286. //Wait until a data is received
  287. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
  288. // Get the received data
  289. data = spi_i2s_data_receive(spi_periph);
  290. if(recv_ptr != RT_NULL)
  291. {
  292. *recv_ptr++ = data;
  293. }
  294. }
  295. LOG_D("spi poll transfer finsh\n");
  296. }
  297. else if(config->data_width <= 16)
  298. {
  299. const rt_uint16_t * send_ptr = message->send_buf;
  300. rt_uint16_t * recv_ptr = message->recv_buf;
  301. rt_uint32_t size = message->length;
  302. while(size--)
  303. {
  304. rt_uint16_t data = 0xFF;
  305. if(send_ptr != RT_NULL)
  306. {
  307. data = *send_ptr++;
  308. }
  309. //Wait until the transmit buffer is empty
  310. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
  311. // Send the byte
  312. spi_i2s_data_transmit(spi_periph, data);
  313. //Wait until a data is received
  314. while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
  315. // Get the received data
  316. data = spi_i2s_data_receive(spi_periph);
  317. if(recv_ptr != RT_NULL)
  318. {
  319. *recv_ptr++ = data;
  320. }
  321. }
  322. }
  323. }
  324. /* release CS */
  325. if(message->cs_release)
  326. {
  327. gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
  328. LOG_D("spi release cs\n");
  329. }
  330. return message->length;
  331. };
  332. /**
  333. * Attach the spi device to SPI bus, this function must be used after initialization.
  334. */
  335. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  336. {
  337. RT_ASSERT(bus_name != RT_NULL);
  338. RT_ASSERT(device_name != RT_NULL);
  339. rt_err_t result;
  340. struct rt_spi_device *spi_device;
  341. /* attach the device to spi bus*/
  342. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  343. RT_ASSERT(spi_device != RT_NULL);
  344. if(cs_pin != PIN_NONE)
  345. {
  346. /* initialize the cs pin && select the slave*/
  347. rt_pin_mode(cs_pin, PIN_MODE_OUTPUT);
  348. rt_pin_write(cs_pin, PIN_HIGH);
  349. }
  350. result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  351. if (result != RT_EOK)
  352. {
  353. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  354. }
  355. RT_ASSERT(result == RT_EOK);
  356. LOG_D("%s attach to %s done", device_name, bus_name);
  357. return result;
  358. }
  359. int rt_hw_spi_init(void)
  360. {
  361. int result = 0;
  362. int i;
  363. for (i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++)
  364. {
  365. spi_bus_obj[i].spi_bus->parent.user_data = (void *)&spi_bus_obj[i];
  366. result = rt_spi_bus_register(spi_bus_obj[i].spi_bus, spi_bus_obj[i].bus_name, &gd32_spi_ops);
  367. RT_ASSERT(result == RT_EOK);
  368. LOG_D("%s bus init done", spi_bus_obj[i].bus_name);
  369. }
  370. return result;
  371. }
  372. INIT_BOARD_EXPORT(rt_hw_spi_init);
  373. #endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4*/
  374. #endif /* RT_USING_SPI */