eth_phy_port.h 2.0 KB

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  1. /*
  2. * Copyright (c) 2021 hpmicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #ifndef ETH_PHY_PORT_H
  8. #define ETH_PHY_PORT_H
  9. #include "hpm_ioc_regs.h"
  10. #include <rtdevice.h>
  11. #ifndef PHY_AUTO_NEGO
  12. #define PHY_AUTO_NEGO (1U)
  13. #endif
  14. #ifndef PHY_MDIO_CSR_CLK_FREQ
  15. #define PHY_MDIO_CSR_CLK_FREQ (200000000U)
  16. #endif
  17. enum phy_link_status
  18. {
  19. PHY_LINK_DOWN = 0U,
  20. PHY_LINK_UP
  21. };
  22. typedef struct {
  23. rt_uint32_t phy_speed;
  24. rt_uint32_t phy_duplex;
  25. } phy_info_t;
  26. typedef struct {
  27. rt_uint32_t phy_link;
  28. rt_phy_t phy;
  29. phy_info_t phy_info;
  30. } phy_device_t;
  31. /** @note PHY: RTL8201 */
  32. #define PHY_NAME ("RTL8201")
  33. #define PHY_ID1 (0x1CU)
  34. /* The PHY basic control register */
  35. #define PHY_BASIC_CONTROL_REG (0x00U)
  36. #define PHY_RESET_MASK (1U << 15)
  37. #define PHY_AUTO_NEGOTIATION_MASK (1U << 12)
  38. /* The PHY basic status register */
  39. #define PHY_BASIC_STATUS_REG (0x01U)
  40. #define PHY_LINKED_STATUS_MASK (1U << 2)
  41. #define PHY_AUTONEGO_COMPLETE_MASK (1U << 5)
  42. /* The PHY ID one register */
  43. #define PHY_ID1_REG (0x02U)
  44. /* The PHY ID two register */
  45. #define PHY_ID2_REG (0x03U)
  46. /* The PHY auto-negotiate advertise register */
  47. #define PHY_AUTONEG_ADVERTISE_REG (0x04U)
  48. /* The PHY status register. */
  49. #define PHY_STATUS_REG (0x00U)
  50. #define PHY_10M_MASK (1 << 13)
  51. #define PHY_100M_MASK (1 << 13)
  52. #define PHY_FULL_DUPLEX_MASK (1 << 8)
  53. #define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_100M_MASK) ? 0: 1
  54. #define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK)
  55. #define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK)
  56. /* PHY0 register list */
  57. #define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\
  58. PHY_BASIC_STATUS_REG,\
  59. PHY_ID1_REG,\
  60. PHY_ID2_REG,\
  61. PHY_AUTONEG_ADVERTISE_REG,\
  62. PHY_STATUS_REG
  63. /* PHY0 register index */
  64. #define PHY_BASIC_STATUS_REG_IDX (1U)
  65. #define PHY_ID1_REG_IDX (2U)
  66. #define PHY_STATUS_REG_IDX (5U)
  67. #endif