hpm_ov7725.h 24 KB

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  1. /*
  2. * Copyright (c) 2021 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #ifndef HPM_OV7725_H
  8. #define HPM_OV7725_H
  9. #include "hpm_common.h"
  10. #include "hpm_camera_config.h"
  11. /**
  12. * @brief OV7725 sensor driver APIs
  13. * @defgroup ov7725_interface sensor driver APIs
  14. * @ingroup component_interfaces
  15. * @{
  16. *
  17. */
  18. /***********************************************************************************************************************
  19. *
  20. * Definitions
  21. *
  22. **********************************************************************************************************************/
  23. /**
  24. * @brief OV7725 definition
  25. */
  26. #define OV7725_ACTIVE_IMAGE_WIDTH (480U)
  27. #define OV7725_ACTIVE_IMAGE_HEIGHT (480U)
  28. #define OV7725_I2C_ADDR (0x21U)
  29. #define OV7725_CHIP_ID_HIGH_BYTE_ADDR (0x0A)
  30. #define OV7725_CHIP_ID_HIGH_BYTE_VALUE (0x77)
  31. #define OV7725_CHIP_ID_LOW_BYTE_ADDR (0x0B)
  32. #define OV7725_CHIP_ID_LOW_BYTE_VALUE (0x21) /* need to check */
  33. #define OV7725_RST_ACTIVE 0
  34. #define OV7725_RST_INACTIVE 1
  35. #define OV7725_PWDN_ACTIVE 1
  36. #define OV7725_PWDN_INACTIVE 0
  37. /**
  38. * @brief OV7725 registers
  39. */
  40. #define GAIN (0x00U) /* AGC – Gain control gain setting */
  41. #define BLUE (0x01U) /* AWB – Blue channel gain setting */
  42. #define RED (0x02U) /* AWB – Red channel gain setting */
  43. #define GREEN (0x03U) /* AWB – Green channel gain setting */
  44. #define BAVG (0x05U) /* U/B Average Level */
  45. #define GAVG (0x06U) /* Y/Gb Average Level */
  46. #define RAVG (0x07U) /* V/R Average Level */
  47. #define AECH (0x08U) /* Exposure Value – AEC MSBs */
  48. #define COM2 (0x09U) /* Common Control 2 */
  49. #define COM2_SOFT_SLEEP (0x10U) /* Soft sleep mode */
  50. #define COM2_OUT_DRIVE_1x (0x00U) /* Output drive capability 1x */
  51. #define COM2_OUT_DRIVE_2x (0x01U) /* Output drive capability 2x */
  52. #define COM2_OUT_DRIVE_3x (0x02U) /* Output drive capability 3x */
  53. #define COM2_OUT_DRIVE_4x (0x03U) /* Output drive capability 4x */
  54. #define PID (0x0AU) /* Product ID Number MSB */
  55. #define VER (0x0BU) /* Product ID Number LSB */
  56. #define COM3 (0x0CU) /* Common Control 3 */
  57. #define COM3_VFLIP (0x80U) /* Vertical flip image ON/OFF selection */
  58. #define COM3_MIRROR (0x40U) /* Horizontal mirror image ON/OFF selection */
  59. #define COM3_SWAP_BR (0x20U) /* Swap B/R output sequence in RGB output mode */
  60. #define COM3_SWAP_YUV (0x10U) /* Swap Y/UV output sequence in YUV output mode */
  61. #define COM3_SWAP_MSB (0x08U) /* Swap output MSB/LSB */
  62. #define COM3_TRI_CLOCK (0x04U) /* Tri-state option for output clock at power-down period */
  63. #define COM3_TRI_DATA (0x02U) /* Tri-state option for output data at power-down period */
  64. #define COM3_COLOR_BAR (0x01U) /* Sensor color bar test pattern output enable */
  65. #define COM4 (0x0DU) /* Common Control 4 */
  66. #define COM4_PLL_BYPASS (0x00U) /* Bypass PLL */
  67. #define COM4_PLL_4x (0x40U) /* PLL frequency 4x */
  68. #define COM4_PLL_6x (0x80U) /* PLL frequency 6x */
  69. #define COM4_PLL_8x (0xc0U) /* PLL frequency 8x */
  70. #define COM4_AEC_FULL (0x00U) /* AEC evaluate full window */
  71. #define COM4_AEC_1_2 (0x10U) /* AEC evaluate 1/2 window */
  72. #define COM4_AEC_1_4 (0x20U) /* AEC evaluate 1/4 window */
  73. #define COM4_AEC_2_3 (0x30U) /* AEC evaluate 2/3 window */
  74. #define COM5 (0x0EU) /* Common Control 5 */
  75. #define COM5_AFR (0x80U) /* Auto frame rate control ON/OFF selection (night mode) */
  76. #define COM5_AFR_SPEED (0x40U) /* Auto frame rate control speed selection */
  77. #define COM5_AFR_0 (0x00U) /* No reduction of frame rate */
  78. #define COM5_AFR_1_2 (0x10U) /* Max reduction to 1/2 frame rate */
  79. #define COM5_AFR_1_4 (0x20U) /* Max reduction to 1/4 frame rate */
  80. #define COM5_AFR_1_8 (0x30U) /* Max reduction to 1/8 frame rate */
  81. #define COM5_AFR_4x (0x04U) /* Add frame when AGC reaches 4x gain */
  82. #define COM5_AFR_8x (0x08U) /* Add frame when AGC reaches 8x gain */
  83. #define COM5_AFR_16x (0x0cU) /* Add frame when AGC reaches 16x gain */
  84. #define COM5_AEC_NO_LIMIT (0x01U) /* No limit to AEC increase step */
  85. #define COM6 (0x0FU) /* Common Control 6 */
  86. #define COM6_AUTO_WINDOW (0x01U) /* Auto window setting ON/OFF selection when format changes */
  87. #define AEC (0x10U) /* AEC[7:0] (see register AECH for AEC[15:8]) */
  88. #define CLKRC (0x11U) /* Internal Clock */
  89. #define COM7 (0x12U) /* Common Control 7 */
  90. #define COM7_RESET (0x80U) /* SCCB Register Reset */
  91. #define COM7_RES_VGA (0x00U) /* Resolution VGA */
  92. #define COM7_RES_QVGA (0x40U) /* Resolution QVGA */
  93. #define COM7_BT656 (0x20U) /* BT.656 protocol ON/OFF */
  94. #define COM7_SENSOR_RAW (0x10U) /* Sensor RAW */
  95. #define COM7_FMT_GBR422 (0x02U) /* RGB output format GBR422 */
  96. #define COM7_FMT_RGB565 (0x06U) /* RGB output format RGB565 */
  97. #define COM7_FMT_RGB555 (0x0AU) /* RGB output format RGB555 */
  98. #define COM7_FMT_RGB444 (0x0EU) /* RGB output format RGB444 */
  99. #define COM7_FMT_YUV (0x00U) /* Output format YUV */
  100. #define COM7_FMT_P_BAYER (0x01U) /* Output format Processed Bayer RAW */
  101. #define COM7_FMT_R_BAYER (0x03U) /* Output format Bayer RAW */
  102. #define COM8 (0x13U) /* Common Control 8 */
  103. #define COM8_FAST_AUTO (0x80U) /* Enable fast AGC/AEC algorithm */
  104. #define COM8_STEP_VSYNC (0x00U) /* AEC - Step size limited to vertical blank */
  105. #define COM8_STEP_UNLIMIT (0x40U) /* AEC - Step size unlimited step size */
  106. #define COM8_BANDF_EN (0x20U) /* Banding filter ON/OFF */
  107. #define COM8_AEC_BANDF (0x10U) /* Enable AEC below banding value */
  108. #define COM8_AEC_FINE_EN (0x08U) /* Fine AEC ON/OFF control */
  109. #define COM8_AGC_EN (0x04U) /* AGC Enable */
  110. #define COM8_AWB_EN (0x02U) /* AWB Enable */
  111. #define COM8_AEC_EN (0x01U) /* AEC Enable */
  112. #define COM9 (0x14U) /* Common Control 9 */
  113. #define COM9_HISTO_AVG (0x80U) /* Histogram or average based AEC/AGC selection */
  114. #define COM9_AGC_GAIN_2x (0x00U) /* Automatic Gain Ceiling 2x */
  115. #define COM9_AGC_GAIN_4x (0x10U) /* Automatic Gain Ceiling 4x */
  116. #define COM9_AGC_GAIN_8x (0x20U) /* Automatic Gain Ceiling 8x */
  117. #define COM9_AGC_GAIN_16x (0x30U) /* Automatic Gain Ceiling 16x */
  118. #define COM9_AGC_GAIN_32x (0x40U) /* Automatic Gain Ceiling 32x */
  119. #define COM9_DROP_VSYNC (0x04U) /* Drop VSYNC output of corrupt frame */
  120. #define COM9_DROP_HREF (0x02U) /* Drop HREF output of corrupt frame */
  121. #define COM10 (0x15U) /* Common Control 10 */
  122. #define COM10_NEGATIVE (0x80U) /* Output negative data */
  123. #define COM10_HSYNC_EN (0x40U) /* HREF changes to HSYNC */
  124. #define COM10_PCLK_FREE (0x00U) /* PCLK output option: free running PCLK */
  125. #define COM10_PCLK_MASK (0x20U) /* PCLK output option: masked during horizontal blank */
  126. #define COM10_PCLK_REV (0x10U) /* PCLK reverse */
  127. #define COM10_HREF_REV (0x08U) /* HREF reverse */
  128. #define COM10_VSYNC_FALLING (0x00U) /* VSYNC changes on falling edge of PCLK */
  129. #define COM10_VSYNC_RISING (0x04U) /* VSYNC changes on rising edge of PCLK */
  130. #define COM10_VSYNC_NEG (0x02U) /* VSYNC negative */
  131. #define COM10_OUT_RANGE_8 (0x01U) /* Output data range: Full range */
  132. #define COM10_OUT_RANGE_10 (0x00U) /* Output data range: Data from [10] to [F0] (8 MSBs) */
  133. #define REG16 (0x16U) /* Register 16 */
  134. #define REG16_BIT_SHIFT (0x80U) /* Bit shift test pattern options */
  135. #define HSTART (0x17U) /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */
  136. #define HSIZE (0x18U) /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */
  137. #define VSTART (0x19U) /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */
  138. #define VSIZE (0x1AU) /* Vertical Sensor Size (1 LSB is at HREF[2]) */
  139. #define PSHFT (0x1BU) /* Data Format - Pixel Delay Select */
  140. #define REG_MIDH (0x1CU) /* Manufacturer ID Byte – High */
  141. #define REG_MIDL (0x1DU) /* Manufacturer ID Byte – Low */
  142. #define LAEC (0x1FU) /* Fine AEC Value - defines exposure value less than one row period */
  143. #define COM11 (0x20U) /* Common Control 11 */
  144. #define COM11_SNGL_FRAME_EN (0x02U) /* Single frame ON/OFF selection */
  145. #define COM11_SNGL_XFR_TRIG (0x01U) /* Single frame transfer trigger */
  146. #define BDBASE (0x22U) /* Banding Filter Minimum AEC Value */
  147. #define DBSTEP (0x23U) /* Banding Filter Maximum Step */
  148. #define AEW (0x24U) /* AGC/AEC - Stable Operating Region (Upper Limit) */
  149. #define AEB (0x25U) /* AGC/AEC - Stable Operating Region (Lower Limit) */
  150. #define VPT (0x26U) /* AGC/AEC Fast Mode Operating Region */
  151. #define REG28 (0x28U) /* Selection on the number of dummy rows, N */
  152. #define HOUTSIZE (0x29U) /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */
  153. #define EXHCH (0x2AU) /* Dummy Pixel Insert MSB */
  154. #define EXHCL (0x2BU) /* Dummy Pixel Insert LSB */
  155. #define VOUTSIZE (0x2CU) /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */
  156. #define ADVFL (0x2DU) /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */
  157. #define ADVFH (0x2EU) /* MSB of Insert Dummy Rows in Vertical Sync */
  158. #define YAVE (0x2FU) /* Y/G Channel Average Value */
  159. #define LUMHTH (0x30U) /* Histogram AEC/AGC Luminance High Level Threshold */
  160. #define LUMLTH (0x31U) /* Histogram AEC/AGC Luminance Low Level Threshold */
  161. #define HREF (0x32U) /* Image Start and Size Control */
  162. #define DM_LNL (0x33U) /* Dummy Row Low 8 Bits */
  163. #define DM_LNH (0x34U) /* Dummy Row High 8 Bits */
  164. #define ADOFF_B (0x35U) /* AD Offset Compensation Value for B Channel */
  165. #define ADOFF_R (0x36U) /* AD Offset Compensation Value for R Channel */
  166. #define ADOFF_GB (0x37U) /* AD Offset Compensation Value for GB Channel */
  167. #define ADOFF_GR (0x38U) /* AD Offset Compensation Value for GR Channel */
  168. #define OFF_B (0x39U) /* AD Offset Compensation Value for B Channel */
  169. #define OFF_R (0x3AU) /* AD Offset Compensation Value for R Channel */
  170. #define OFF_GB (0x3BU) /* AD Offset Compensation Value for GB Channel */
  171. #define OFF_GR (0x3CU) /* AD Offset Compensation Value for GR Channel */
  172. #define COM12 (0x3DU) /* DC offset compensation for analog process */
  173. #define COM13 (0x3EU) /* Common Control 13 */
  174. #define COM13_BLC_EN (0x80U) /* BLC enable */
  175. #define COM13_ADC_EN (0x40U) /* ADC channel BLC ON/OFF control */
  176. #define COM13_ANALOG_BLC (0x20U) /* Analog processing channel BLC ON/OFF control */
  177. #define COM13_ABLC_GAIN_EN (0x04U) /* ABLC gain trigger enable */
  178. #define COM14 (0x3FU) /* Common Control 14 */
  179. #define COM15 (0x40U) /* Common Control 15 */
  180. #define COM16 (0x41U) /* Common Control 16 */
  181. #define TGT_B (0x42U) /* BLC Blue Channel Target Value */
  182. #define TGT_R (0x43U) /* BLC Red Channel Target Value */
  183. #define TGT_GB (0x44U) /* BLC Gb Channel Target Value */
  184. #define TGT_GR (0x45U) /* BLC Gr Channel Target Value */
  185. #define LC_CTR (0x46U) /* Lens Correction Control */
  186. #define LC_CTR_RGB_COMP_1 (0x00U) /* R, G, and B channel compensation coefficient is set by LC_COEF ((0x49U)) */
  187. /* R, G, and B channel compensation coefficient is set by registers LC_COEFB ((0x4BU)), LC_COEF ((0x49U)), and LC_COEFR ((0x4CU)), respectively */
  188. #define LC_CTR_RGB_COMP_3 (0x04U)
  189. #define LC_CTR_EN (0x01U) /* Lens correction enable */
  190. #define LC_XC (0x47U) /* X Coordinate of Lens Correction Center Relative to Array Center */
  191. #define LC_YC (0x48U) /* Y Coordinate of Lens Correction Center Relative to Array Center */
  192. #define LC_COEF (0x49U) /* Lens Correction Coefficient */
  193. #define LC_RADI (0x4AU) /* Lens Correction Radius */
  194. #define LC_COEFB (0x4BU) /* Lens Correction B Channel Compensation Coefficient */
  195. #define LC_COEFR (0x4CU) /* Lens Correction R Channel Compensation Coefficient */
  196. #define FIXGAIN (0x4DU) /* Analog Fix Gain Amplifier */
  197. #define AREF0 (0x4EU) /* Sensor Reference Control */
  198. #define AREF1 (0x4FU) /* Sensor Reference Current Control */
  199. #define AREF2 (0x50U) /* Analog Reference Control */
  200. #define AREF3 (0x51U) /* ADC Reference Control */
  201. #define AREF4 (0x52U) /* ADC Reference Control */
  202. #define AREF5 (0x53U) /* ADC Reference Control */
  203. #define AREF6 (0x54U) /* Analog Reference Control */
  204. #define AREF7 (0x55U) /* Analog Reference Control */
  205. #define UFIX (0x60U) /* U Channel Fixed Value Output */
  206. #define VFIX (0x61U) /* V Channel Fixed Value Output */
  207. #define AWBB_BLK (0x62U) /* AWB Option for Advanced AWB */
  208. #define AWB_CTRL0 (0x63U) /* AWB Control Byte 0 */
  209. #define AWB_CTRL0_GAIN_EN (0x80U) /* AWB gain enable */
  210. #define AWB_CTRL0_CALC_EN (0x40U) /* AWB calculate enable */
  211. #define AWB_CTRL0_WBC_MASK (0x0FU) /* WBC threshold 2 */
  212. #define DSP_CTRL1 (0x64U) /* DSP Control Byte 1 */
  213. #define DSP_CTRL1_FIFO_EN (0x80U) /* FIFO enable/disable selection */
  214. #define DSP_CTRL1_UV_EN (0x40U) /* UV adjust function ON/OFF selection */
  215. #define DSP_CTRL1_SDE_EN (0x20U) /* SDE enable */
  216. #define DSP_CTRL1_MTRX_EN (0x10U) /* Color matrix ON/OFF selection */
  217. #define DSP_CTRL1_INTRP_EN (0x08U) /* Interpolation ON/OFF selection */
  218. #define DSP_CTRL1_GAMMA_EN (0x04U) /* Gamma function ON/OFF selection */
  219. #define DSP_CTRL1_BLACK_EN (0x02U) /* Black defect auto correction ON/OFF */
  220. #define DSP_CTRL1_WHITE_EN (0x01U) /* White defect auto correction ON/OFF */
  221. #define DSP_CTRL2 (0x65U) /* DSP Control Byte 2 */
  222. #define DSP_CTRL2_VDCW_EN (0x08U) /* Vertical DCW enable */
  223. #define DSP_CTRL2_HDCW_EN (0x04U) /* Horizontal DCW enable */
  224. #define DSP_CTRL2_VZOOM_EN (0x02U) /* Vertical zoom out enable */
  225. #define DSP_CTRL2_HZOOM_EN (0x01U) /* Horizontal zoom out enable */
  226. #define DSP_CTRL3 (0x66U) /* DSP Control Byte 3 */
  227. #define DSP_CTRL3_UV_EN (0x80U) /* UV output sequence option */
  228. #define DSP_CTRL3_CBAR_EN (0x20U) /* DSP color bar ON/OFF selection */
  229. #define DSP_CTRL3_FIFO_EN (0x08U) /* FIFO power down ON/OFF selection */
  230. #define DSP_CTRL3_SCAL1_PWDN (0x04U) /* Scaling module power down control 1 */
  231. #define DSP_CTRL3_SCAL2_PWDN (0x02U) /* Scaling module power down control 2 */
  232. #define DSP_CTRL3_INTRP_PWDN (0x01U) /* Interpolation module power down control */
  233. #define DSP_CTRL4 (0x67U) /* DSP Control Byte 4 */
  234. #define DSP_CTRL4_YUV_RGB (0x00U) /* Output selection YUV or RGB */
  235. #define DSP_CTRL4_RAW8 (0x02U) /* Output selection RAW8 */
  236. #define DSP_CTRL4_RAW10 (0x03U) /* Output selection RAW10 */
  237. #define AWB_BIAS (0x68U) /* AWB BLC Level Clip */
  238. #define AWB_CTRL1 (0x69U) /* AWB Control 1 */
  239. #define AWB_CTRL2 (0x6AU) /* AWB Control 2 */
  240. #define AWB_CTRL3 (0x6BU) /* AWB Control 3 */
  241. #define AWB_CTRL3_ADVANCED (0x80U) /* AWB mode select - Advanced AWB */
  242. #define AWB_CTRL3_SIMPLE (0x00U) /* AWB mode select - Simple AWB */
  243. #define AWB_CTRL4 (0x6CU) /* AWB Control 4 */
  244. #define AWB_CTRL5 (0x6DU) /* AWB Control 5 */
  245. #define AWB_CTRL6 (0x6EU) /* AWB Control 6 */
  246. #define AWB_CTRL7 (0x6FU) /* AWB Control 7 */
  247. #define AWB_CTRL8 (0x70U) /* AWB Control 8 */
  248. #define AWB_CTRL9 (0x71U) /* AWB Control 9 */
  249. #define AWB_CTRL10 (0x72U) /* AWB Control 10 */
  250. #define AWB_CTRL11 (0x73U) /* AWB Control 11 */
  251. #define AWB_CTRL12 (0x74U) /* AWB Control 12 */
  252. #define AWB_CTRL13 (0x75U) /* AWB Control 13 */
  253. #define AWB_CTRL14 (0x76U) /* AWB Control 14 */
  254. #define AWB_CTRL15 (0x77U) /* AWB Control 15 */
  255. #define AWB_CTRL16 (0x78U) /* AWB Control 16 */
  256. #define AWB_CTRL17 (0x79U) /* AWB Control 17 */
  257. #define AWB_CTRL18 (0x7AU) /* AWB Control 18 */
  258. #define AWB_CTRL19 (0x7BU) /* AWB Control 19 */
  259. #define AWB_CTRL20 (0x7CU) /* AWB Control 20 */
  260. #define AWB_CTRL21 (0x7DU) /* AWB Control 21 */
  261. #define GAM1 (0x7EU) /* Gamma Curve 1st Segment Input End Point (0x04U) Output Value */
  262. #define GAM2 (0x7FU) /* Gamma Curve 2nd Segment Input End Point (0x08U) Output Value */
  263. #define GAM3 (0x80U) /* Gamma Curve 3rd Segment Input End Point (0x10U) Output Value */
  264. #define GAM4 (0x81U) /* Gamma Curve 4th Segment Input End Point (0x20U) Output Value */
  265. #define GAM5 (0x82U) /* Gamma Curve 5th Segment Input End Point (0x28U) Output Value */
  266. #define GAM6 (0x83U) /* Gamma Curve 6th Segment Input End Point (0x30U) Output Value */
  267. #define GAM7 (0x84U) /* Gamma Curve 7th Segment Input End Point (0x38U) Output Value */
  268. #define GAM8 (0x85U) /* Gamma Curve 8th Segment Input End Point (0x40U) Output Value */
  269. #define GAM9 (0x86U) /* Gamma Curve 9th Segment Input End Point (0x48U) Output Value */
  270. #define GAM10 (0x87U) /* Gamma Curve 10th Segment Input End Point (0x50U) Output Value */
  271. #define GAM11 (0x88U) /* Gamma Curve 11th Segment Input End Point (0x60U) Output Value */
  272. #define GAM12 (0x89U) /* Gamma Curve 12th Segment Input End Point (0x70U) Output Value */
  273. #define GAM13 (0x8AU) /* Gamma Curve 13th Segment Input End Point (0x90U) Output Value */
  274. #define GAM14 (0x8BU) /* Gamma Curve 14th Segment Input End Point (0xB0U) Output Value */
  275. #define GAM15 (0x8CU) /* Gamma Curve 15th Segment Input End Point (0xD0U) Output Value */
  276. #define SLOP (0x8DU) /* Gamma Curve Highest Segment Slope */
  277. #define DNSTH (0x8EU) /* De-noise Threshold */
  278. #define EDGE0 (0x8FU) /* Edge Enhancement Strength Control */
  279. #define EDGE1 (0x90U) /* Edge Enhancement Threshold Control */
  280. #define DNSOFF (0x91U) /* Auto De-noise Threshold Control */
  281. #define EDGE2 (0x92U) /* Edge Enhancement Strength Upper Limit */
  282. #define EDGE3 (0x93U) /* Edge Enhancement Strength Upper Limit */
  283. #define MTX1 (0x94U) /* Matrix Coefficient 1 */
  284. #define MTX2 (0x95U) /* Matrix Coefficient 2 */
  285. #define MTX3 (0x96U) /* Matrix Coefficient 3 */
  286. #define MTX4 (0x97U) /* Matrix Coefficient 4 */
  287. #define MTX5 (0x98U) /* Matrix Coefficient 5 */
  288. #define MTX6 (0x99U) /* Matrix Coefficient 6 */
  289. #define MTX_CTRL (0x9AU) /* Matrix Control */
  290. #define MTX_CTRL_DBL_EN (0x80U) /* Matrix double ON/OFF selection */
  291. #define BRIGHTNESS (0x9BU) /* Brightness Control */
  292. #define CONTRAST (0x9CU) /* Contrast Gain */
  293. #define UVADJ0 (0x9EU) /* Auto UV Adjust Control 0 */
  294. #define UVADJ1 (0x9FU) /* Auto UV Adjust Control 1 */
  295. #define SCAL0 (0xA0U) /* DCW Ratio Control */
  296. #define SCAL1 (0xA1U) /* Horizontal Zoom Out Control */
  297. #define SCAL2 (0xA2U) /* Vertical Zoom Out Control */
  298. #define FIFODLYM (0xA3U) /* FIFO Manual Mode Delay Control */
  299. #define FIFODLYA (0xA4U) /* FIFO Auto Mode Delay Control */
  300. #define SDE (0xA6U) /* Special Digital Effect Control */
  301. #define SDE_NEGATIVE_EN (0x40U) /* Negative image enable */
  302. #define SDE_GRAYSCALE_EN (0x20U) /* Gray scale image enable */
  303. #define SDE_V_FIXED_EN (0x10U) /* V fixed value enable */
  304. #define SDE_U_FIXED_EN (0x08U) /* U fixed value enable */
  305. #define SDE_CONT_BRIGHT_EN (0x04U) /* Contrast/Brightness enable */
  306. #define SDE_SATURATION_EN (0x02U) /* Saturation enable */
  307. #define SDE_HUE_EN (0x01U) /* Hue enable */
  308. #define USAT (0xA7U) /* U Component Saturation Gain */
  309. #define VSAT (0xA8U) /* V Component Saturation Gain */
  310. #define HUECOS (0xA9U) /* Cosine value × (0x80U) */
  311. #define HUESIN (0xAAU) /* Sine value × (0x80U) */
  312. #define SIGN_BIT (0xABU) /* Sign Bit for Hue and Brightness */
  313. #define DSPAUTO (0xACU) /* DSP Auto Function ON/OFF Control */
  314. #define DSPAUTO_AWB_EN (0x80U) /* AWB auto threshold control */
  315. #define DSPAUTO_DENOISE_EN (0x40U) /* De-noise auto threshold control */
  316. #define DSPAUTO_EDGE_EN (0x20U) /* Sharpness (edge enhancement) auto strength control */
  317. #define DSPAUTO_UV_EN (0x10U) /* UV adjust auto slope control */
  318. #define DSPAUTO_SCAL0_EN (0x08U) /* Auto scaling factor control (register SCAL0 ((0xA0U))) */
  319. #define DSPAUTO_SCAL1_EN (0x04U) /* Auto scaling factor control (registers SCAL1 ((0xA1U) and SCAL2 ((0xA2U)))*/
  320. #ifdef __cplusplus
  321. extern "C" {
  322. #endif
  323. /**
  324. * @brief ov7725 initialization routine
  325. * @param [in] context camera_context_t
  326. * @param [in] ov_config camera config structure
  327. */
  328. hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config);
  329. /**
  330. * @brief ov7725 read register
  331. * @param [in] context camera_context_t
  332. * @param [in] reg register address
  333. * @param [in] buf buffer to store read data
  334. * @retval status_success if everything is okay
  335. */
  336. hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf);
  337. /**
  338. * @brief ov7725 write register
  339. * @param [in] context camera_context_t
  340. * @param [in] reg register address
  341. * @param [in] val value to be written
  342. * @retval status_success if everything is okay
  343. */
  344. hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val);
  345. /**
  346. * @brief ov7725 reset
  347. * @param [in] context camera_context_t
  348. */
  349. hpm_stat_t ov7725_software_reset(camera_context_t *context);
  350. /**
  351. * @brief ov7725 check chip id
  352. * @param [in] context camera_context_t
  353. */
  354. hpm_stat_t ov7725_check_chip_id(camera_context_t *context);
  355. /**
  356. * @brief ov7725 load set of register-value pairs
  357. *
  358. * @param [in] context camera_context_t
  359. * @param [in] reg_values register-value pair in 2-d array form, ex. reg_values[][2] = {{COM3, 0x1}};
  360. * @parma [in] count register-value pair count in 2-d array
  361. * @retval status_success if everything is okay
  362. */
  363. hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count);
  364. /**
  365. * @brief ov7725 power up
  366. *
  367. * @param [in] context camera_context_t
  368. */
  369. void ov7725_power_up(camera_context_t *context);
  370. #ifdef __cplusplus
  371. }
  372. #endif
  373. /**
  374. * @}
  375. *
  376. */
  377. #endif /* HPM_OV7725_H */