hpm_gptmr_drv.h 12 KB

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  1. /*
  2. * Copyright (c) 2021 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #ifndef HPM_GPTMR_DRV_H
  8. #define HPM_GPTMR_DRV_H
  9. #include "hpm_common.h"
  10. #include "hpm_gptmr_regs.h"
  11. /**
  12. * @brief GPTMR driver APIs
  13. * @defgroup gptmr_interface GPTMR driver APIs
  14. * @ingroup io_interfaces
  15. * @{
  16. */
  17. /**
  18. * @brief GPTMR channel IRQ mask
  19. */
  20. #define GPTMR_CH_CMP_IRQ_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp))
  21. #define GPTMR_CH_CAP_IRQ_MASK(ch) (1 << (ch * 4 + 1))
  22. #define GPTMR_CH_RLD_IRQ_MASK(ch) (1 << (ch * 4))
  23. /**
  24. * @brief GPTMR channel status
  25. */
  26. #define GPTMR_CH_CMP_STAT_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp))
  27. #define GPTMR_CH_CAP_STAT_MASK(ch) (1 << (ch * 4 + 1))
  28. #define GPTMR_CH_RLD_STAT_MASK(ch) (1 << (ch * 4))
  29. /**
  30. * @brief GPTMR channel swsynct mask
  31. */
  32. #define GPTMR_CH_GCR_SWSYNCT_MASK(ch) (1 << ch)
  33. /**
  34. * @brief GPTMR one channel support output comparator count
  35. */
  36. #define GPTMR_CH_CMP_COUNT (2U)
  37. /**
  38. * @brief GPTMR synci valid edge
  39. */
  40. typedef enum gptmr_synci_edge {
  41. gptmr_synci_edge_none = 0,
  42. gptmr_synci_edge_falling = GPTMR_CHANNEL_CR_SYNCIFEN_MASK,
  43. gptmr_synci_edge_rising = GPTMR_CHANNEL_CR_SYNCIREN_MASK,
  44. gptmr_synci_edge_both = gptmr_synci_edge_falling | gptmr_synci_edge_rising,
  45. } gptmr_synci_edge_t;
  46. /**
  47. * @brief GPTMR work mode
  48. */
  49. typedef enum gptmr_work_mode {
  50. gptmr_work_mode_no_capture = 0,
  51. gptmr_work_mode_capture_at_rising_edge = 1,
  52. gptmr_work_mode_capture_at_falling_edge = 2,
  53. gptmr_work_mode_capture_at_both_edge = 3,
  54. gptmr_work_mode_measure_width = 4,
  55. } gptmr_work_mode_t;
  56. /**
  57. * @brief GPTMR DMA request event
  58. */
  59. typedef enum gptmr_dma_request_event {
  60. gptmr_dma_request_on_cmp0 = 0,
  61. gptmr_dma_request_on_cmp1 = 1,
  62. gptmr_dma_request_on_input_signal_toggle = 2,
  63. gptmr_dma_request_on_reload = 3,
  64. gptmr_dma_request_disabled = 0xFF,
  65. } gptmr_dma_request_event_t;
  66. /**
  67. * @brief GPTMR counter type
  68. */
  69. typedef enum gptmr_counter_type {
  70. gptmr_counter_type_rising_edge,
  71. gptmr_counter_type_falling_edge,
  72. gptmr_counter_type_measured_period,
  73. gptmr_counter_type_measured_duty_cycle,
  74. gptmr_counter_type_normal,
  75. } gptmr_counter_type_t;
  76. /**
  77. * @brief GPTMR channel config
  78. */
  79. typedef struct gptmr_channel_config {
  80. gptmr_work_mode_t mode;
  81. gptmr_dma_request_event_t dma_request_event;
  82. gptmr_synci_edge_t synci_edge;
  83. uint32_t cmp[GPTMR_CH_CMP_COUNT];
  84. uint32_t reload;
  85. bool cmp_initial_polarity_high;
  86. bool enable_cmp_output;
  87. bool enable_sync_follow_previous_channel;
  88. bool enable_software_sync;
  89. bool debug_mode;
  90. } gptmr_channel_config_t;
  91. #ifdef __cplusplus
  92. extern "C" {
  93. #endif
  94. /**
  95. * @brief gptmr channel enable
  96. *
  97. * @param [in] ptr GPTMR base address
  98. * @param [in] ch_index channel index
  99. * @param [in] enable
  100. * @arg true: enable
  101. * @arg false: disable
  102. */
  103. static inline void gptmr_channel_enable(GPTMR_Type *ptr, uint8_t ch_index, bool enable)
  104. {
  105. ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR
  106. & ~(GPTMR_CHANNEL_CR_CNTRST_MASK | GPTMR_CHANNEL_CR_CMPEN_MASK))
  107. | GPTMR_CHANNEL_CR_CMPEN_SET(enable);
  108. }
  109. /**
  110. * @brief gptmr channel reset counter
  111. *
  112. * @param [in] ptr GPTMR base address
  113. * @param [in] ch_index channel index
  114. */
  115. static inline void gptmr_channel_reset_count(GPTMR_Type *ptr, uint8_t ch_index)
  116. {
  117. ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTRST_MASK;
  118. ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CNTRST_MASK;
  119. }
  120. /**
  121. * @brief gptmr channel update counter
  122. *
  123. * @param [in] ptr GPTMR base address
  124. * @param [in] ch_index channel index
  125. * @param [in] value updated vaue
  126. */
  127. static inline void gptmr_channel_update_count(GPTMR_Type *ptr,
  128. uint8_t ch_index,
  129. uint32_t value)
  130. {
  131. if (value > 0) {
  132. value--;
  133. }
  134. ptr->CHANNEL[ch_index].CNTUPTVAL = GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(value);
  135. ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK;
  136. }
  137. /**
  138. * @brief gptmr channel slect synci valid edge
  139. *
  140. * @param [in] ptr GPTMR base address
  141. * @param [in] ch_index channel index
  142. * @param [in] edge gptmr_synci_edge_t
  143. */
  144. static inline void gptmr_channel_select_synci_valid_edge(GPTMR_Type *ptr,
  145. uint8_t ch_index,
  146. gptmr_synci_edge_t edge)
  147. {
  148. ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR
  149. & ~(GPTMR_CHANNEL_CR_SYNCIFEN_MASK
  150. | GPTMR_CHANNEL_CR_SYNCIREN_MASK)) | edge;
  151. }
  152. /**
  153. * @brief gptmr channel enable dma request
  154. *
  155. * @param [in] ptr GPTMR base address
  156. * @param [in] ch_index channel index
  157. * @param [in] enable
  158. * @arg true: enable
  159. * @arg false: disable
  160. */
  161. static inline void gptmr_channel_enable_dma_request(GPTMR_Type *ptr,
  162. uint8_t ch_index,
  163. bool enable)
  164. {
  165. ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR
  166. & ~(GPTMR_CHANNEL_CR_DMAEN_MASK)) | GPTMR_CHANNEL_CR_DMAEN_SET(enable);
  167. }
  168. /**
  169. * @brief gptmr channel get counter value
  170. *
  171. * @param [in] ptr GPTMR base address
  172. * @param [in] ch_index channel index
  173. * @param [in] capture gptmr_counter_type_t
  174. */
  175. static inline uint32_t gptmr_channel_get_counter(GPTMR_Type *ptr,
  176. uint8_t ch_index,
  177. gptmr_counter_type_t capture)
  178. {
  179. uint32_t value;
  180. switch (capture) {
  181. case gptmr_counter_type_rising_edge:
  182. value = (ptr->CHANNEL[ch_index].CAPPOS & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT;
  183. break;
  184. case gptmr_counter_type_falling_edge:
  185. value = (ptr->CHANNEL[ch_index].CAPNEG & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT;
  186. break;
  187. case gptmr_counter_type_measured_period:
  188. value = (ptr->CHANNEL[ch_index].CAPPRD & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT;
  189. break;
  190. case gptmr_counter_type_measured_duty_cycle:
  191. value = (ptr->CHANNEL[ch_index].CAPDTY & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT;
  192. break;
  193. default:
  194. value = (ptr->CHANNEL[ch_index].CNT & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT;
  195. break;
  196. }
  197. return value;
  198. }
  199. /**
  200. * @brief gptmr trigger channel software sync
  201. *
  202. * @param [in] ptr GPTMR base address
  203. * @param [in] ch_index_mask channel index mask
  204. */
  205. static inline void gptmr_trigger_channel_software_sync(GPTMR_Type *ptr, uint32_t ch_index_mask)
  206. {
  207. ptr->GCR = ch_index_mask;
  208. }
  209. /**
  210. * @brief gptmr enable irq
  211. *
  212. * @param [in] ptr GPTMR base address
  213. * @param [in] irq_mask irq mask
  214. */
  215. static inline void gptmr_enable_irq(GPTMR_Type *ptr, uint32_t irq_mask)
  216. {
  217. ptr->IRQEN |= irq_mask;
  218. }
  219. /**
  220. * @brief gptmr disable irq
  221. *
  222. * @param [in] ptr GPTMR base address
  223. * @param [in] irq_mask irq mask
  224. */
  225. static inline void gptmr_disable_irq(GPTMR_Type *ptr, uint32_t irq_mask)
  226. {
  227. ptr->IRQEN &= ~irq_mask;
  228. }
  229. /**
  230. * @brief gptmr check status
  231. *
  232. * @param [in] ptr GPTMR base address
  233. * @param [in] mask channel flag mask
  234. */
  235. static inline bool gptmr_check_status(GPTMR_Type *ptr, uint32_t mask)
  236. {
  237. return (ptr->SR & mask) == mask;
  238. }
  239. /**
  240. * @brief gptmr clear status
  241. *
  242. * @param [in] ptr GPTMR base address
  243. * @param [in] mask channel flag mask
  244. */
  245. static inline void gptmr_clear_status(GPTMR_Type *ptr, uint32_t mask)
  246. {
  247. ptr->SR |= mask;
  248. }
  249. /**
  250. * @brief gptmr get status
  251. *
  252. * @param [in] ptr GPTMR base address
  253. * @retval SR register value
  254. */
  255. static inline uint32_t gptmr_get_status(GPTMR_Type *ptr)
  256. {
  257. return ptr->SR;
  258. }
  259. /**
  260. * @brief gptmr channel start counter
  261. *
  262. * @param [in] ptr GPTMR base address
  263. * @param [in] ch_index channel index
  264. */
  265. static inline void gptmr_start_counter(GPTMR_Type *ptr, uint8_t ch_index)
  266. {
  267. ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CEN_MASK;
  268. }
  269. /**
  270. * @brief gptmr channel stop counter
  271. *
  272. * @param [in] ptr GPTMR base address
  273. * @param [in] ch_index channel index
  274. */
  275. static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index)
  276. {
  277. ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK;
  278. }
  279. /**
  280. * @brief gptmr channel enable compare output
  281. *
  282. * @param [in] ptr GPTMR base address
  283. * @param [in] ch_index channel index
  284. */
  285. static inline void gptmr_enable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index)
  286. {
  287. ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CMPEN_MASK;
  288. }
  289. /**
  290. * @brief gptmr channel disable compare output
  291. *
  292. * @param [in] ptr GPTMR base address
  293. * @param [in] ch_index channel index
  294. */
  295. static inline void gptmr_disable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index)
  296. {
  297. ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CMPEN_MASK;
  298. }
  299. /**
  300. * @brief gptmr channel set capmode
  301. *
  302. * @param [in] ptr GPTMR base address
  303. * @param [in] ch_index channel index
  304. */
  305. static inline void gptmr_channel_set_capmode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_work_mode_t mode)
  306. {
  307. ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CAPMODE_MASK) | GPTMR_CHANNEL_CR_CAPMODE_SET(mode);
  308. }
  309. /**
  310. * @brief gptmr channel get capmode
  311. *
  312. * @param [in] ptr GPTMR base address
  313. * @param [in] ch_index channel index
  314. * @retval gptmr_work_mode_t enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge
  315. */
  316. static inline gptmr_work_mode_t gptmr_channel_get_capmode(GPTMR_Type *ptr, uint8_t ch_index)
  317. {
  318. return GPTMR_CHANNEL_CR_CAPMODE_GET(ptr->CHANNEL[ch_index].CR);
  319. }
  320. /**
  321. * @brief gptmr channel update comparator
  322. *
  323. * @param [in] ptr GPTMR base address
  324. * @param [in] ch_index channel index
  325. * @param [in] cmp_index comparator index
  326. * @param [in] cmp comparator value
  327. */
  328. static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t cmp_index, uint32_t cmp)
  329. {
  330. if (cmp > 0) {
  331. cmp--;
  332. }
  333. ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CHANNEL_CMP_CMP_SET(cmp);
  334. }
  335. /**
  336. * @brief gptmr channel get reload
  337. *
  338. * @param [in] ptr GPTMR base address
  339. * @param [in] ch_index channel index
  340. * @retval RLD register value
  341. */
  342. static inline uint32_t gptmr_channel_get_reload(GPTMR_Type *ptr, uint8_t ch_index)
  343. {
  344. return ptr->CHANNEL[ch_index].RLD;
  345. }
  346. /**
  347. * @brief gptmr channel update reload
  348. *
  349. * @param [in] ptr GPTMR base address
  350. * @param [in] ch_index channel index
  351. * @param [in] reload reload value
  352. */
  353. static inline void gptmr_channel_config_update_reload(GPTMR_Type *ptr, uint8_t ch_index, uint32_t reload)
  354. {
  355. if (reload > 0) {
  356. reload--;
  357. }
  358. ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload);
  359. }
  360. /**
  361. * @brief gptmr channel get dma request event
  362. *
  363. * @param [in] ptr GPTMR base address
  364. * @param [in] ch_index channel index
  365. * @retval gptmr_dma_request_event_t gptmr_dma_request_on_cmp0 or gptmr_dma_request_on_reload
  366. */
  367. static inline gptmr_dma_request_event_t gptmr_channel_get_dma_request_event(GPTMR_Type *ptr, uint8_t ch_index)
  368. {
  369. return GPTMR_CHANNEL_CR_DMASEL_GET(ptr->CHANNEL[ch_index].CR);
  370. }
  371. /**
  372. * @brief gptmr channel config
  373. *
  374. * @param [in] ptr GPTMR base address
  375. * @param [in] ch_index channel index
  376. * @param [in] config gptmr_channel_config_t
  377. * @param [in] enable
  378. * @arg true: enable
  379. * @arg false: disable
  380. *
  381. * @retval hpm_stat_t status_invalid_argument or status_success
  382. */
  383. hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr,
  384. uint8_t ch_index,
  385. gptmr_channel_config_t *config,
  386. bool enable);
  387. /**
  388. * @brief gptmr channel get default config
  389. *
  390. * @param [in] ptr GPTMR base address
  391. * @param [out] config gptmr_channel_config_t
  392. */
  393. void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config);
  394. /**
  395. * @}
  396. */
  397. #ifdef __cplusplus
  398. }
  399. #endif
  400. #endif /* HPM_GPTMR_DRV_H */