hpm_sysctl_regs.h 52 KB

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  1. /*
  2. * Copyright (c) 2021-2023 HPMicro
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. *
  6. */
  7. #ifndef HPM_SYSCTL_H
  8. #define HPM_SYSCTL_H
  9. typedef struct {
  10. __RW uint32_t RESOURCE[350]; /* 0x0 - 0x574: Resource control register for cpu0 */
  11. __R uint8_t RESERVED0[648]; /* 0x578 - 0x7FF: Reserved */
  12. struct {
  13. __RW uint32_t VALUE; /* 0x800: Goup setting */
  14. __RW uint32_t SET; /* 0x804: Goup setting */
  15. __RW uint32_t CLEAR; /* 0x808: Goup setting */
  16. __RW uint32_t TOGGLE; /* 0x80C: Goup setting */
  17. } GROUP0[3];
  18. __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */
  19. struct {
  20. __RW uint32_t VALUE; /* 0x840: Goup setting */
  21. __RW uint32_t SET; /* 0x844: Goup setting */
  22. __RW uint32_t CLEAR; /* 0x848: Goup setting */
  23. __RW uint32_t TOGGLE; /* 0x84C: Goup setting */
  24. } GROUP1[3];
  25. __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */
  26. struct {
  27. __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
  28. __RW uint32_t SET; /* 0x904: Affiliate of Group */
  29. __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
  30. __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
  31. } AFFILIATE[2];
  32. struct {
  33. __RW uint32_t VALUE; /* 0x920: Retention Contol */
  34. __RW uint32_t SET; /* 0x924: Retention Contol */
  35. __RW uint32_t CLEAR; /* 0x928: Retention Contol */
  36. __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */
  37. } RETENTION[2];
  38. __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */
  39. struct {
  40. __RW uint32_t STATUS; /* 0x1000: Power Setting */
  41. __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
  42. __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
  43. __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
  44. } POWER[4];
  45. __R uint8_t RESERVED4[960]; /* 0x1040 - 0x13FF: Reserved */
  46. struct {
  47. __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
  48. __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
  49. __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
  50. __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
  51. } RESET[5];
  52. __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */
  53. __RW uint32_t CLOCK[67]; /* 0x1800 - 0x1908: Clock setting */
  54. __R uint8_t RESERVED6[756]; /* 0x190C - 0x1BFF: Reserved */
  55. __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */
  56. __RW uint32_t I2SCLK[4]; /* 0x1C10 - 0x1C1C: Clock setting */
  57. __R uint8_t RESERVED7[992]; /* 0x1C20 - 0x1FFF: Reserved */
  58. __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
  59. __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */
  60. struct {
  61. __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
  62. __R uint32_t CURRENT; /* 0x2404: Clock measure result */
  63. __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
  64. __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
  65. __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
  66. } MONITOR[4];
  67. __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */
  68. struct {
  69. __RW uint32_t LP; /* 0x2800: */
  70. __RW uint32_t LOCK; /* 0x2804: */
  71. __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: */
  72. __R uint32_t WAKEUP_STATUS[8]; /* 0x2840 - 0x285C: */
  73. __R uint8_t RESERVED0[32]; /* 0x2860 - 0x287F: Reserved */
  74. __RW uint32_t WAKEUP_ENABLE[8]; /* 0x2880 - 0x289C: */
  75. __R uint8_t RESERVED1[864]; /* 0x28A0 - 0x2BFF: Reserved */
  76. } CPU[2];
  77. } SYSCTL_Type;
  78. /* Bitfield definition for register array: RESOURCE */
  79. /*
  80. * GLB_BUSY (RO)
  81. *
  82. * global busy
  83. * 0: no changes pending to any nodes
  84. * 1: any of nodes is changing status
  85. */
  86. #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
  87. #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
  88. #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
  89. /*
  90. * LOC_BUSY (RO)
  91. *
  92. * local busy
  93. * 0: no change is pending for current node
  94. * 1: current node is changing status
  95. */
  96. #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
  97. #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
  98. #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
  99. /*
  100. * MODE (RW)
  101. *
  102. * resource work mode
  103. * 0:auto turn on and off as system required(recommended)
  104. * 1:always on
  105. * 2:always off
  106. * 3:reserved
  107. */
  108. #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
  109. #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
  110. #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
  111. #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
  112. /* Bitfield definition for register of struct array GROUP0: VALUE */
  113. /*
  114. * LINK (RW)
  115. *
  116. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  117. * 0: peripheral is not needed
  118. * 1: periphera is needed
  119. */
  120. #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
  121. #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
  122. #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
  123. #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
  124. /* Bitfield definition for register of struct array GROUP0: SET */
  125. /*
  126. * LINK (RW)
  127. *
  128. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  129. * 0: peripheral is not needed
  130. * 1: periphera is needed
  131. */
  132. #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
  133. #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
  134. #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
  135. #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
  136. /* Bitfield definition for register of struct array GROUP0: CLEAR */
  137. /*
  138. * LINK (RW)
  139. *
  140. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  141. * 0: peripheral is not needed
  142. * 1: periphera is needed
  143. */
  144. #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
  145. #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
  146. #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
  147. #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
  148. /* Bitfield definition for register of struct array GROUP0: TOGGLE */
  149. /*
  150. * LINK (RW)
  151. *
  152. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  153. * 0: peripheral is not needed
  154. * 1: periphera is needed
  155. */
  156. #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
  157. #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
  158. #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
  159. #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
  160. /* Bitfield definition for register of struct array GROUP1: VALUE */
  161. /*
  162. * LINK (RW)
  163. *
  164. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  165. * 0: peripheral is not needed
  166. * 1: periphera is needed
  167. */
  168. #define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL)
  169. #define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U)
  170. #define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK)
  171. #define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT)
  172. /* Bitfield definition for register of struct array GROUP1: SET */
  173. /*
  174. * LINK (RW)
  175. *
  176. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  177. * 0: peripheral is not needed
  178. * 1: periphera is needed
  179. */
  180. #define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL)
  181. #define SYSCTL_GROUP1_SET_LINK_SHIFT (0U)
  182. #define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK)
  183. #define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT)
  184. /* Bitfield definition for register of struct array GROUP1: CLEAR */
  185. /*
  186. * LINK (RW)
  187. *
  188. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  189. * 0: peripheral is not needed
  190. * 1: periphera is needed
  191. */
  192. #define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL)
  193. #define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U)
  194. #define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK)
  195. #define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT)
  196. /* Bitfield definition for register of struct array GROUP1: TOGGLE */
  197. /*
  198. * LINK (RW)
  199. *
  200. * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral
  201. * 0: peripheral is not needed
  202. * 1: periphera is needed
  203. */
  204. #define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
  205. #define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U)
  206. #define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK)
  207. #define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT)
  208. /* Bitfield definition for register of struct array AFFILIATE: VALUE */
  209. /*
  210. * LINK (RW)
  211. *
  212. * Affiliate groups of cpu0
  213. * bit0: cpu0 depends on logic node0
  214. * bit1: cpu0 depends on logic node1
  215. * bit2: cpu0 depends on logic node2
  216. * bit3: cpu0 depends on logic node3
  217. */
  218. #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
  219. #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
  220. #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
  221. #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
  222. /* Bitfield definition for register of struct array AFFILIATE: SET */
  223. /*
  224. * LINK (RW)
  225. *
  226. * Affiliate groups of cpu0
  227. * bit0: cpu0 depends on logic node0
  228. * bit1: cpu0 depends on logic node1
  229. * bit2: cpu0 depends on logic node2
  230. * bit3: cpu0 depends on logic node3
  231. */
  232. #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
  233. #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
  234. #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
  235. #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
  236. /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
  237. /*
  238. * LINK (RW)
  239. *
  240. * Affiliate groups of cpu0
  241. * bit0: cpu0 depends on logic node0
  242. * bit1: cpu0 depends on logic node1
  243. * bit2: cpu0 depends on logic node2
  244. * bit3: cpu0 depends on logic node3
  245. */
  246. #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
  247. #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
  248. #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
  249. #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
  250. /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
  251. /*
  252. * LINK (RW)
  253. *
  254. * Affiliate groups of cpu0
  255. * bit0: cpu0 depends on logic node0
  256. * bit1: cpu0 depends on logic node1
  257. * bit2: cpu0 depends on logic node2
  258. * bit3: cpu0 depends on logic node3
  259. */
  260. #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
  261. #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
  262. #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
  263. #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
  264. /* Bitfield definition for register of struct array RETENTION: VALUE */
  265. /*
  266. * LINK (RW)
  267. *
  268. * retention setting while system sleep, each bit represents a resource
  269. * bit0: soc_pow
  270. * bit1: soc_rst
  271. * bit2: cpu0_pow
  272. * bit3: cpu0_rst
  273. * bit4: cpu1_pow
  274. * bit5: cpu1_rst
  275. * bit6: con_pow
  276. * bit7: con_rst
  277. * bit8: vis_pow
  278. * bit9: vis_rst
  279. * bit10: xtal
  280. * bit11: pll0
  281. * bit12: pll1
  282. * bit13: pll2
  283. * bit14: pll3
  284. * bit15: pll4
  285. */
  286. #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFFFUL)
  287. #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
  288. #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
  289. #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
  290. /* Bitfield definition for register of struct array RETENTION: SET */
  291. /*
  292. * LINK (RW)
  293. *
  294. * retention setting while system sleep
  295. */
  296. #define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFFFUL)
  297. #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
  298. #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
  299. #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
  300. /* Bitfield definition for register of struct array RETENTION: CLEAR */
  301. /*
  302. * LINK (RW)
  303. *
  304. * retention setting while system sleep
  305. */
  306. #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFFFUL)
  307. #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
  308. #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
  309. #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
  310. /* Bitfield definition for register of struct array RETENTION: TOGGLE */
  311. /*
  312. * LINK (RW)
  313. *
  314. * retention setting while system sleep
  315. */
  316. #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFFFUL)
  317. #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
  318. #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
  319. #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
  320. /* Bitfield definition for register of struct array POWER: STATUS */
  321. /*
  322. * FLAG (RW)
  323. *
  324. * flag represents power cycle happened from last clear of this bit
  325. * 0: power domain did not edurance power cycle since last clear of this bit
  326. * 1: power domain enduranced power cycle since last clear of this bit
  327. */
  328. #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
  329. #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
  330. #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
  331. #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
  332. /*
  333. * FLAG_WAKE (RW)
  334. *
  335. * flag represents wakeup power cycle happened from last clear of this bit
  336. * 0: power domain did not edurance wakeup power cycle since last clear of this bit
  337. * 1: power domain enduranced wakeup power cycle since last clear of this bit
  338. */
  339. #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
  340. #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
  341. #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
  342. #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
  343. /*
  344. * LF_DISABLE (RO)
  345. *
  346. * low fanout power switch disable
  347. * 0: low fanout power switches are turned on
  348. * 1: low fanout power switches are truned off
  349. */
  350. #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
  351. #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
  352. #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
  353. /*
  354. * LF_ACK (RO)
  355. *
  356. * low fanout power switch feedback
  357. * 0: low fanout power switches are turned on
  358. * 1: low fanout power switches are truned off
  359. */
  360. #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
  361. #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
  362. #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
  363. /* Bitfield definition for register of struct array POWER: LF_WAIT */
  364. /*
  365. * WAIT (RW)
  366. *
  367. * wait time for low fan out power switch turn on, default value is 255
  368. * 0: 0 clock cycle
  369. * 1: 1 clock cycles
  370. * . . .
  371. * clock cycles count on 24MHz
  372. */
  373. #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
  374. #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
  375. #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
  376. #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
  377. /* Bitfield definition for register of struct array POWER: OFF_WAIT */
  378. /*
  379. * WAIT (RW)
  380. *
  381. * wait time for power switch turn off, default value is 15
  382. * 0: 0 clock cycle
  383. * 1: 1 clock cycles
  384. * . . .
  385. * clock cycles count on 24MHz
  386. */
  387. #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
  388. #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
  389. #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
  390. #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
  391. /* Bitfield definition for register of struct array RESET: CONTROL */
  392. /*
  393. * FLAG (RW)
  394. *
  395. * flag represents reset happened from last clear of this bit
  396. * 0: domain did not edurance reset cycle since last clear of this bit
  397. * 1: domain enduranced reset cycle since last clear of this bit
  398. */
  399. #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
  400. #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
  401. #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
  402. #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
  403. /*
  404. * FLAG_WAKE (RW)
  405. *
  406. * flag represents wakeup reset happened from last clear of this bit
  407. * 0: domain did not edurance wakeup reset cycle since last clear of this bit
  408. * 1: domain enduranced wakeup reset cycle since last clear of this bit
  409. */
  410. #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
  411. #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
  412. #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
  413. #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
  414. /*
  415. * HOLD (RW)
  416. *
  417. * perform reset and hold in reset, until ths bit cleared by software
  418. * 0: reset is released for function
  419. * 1: reset is assert and hold
  420. */
  421. #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
  422. #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
  423. #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
  424. #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
  425. /*
  426. * RESET (RW)
  427. *
  428. * perform reset and release imediately
  429. * 0: reset is released
  430. * 1 reset is asserted and will release automaticly
  431. */
  432. #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
  433. #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
  434. #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
  435. #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
  436. /* Bitfield definition for register of struct array RESET: CONFIG */
  437. /*
  438. * PRE_WAIT (RW)
  439. *
  440. * wait cycle numbers before assert reset
  441. * 0: wait 0 cycle
  442. * 1: wait 1 cycles
  443. * . . .
  444. * Note, clock cycle is base on 24M
  445. */
  446. #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
  447. #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
  448. #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
  449. #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
  450. /*
  451. * RSTCLK_NUM (RW)
  452. *
  453. * reset clock number(must be even number)
  454. * 0: 0 cycle
  455. * 1: 0 cycles
  456. * 2: 2 cycles
  457. * 3: 2 cycles
  458. * . . .
  459. * Note, clock cycle is base on 24M
  460. */
  461. #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
  462. #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
  463. #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
  464. #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
  465. /*
  466. * POST_WAIT (RW)
  467. *
  468. * time guard band for reset release
  469. * 0: wait 0 cycle
  470. * 1: wait 1 cycles
  471. * . . .
  472. * Note, clock cycle is base on 24M
  473. */
  474. #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
  475. #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
  476. #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
  477. #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
  478. /* Bitfield definition for register of struct array RESET: COUNTER */
  479. /*
  480. * COUNTER (RW)
  481. *
  482. * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
  483. * 0: wait 0 cycle
  484. * 1: wait 1 cycles
  485. * . . .
  486. * Note, clock cycle is base on 24M
  487. */
  488. #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
  489. #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
  490. #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
  491. #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
  492. /* Bitfield definition for register array: CLOCK */
  493. /*
  494. * GLB_BUSY (RO)
  495. *
  496. * global busy
  497. * 0: no changes pending to any clock
  498. * 1: any of nodes is changing status
  499. */
  500. #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
  501. #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
  502. #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
  503. /*
  504. * LOC_BUSY (RO)
  505. *
  506. * local busy
  507. * 0: a change is pending for current node
  508. * 1: current node is changing status
  509. */
  510. #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
  511. #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
  512. #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
  513. /*
  514. * MUX (RW)
  515. *
  516. * clock source selection
  517. * 0:osc0_clk0
  518. * 1:pll0_clk0
  519. * 2:pll1_clk0
  520. * 3:pll1_clk1
  521. * 4:pll2_clk0
  522. * 5:pll2_clk1
  523. * 6:pll3_clk0
  524. * 7:pll4_clk0
  525. */
  526. #define SYSCTL_CLOCK_MUX_MASK (0xF00U)
  527. #define SYSCTL_CLOCK_MUX_SHIFT (8U)
  528. #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
  529. #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
  530. /*
  531. * DIV (RW)
  532. *
  533. * clock divider
  534. * 0: divider by1
  535. * 1: divider by 2
  536. * 2 divider by 3
  537. * . . .
  538. * 255: divider by 256
  539. */
  540. #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
  541. #define SYSCTL_CLOCK_DIV_SHIFT (0U)
  542. #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
  543. #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
  544. /* Bitfield definition for register array: ADCCLK */
  545. /*
  546. * GLB_BUSY (RO)
  547. *
  548. * global busy
  549. * 0: no changes pending to any clock
  550. * 1: any of nodes is changing status
  551. */
  552. #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
  553. #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
  554. #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
  555. /*
  556. * LOC_BUSY (RO)
  557. *
  558. * local busy
  559. * 0: a change is pending for current node
  560. * 1: current node is changing status
  561. */
  562. #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
  563. #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
  564. #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
  565. /*
  566. * MUX (RW)
  567. *
  568. * clock source selection
  569. * 0: ahb clock
  570. * 1: adc clock 0
  571. * 2: adc clock 1
  572. * 3: adc clock 2
  573. */
  574. #define SYSCTL_ADCCLK_MUX_MASK (0x700U)
  575. #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
  576. #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
  577. #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
  578. /* Bitfield definition for register array: I2SCLK */
  579. /*
  580. * GLB_BUSY (RO)
  581. *
  582. * global busy
  583. * 0: no changes pending to any clock
  584. * 1: any of nodes is changing status
  585. */
  586. #define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL)
  587. #define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U)
  588. #define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT)
  589. /*
  590. * LOC_BUSY (RO)
  591. *
  592. * local busy
  593. * 0: a change is pending for current node
  594. * 1: current node is changing status
  595. */
  596. #define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL)
  597. #define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U)
  598. #define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT)
  599. /*
  600. * MUX (RW)
  601. *
  602. * clock source selection
  603. * 0: ahb clock
  604. * 1: i2s clock 0
  605. * 2: i2s clock 1
  606. * 3: i2s clock 2
  607. */
  608. #define SYSCTL_I2SCLK_MUX_MASK (0x700U)
  609. #define SYSCTL_I2SCLK_MUX_SHIFT (8U)
  610. #define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK)
  611. #define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT)
  612. /* Bitfield definition for register: GLOBAL00 */
  613. /*
  614. * PRESET (RW)
  615. *
  616. * global clock override request
  617. * bit0: override to preset0
  618. * bit1: override to preset1
  619. * bit2: override to preset2
  620. * bit3: override to preset3
  621. */
  622. #define SYSCTL_GLOBAL00_PRESET_MASK (0xFU)
  623. #define SYSCTL_GLOBAL00_PRESET_SHIFT (0U)
  624. #define SYSCTL_GLOBAL00_PRESET_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_PRESET_SHIFT) & SYSCTL_GLOBAL00_PRESET_MASK)
  625. #define SYSCTL_GLOBAL00_PRESET_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_PRESET_MASK) >> SYSCTL_GLOBAL00_PRESET_SHIFT)
  626. /* Bitfield definition for register of struct array MONITOR: CONTROL */
  627. /*
  628. * VALID (RW)
  629. *
  630. * result is ready for read
  631. * 0: not ready
  632. * 1: result is ready
  633. */
  634. #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
  635. #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
  636. #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
  637. #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
  638. /*
  639. * DIV_BUSY (RO)
  640. *
  641. * divider is applying new setting
  642. */
  643. #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
  644. #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
  645. #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
  646. /*
  647. * OUTEN (RW)
  648. *
  649. * enable clock output
  650. */
  651. #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
  652. #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
  653. #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
  654. #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
  655. /*
  656. * DIV (RW)
  657. *
  658. * output divider
  659. */
  660. #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
  661. #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
  662. #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
  663. #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
  664. /*
  665. * HIGH (RW)
  666. *
  667. * clock frequency higher than upper limit
  668. */
  669. #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
  670. #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
  671. #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
  672. #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
  673. /*
  674. * LOW (RW)
  675. *
  676. * clock frequency lower than lower limit
  677. */
  678. #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
  679. #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
  680. #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
  681. #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
  682. /*
  683. * START (RW)
  684. *
  685. * start measurement
  686. */
  687. #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
  688. #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
  689. #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
  690. #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
  691. /*
  692. * MODE (RW)
  693. *
  694. * work mode,
  695. * 0: register value will be compared to measurement
  696. * 1: upper and lower value will be recordered in register
  697. */
  698. #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
  699. #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
  700. #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
  701. #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
  702. /*
  703. * ACCURACY (RW)
  704. *
  705. * measurement accuracy,
  706. * 0: resolution is 1kHz
  707. * 1: resolution is 1Hz
  708. */
  709. #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
  710. #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
  711. #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
  712. #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
  713. /*
  714. * REFERENCE (RW)
  715. *
  716. * refrence clock selection,
  717. * 0: 32k
  718. * 1: 24M
  719. */
  720. #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
  721. #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
  722. #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
  723. #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
  724. /*
  725. * SELECTION (RW)
  726. *
  727. * clock measurement selection
  728. */
  729. #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
  730. #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
  731. #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
  732. #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
  733. /* Bitfield definition for register of struct array MONITOR: CURRENT */
  734. /*
  735. * FREQUENCY (RO)
  736. *
  737. * self updating measure result
  738. */
  739. #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
  740. #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
  741. #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
  742. /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
  743. /*
  744. * FREQUENCY (RW)
  745. *
  746. * lower frequency
  747. */
  748. #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
  749. #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
  750. #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
  751. #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
  752. /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
  753. /*
  754. * FREQUENCY (RW)
  755. *
  756. * upper frequency
  757. */
  758. #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
  759. #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
  760. #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
  761. #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
  762. /* Bitfield definition for register of struct array CPU: LP */
  763. /*
  764. * WAKE_CNT (RW)
  765. *
  766. * CPU0 wake up counter, counter saturated at 255, write 0x00 to clear
  767. */
  768. #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
  769. #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
  770. #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
  771. #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
  772. /*
  773. * HALT (RW)
  774. *
  775. * halt request for CPU0,
  776. * 0: CPU0 will start to execute after reset or receive wakeup request
  777. * 1: CPU0 will not start after reset, or wakeup after WFI
  778. */
  779. #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
  780. #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
  781. #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
  782. #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
  783. /*
  784. * WAKE (RO)
  785. *
  786. * CPU0 is waking up
  787. * 0: CPU0 wake up not asserted
  788. * 1: CPU0 wake up asserted
  789. */
  790. #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
  791. #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
  792. #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
  793. /*
  794. * EXEC (RO)
  795. *
  796. * CPU0 is executing
  797. * 0: CPU0 is not executing
  798. * 1: CPU0 is executing
  799. */
  800. #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
  801. #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
  802. #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
  803. /*
  804. * WAKE_FLAG (RW)
  805. *
  806. * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
  807. * 0: CPU0 wakeup not happened
  808. * 1: CPU0 wakeup happened
  809. */
  810. #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
  811. #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
  812. #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
  813. #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
  814. /*
  815. * SLEEP_FLAG (RW)
  816. *
  817. * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
  818. * 0: CPU0 sleep not happened
  819. * 1: CPU0 sleep happened
  820. */
  821. #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
  822. #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
  823. #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
  824. #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
  825. /*
  826. * RESET_FLAG (RW)
  827. *
  828. * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
  829. * 0: CPU0 sleep not happened
  830. * 1: CPU0 sleep happened
  831. */
  832. #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
  833. #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
  834. #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
  835. #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
  836. /*
  837. * MODE (RW)
  838. *
  839. * Low power mode, system behavior after WFI
  840. * 00: CPU clock stop after WFI
  841. * 01: System enter low power mode after WFI
  842. * 10: Keep running after WFI
  843. * 11: reserved
  844. */
  845. #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
  846. #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
  847. #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
  848. #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
  849. /* Bitfield definition for register of struct array CPU: LOCK */
  850. /*
  851. * GPR (RW)
  852. *
  853. * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
  854. */
  855. #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
  856. #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
  857. #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
  858. #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
  859. /*
  860. * LOCK (RW)
  861. *
  862. * Lock bit for CPU_LOCK
  863. */
  864. #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
  865. #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
  866. #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
  867. #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
  868. /* Bitfield definition for register of struct array CPU: GPR0 */
  869. /*
  870. * GPR (RW)
  871. *
  872. * register for software to handle resume, can save resume address or status
  873. */
  874. #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
  875. #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
  876. #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
  877. #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
  878. /* Bitfield definition for register of struct array CPU: STATUS0 */
  879. /*
  880. * STATUS (RO)
  881. *
  882. * IRQ values
  883. */
  884. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
  885. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
  886. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
  887. /* Bitfield definition for register of struct array CPU: ENABLE0 */
  888. /*
  889. * ENABLE (RW)
  890. *
  891. * IRQ wakeup enable
  892. */
  893. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
  894. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
  895. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
  896. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
  897. /* RESOURCE register group index macro definition */
  898. #define SYSCTL_RESOURCE_CPU0_CORE (0UL)
  899. #define SYSCTL_RESOURCE_CPU0_SUBSYS (1UL)
  900. #define SYSCTL_RESOURCE_CPU1_CORE (8UL)
  901. #define SYSCTL_RESOURCE_CPX1_SUBSYS (9UL)
  902. #define SYSCTL_RESOURCE_POW_CON (21UL)
  903. #define SYSCTL_RESOURCE_POW_VIS (22UL)
  904. #define SYSCTL_RESOURCE_POW_CPU0 (23UL)
  905. #define SYSCTL_RESOURCE_POW_CPU1 (24UL)
  906. #define SYSCTL_RESOURCE_RST_SOC (25UL)
  907. #define SYSCTL_RESOURCE_RST_CON (26UL)
  908. #define SYSCTL_RESOURCE_RST_VIS (27UL)
  909. #define SYSCTL_RESOURCE_RST_CPU0 (28UL)
  910. #define SYSCTL_RESOURCE_RST_CPU1 (29UL)
  911. #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
  912. #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
  913. #define SYSCTL_RESOURCE_CLK_SRC_PLL0CLK0 (34UL)
  914. #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL)
  915. #define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK0 (36UL)
  916. #define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK1 (37UL)
  917. #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL)
  918. #define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK0 (39UL)
  919. #define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK1 (40UL)
  920. #define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL)
  921. #define SYSCTL_RESOURCE_CLK_SRC_PLL3CLK0 (42UL)
  922. #define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL)
  923. #define SYSCTL_RESOURCE_CLK_SRC_PLL4CLK0 (44UL)
  924. #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
  925. #define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65UL)
  926. #define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL)
  927. #define SYSCTL_RESOURCE_CLK_TOP_MCHTMR1 (67UL)
  928. #define SYSCTL_RESOURCE_CLK_TOP_AXI (68UL)
  929. #define SYSCTL_RESOURCE_CLK_TOP_CONN (69UL)
  930. #define SYSCTL_RESOURCE_CLK_TOP_VIS (70UL)
  931. #define SYSCTL_RESOURCE_CLK_TOP_AHB (71UL)
  932. #define SYSCTL_RESOURCE_CLK_TOP_FEMC (72UL)
  933. #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (73UL)
  934. #define SYSCTL_RESOURCE_CLK_TOP_XPI1 (74UL)
  935. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR0 (75UL)
  936. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR1 (76UL)
  937. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR2 (77UL)
  938. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR3 (78UL)
  939. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR4 (79UL)
  940. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR5 (80UL)
  941. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR6 (81UL)
  942. #define SYSCTL_RESOURCE_CLK_TOP_GPTMR7 (82UL)
  943. #define SYSCTL_RESOURCE_CLK_TOP_UART0 (83UL)
  944. #define SYSCTL_RESOURCE_CLK_TOP_UART1 (84UL)
  945. #define SYSCTL_RESOURCE_CLK_TOP_UART2 (85UL)
  946. #define SYSCTL_RESOURCE_CLK_TOP_UART3 (86UL)
  947. #define SYSCTL_RESOURCE_CLK_TOP_UART4 (87UL)
  948. #define SYSCTL_RESOURCE_CLK_TOP_UART5 (88UL)
  949. #define SYSCTL_RESOURCE_CLK_TOP_UART6 (89UL)
  950. #define SYSCTL_RESOURCE_CLK_TOP_UART7 (90UL)
  951. #define SYSCTL_RESOURCE_CLK_TOP_UART8 (91UL)
  952. #define SYSCTL_RESOURCE_CLK_TOP_UART9 (92UL)
  953. #define SYSCTL_RESOURCE_CLK_TOP_UART10 (93UL)
  954. #define SYSCTL_RESOURCE_CLK_TOP_UART11 (94UL)
  955. #define SYSCTL_RESOURCE_CLK_TOP_UART12 (95UL)
  956. #define SYSCTL_RESOURCE_CLK_TOP_UART13 (96UL)
  957. #define SYSCTL_RESOURCE_CLK_TOP_UART14 (97UL)
  958. #define SYSCTL_RESOURCE_CLK_TOP_UART15 (98UL)
  959. #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (99UL)
  960. #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (100UL)
  961. #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (101UL)
  962. #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (102UL)
  963. #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (103UL)
  964. #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (104UL)
  965. #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (105UL)
  966. #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (106UL)
  967. #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (107UL)
  968. #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (108UL)
  969. #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (109UL)
  970. #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (110UL)
  971. #define SYSCTL_RESOURCE_CLK_TOP_PTPC (111UL)
  972. #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (112UL)
  973. #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (113UL)
  974. #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (114UL)
  975. #define SYSCTL_RESOURCE_CLK_TOP_AUD0 (115UL)
  976. #define SYSCTL_RESOURCE_CLK_TOP_AUD1 (116UL)
  977. #define SYSCTL_RESOURCE_CLK_TOP_AUD2 (117UL)
  978. #define SYSCTL_RESOURCE_CLK_TOP_LCDC (118UL)
  979. #define SYSCTL_RESOURCE_CLK_TOP_CAM0 (119UL)
  980. #define SYSCTL_RESOURCE_CLK_TOP_CAM1 (120UL)
  981. #define SYSCTL_RESOURCE_CLK_TOP_ENET0 (121UL)
  982. #define SYSCTL_RESOURCE_CLK_TOP_ENET1 (122UL)
  983. #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (123UL)
  984. #define SYSCTL_RESOURCE_CLK_TOP_PTP1 (124UL)
  985. #define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL)
  986. #define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL)
  987. #define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (127UL)
  988. #define SYSCTL_RESOURCE_CLK_TOP_NTMR1 (128UL)
  989. #define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (129UL)
  990. #define SYSCTL_RESOURCE_CLK_TOP_SDXC1 (130UL)
  991. #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (192UL)
  992. #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (193UL)
  993. #define SYSCTL_RESOURCE_CLK_TOP_ADC2 (194UL)
  994. #define SYSCTL_RESOURCE_CLK_TOP_ADC3 (195UL)
  995. #define SYSCTL_RESOURCE_CLK_TOP_I2S0 (196UL)
  996. #define SYSCTL_RESOURCE_CLK_TOP_I2S1 (197UL)
  997. #define SYSCTL_RESOURCE_CLK_TOP_I2S2 (198UL)
  998. #define SYSCTL_RESOURCE_CLK_TOP_I2S3 (199UL)
  999. #define SYSCTL_RESOURCE_AHBAPB_BUS (256UL)
  1000. #define SYSCTL_RESOURCE_AXI_BUS (257UL)
  1001. #define SYSCTL_RESOURCE_CONN_BUS (258UL)
  1002. #define SYSCTL_RESOURCE_VIS_BUS (259UL)
  1003. #define SYSCTL_RESOURCE_FEMC (260UL)
  1004. #define SYSCTL_RESOURCE_ROM (261UL)
  1005. #define SYSCTL_RESOURCE_LMM0 (262UL)
  1006. #define SYSCTL_RESOURCE_LMM1 (263UL)
  1007. #define SYSCTL_RESOURCE_MCHTMR0 (264UL)
  1008. #define SYSCTL_RESOURCE_MCHTMR1 (265UL)
  1009. #define SYSCTL_RESOURCE_AXI_SRAM0 (266UL)
  1010. #define SYSCTL_RESOURCE_AXI_SRAM1 (267UL)
  1011. #define SYSCTL_RESOURCE_XPI0 (268UL)
  1012. #define SYSCTL_RESOURCE_XPI1 (269UL)
  1013. #define SYSCTL_RESOURCE_SDP (270UL)
  1014. #define SYSCTL_RESOURCE_RNG (271UL)
  1015. #define SYSCTL_RESOURCE_KEYM (272UL)
  1016. #define SYSCTL_RESOURCE_HDMA (273UL)
  1017. #define SYSCTL_RESOURCE_XDMA (274UL)
  1018. #define SYSCTL_RESOURCE_GPIO (275UL)
  1019. #define SYSCTL_RESOURCE_MBX0 (276UL)
  1020. #define SYSCTL_RESOURCE_MBX1 (277UL)
  1021. #define SYSCTL_RESOURCE_WDG0 (278UL)
  1022. #define SYSCTL_RESOURCE_WDG1 (279UL)
  1023. #define SYSCTL_RESOURCE_WDG2 (280UL)
  1024. #define SYSCTL_RESOURCE_WDG3 (281UL)
  1025. #define SYSCTL_RESOURCE_GPTMR0 (282UL)
  1026. #define SYSCTL_RESOURCE_GPTMR1 (283UL)
  1027. #define SYSCTL_RESOURCE_GPTMR2 (284UL)
  1028. #define SYSCTL_RESOURCE_GPTMR3 (285UL)
  1029. #define SYSCTL_RESOURCE_GPTMR4 (286UL)
  1030. #define SYSCTL_RESOURCE_GPTMR5 (287UL)
  1031. #define SYSCTL_RESOURCE_GPTMR6 (288UL)
  1032. #define SYSCTL_RESOURCE_GPTMR7 (289UL)
  1033. #define SYSCTL_RESOURCE_UART0 (290UL)
  1034. #define SYSCTL_RESOURCE_UART1 (291UL)
  1035. #define SYSCTL_RESOURCE_UART2 (292UL)
  1036. #define SYSCTL_RESOURCE_UART3 (293UL)
  1037. #define SYSCTL_RESOURCE_UART4 (294UL)
  1038. #define SYSCTL_RESOURCE_UART5 (295UL)
  1039. #define SYSCTL_RESOURCE_UART6 (296UL)
  1040. #define SYSCTL_RESOURCE_UART7 (297UL)
  1041. #define SYSCTL_RESOURCE_UART8 (298UL)
  1042. #define SYSCTL_RESOURCE_UART9 (299UL)
  1043. #define SYSCTL_RESOURCE_UART10 (300UL)
  1044. #define SYSCTL_RESOURCE_UART11 (301UL)
  1045. #define SYSCTL_RESOURCE_UART12 (302UL)
  1046. #define SYSCTL_RESOURCE_UART13 (303UL)
  1047. #define SYSCTL_RESOURCE_UART14 (304UL)
  1048. #define SYSCTL_RESOURCE_UART15 (305UL)
  1049. #define SYSCTL_RESOURCE_I2C0 (306UL)
  1050. #define SYSCTL_RESOURCE_I2C1 (307UL)
  1051. #define SYSCTL_RESOURCE_I2C2 (308UL)
  1052. #define SYSCTL_RESOURCE_I2C3 (309UL)
  1053. #define SYSCTL_RESOURCE_SPI0 (310UL)
  1054. #define SYSCTL_RESOURCE_SPI1 (311UL)
  1055. #define SYSCTL_RESOURCE_SPI2 (312UL)
  1056. #define SYSCTL_RESOURCE_SPI3 (313UL)
  1057. #define SYSCTL_RESOURCE_CAN0 (314UL)
  1058. #define SYSCTL_RESOURCE_CAN1 (315UL)
  1059. #define SYSCTL_RESOURCE_CAN2 (316UL)
  1060. #define SYSCTL_RESOURCE_CAN3 (317UL)
  1061. #define SYSCTL_RESOURCE_PTPC (318UL)
  1062. #define SYSCTL_RESOURCE_ADC0 (319UL)
  1063. #define SYSCTL_RESOURCE_ADC1 (320UL)
  1064. #define SYSCTL_RESOURCE_ADC2 (321UL)
  1065. #define SYSCTL_RESOURCE_ADC3 (322UL)
  1066. #define SYSCTL_RESOURCE_ACMP (323UL)
  1067. #define SYSCTL_RESOURCE_I2S0 (324UL)
  1068. #define SYSCTL_RESOURCE_I2S1 (325UL)
  1069. #define SYSCTL_RESOURCE_I2S2 (326UL)
  1070. #define SYSCTL_RESOURCE_I2S3 (327UL)
  1071. #define SYSCTL_RESOURCE_PDM (328UL)
  1072. #define SYSCTL_RESOURCE_DAO (329UL)
  1073. #define SYSCTL_RESOURCE_SYNT (330UL)
  1074. #define SYSCTL_RESOURCE_MOT0 (331UL)
  1075. #define SYSCTL_RESOURCE_MOT1 (332UL)
  1076. #define SYSCTL_RESOURCE_MOT2 (333UL)
  1077. #define SYSCTL_RESOURCE_MOT3 (334UL)
  1078. #define SYSCTL_RESOURCE_LCDC (335UL)
  1079. #define SYSCTL_RESOURCE_CAM0 (336UL)
  1080. #define SYSCTL_RESOURCE_CAM1 (337UL)
  1081. #define SYSCTL_RESOURCE_JPEG (338UL)
  1082. #define SYSCTL_RESOURCE_PDMA (339UL)
  1083. #define SYSCTL_RESOURCE_ENET0 (340UL)
  1084. #define SYSCTL_RESOURCE_ENET1 (341UL)
  1085. #define SYSCTL_RESOURCE_NTMR0 (342UL)
  1086. #define SYSCTL_RESOURCE_NTMR1 (343UL)
  1087. #define SYSCTL_RESOURCE_SDXC0 (344UL)
  1088. #define SYSCTL_RESOURCE_SDXC1 (345UL)
  1089. #define SYSCTL_RESOURCE_USB0 (346UL)
  1090. #define SYSCTL_RESOURCE_USB1 (347UL)
  1091. #define SYSCTL_RESOURCE_REF0 (348UL)
  1092. #define SYSCTL_RESOURCE_REF1 (349UL)
  1093. /* GROUP0 register group index macro definition */
  1094. #define SYSCTL_GROUP0_0 (0UL)
  1095. #define SYSCTL_GROUP0_1 (1UL)
  1096. #define SYSCTL_GROUP0_2 (2UL)
  1097. /* GROUP1 register group index macro definition */
  1098. #define SYSCTL_GROUP1_0 (0UL)
  1099. #define SYSCTL_GROUP1_1 (1UL)
  1100. #define SYSCTL_GROUP1_2 (2UL)
  1101. /* AFFILIATE register group index macro definition */
  1102. #define SYSCTL_AFFILIATE_CPU0 (0UL)
  1103. #define SYSCTL_AFFILIATE_CPU1 (1UL)
  1104. /* RETENTION register group index macro definition */
  1105. #define SYSCTL_RETENTION_CPU0 (0UL)
  1106. #define SYSCTL_RETENTION_CPU1 (1UL)
  1107. /* POWER register group index macro definition */
  1108. #define SYSCTL_POWER_CPU0 (0UL)
  1109. #define SYSCTL_POWER_CPU1 (1UL)
  1110. #define SYSCTL_POWER_CON (2UL)
  1111. #define SYSCTL_POWER_VIS (3UL)
  1112. /* RESET register group index macro definition */
  1113. #define SYSCTL_RESET_SOC (0UL)
  1114. #define SYSCTL_RESET_CON (1UL)
  1115. #define SYSCTL_RESET_VIS (2UL)
  1116. #define SYSCTL_RESET_CPU0 (3UL)
  1117. #define SYSCTL_RESET_CPU1 (4UL)
  1118. /* CLOCK register group index macro definition */
  1119. #define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL)
  1120. #define SYSCTL_CLOCK_CLK_TOP_MCHTMR0 (1UL)
  1121. #define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL)
  1122. #define SYSCTL_CLOCK_CLK_TOP_MCHTMR (3UL)
  1123. #define SYSCTL_CLOCK_CLK_TOP_AXI (4UL)
  1124. #define SYSCTL_CLOCK_CLK_TOP_CONN (5UL)
  1125. #define SYSCTL_CLOCK_CLK_TOP_VIS (6UL)
  1126. #define SYSCTL_CLOCK_CLK_TOP_AHB (7UL)
  1127. #define SYSCTL_CLOCK_CLK_TOP_FEMC (8UL)
  1128. #define SYSCTL_CLOCK_CLK_TOP_XPI0 (9UL)
  1129. #define SYSCTL_CLOCK_CLK_TOP_XPI1 (10UL)
  1130. #define SYSCTL_CLOCK_CLK_TOP_GPTMR0 (11UL)
  1131. #define SYSCTL_CLOCK_CLK_TOP_GPTMR1 (12UL)
  1132. #define SYSCTL_CLOCK_CLK_TOP_GPTMR2 (13UL)
  1133. #define SYSCTL_CLOCK_CLK_TOP_GPTMR3 (14UL)
  1134. #define SYSCTL_CLOCK_CLK_TOP_GPTMR4 (15UL)
  1135. #define SYSCTL_CLOCK_CLK_TOP_GPTMR5 (16UL)
  1136. #define SYSCTL_CLOCK_CLK_TOP_GPTMR6 (17UL)
  1137. #define SYSCTL_CLOCK_CLK_TOP_GPTMR7 (18UL)
  1138. #define SYSCTL_CLOCK_CLK_TOP_UART0 (19UL)
  1139. #define SYSCTL_CLOCK_CLK_TOP_UART1 (20UL)
  1140. #define SYSCTL_CLOCK_CLK_TOP_UART2 (21UL)
  1141. #define SYSCTL_CLOCK_CLK_TOP_UART3 (22UL)
  1142. #define SYSCTL_CLOCK_CLK_TOP_UART4 (23UL)
  1143. #define SYSCTL_CLOCK_CLK_TOP_UART5 (24UL)
  1144. #define SYSCTL_CLOCK_CLK_TOP_UART6 (25UL)
  1145. #define SYSCTL_CLOCK_CLK_TOP_UART7 (26UL)
  1146. #define SYSCTL_CLOCK_CLK_TOP_UART8 (27UL)
  1147. #define SYSCTL_CLOCK_CLK_TOP_UART9 (28UL)
  1148. #define SYSCTL_CLOCK_CLK_TOP_UART10 (29UL)
  1149. #define SYSCTL_CLOCK_CLK_TOP_UART11 (30UL)
  1150. #define SYSCTL_CLOCK_CLK_TOP_UART12 (31UL)
  1151. #define SYSCTL_CLOCK_CLK_TOP_UART13 (32UL)
  1152. #define SYSCTL_CLOCK_CLK_TOP_UART14 (33UL)
  1153. #define SYSCTL_CLOCK_CLK_TOP_UART15 (34UL)
  1154. #define SYSCTL_CLOCK_CLK_TOP_I2C0 (35UL)
  1155. #define SYSCTL_CLOCK_CLK_TOP_I2C1 (36UL)
  1156. #define SYSCTL_CLOCK_CLK_TOP_I2C2 (37UL)
  1157. #define SYSCTL_CLOCK_CLK_TOP_I2C3 (38UL)
  1158. #define SYSCTL_CLOCK_CLK_TOP_SPI0 (39UL)
  1159. #define SYSCTL_CLOCK_CLK_TOP_SPI1 (40UL)
  1160. #define SYSCTL_CLOCK_CLK_TOP_SPI2 (41UL)
  1161. #define SYSCTL_CLOCK_CLK_TOP_SPI3 (42UL)
  1162. #define SYSCTL_CLOCK_CLK_TOP_CAN0 (43UL)
  1163. #define SYSCTL_CLOCK_CLK_TOP_CAN1 (44UL)
  1164. #define SYSCTL_CLOCK_CLK_TOP_CAN2 (45UL)
  1165. #define SYSCTL_CLOCK_CLK_TOP_CAN3 (46UL)
  1166. #define SYSCTL_CLOCK_CLK_TOP_PTPC (47UL)
  1167. #define SYSCTL_CLOCK_CLK_TOP_ANA0 (48UL)
  1168. #define SYSCTL_CLOCK_CLK_TOP_ANA1 (49UL)
  1169. #define SYSCTL_CLOCK_CLK_TOP_ANA2 (50UL)
  1170. #define SYSCTL_CLOCK_CLK_TOP_AUD0 (51UL)
  1171. #define SYSCTL_CLOCK_CLK_TOP_AUD1 (52UL)
  1172. #define SYSCTL_CLOCK_CLK_TOP_AUD2 (53UL)
  1173. #define SYSCTL_CLOCK_CLK_TOP_LCDC (54UL)
  1174. #define SYSCTL_CLOCK_CLK_TOP_CAM0 (55UL)
  1175. #define SYSCTL_CLOCK_CLK_TOP_CAM1 (56UL)
  1176. #define SYSCTL_CLOCK_CLK_TOP_ENET0 (57UL)
  1177. #define SYSCTL_CLOCK_CLK_TOP_ENET1 (58UL)
  1178. #define SYSCTL_CLOCK_CLK_TOP_PTP0 (59UL)
  1179. #define SYSCTL_CLOCK_CLK_TOP_PTP1 (60UL)
  1180. #define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL)
  1181. #define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL)
  1182. #define SYSCTL_CLOCK_CLK_TOP_NTMR0 (63UL)
  1183. #define SYSCTL_CLOCK_CLK_TOP_NTMR1 (64UL)
  1184. #define SYSCTL_CLOCK_CLK_TOP_SDXC0 (65UL)
  1185. #define SYSCTL_CLOCK_CLK_TOP_SDXC1 (66UL)
  1186. /* ADCCLK register group index macro definition */
  1187. #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
  1188. #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
  1189. #define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL)
  1190. #define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL)
  1191. /* I2SCLK register group index macro definition */
  1192. #define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL)
  1193. #define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL)
  1194. #define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL)
  1195. #define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL)
  1196. /* MONITOR register group index macro definition */
  1197. #define SYSCTL_MONITOR_SLICE0 (0UL)
  1198. #define SYSCTL_MONITOR_SLICE1 (1UL)
  1199. #define SYSCTL_MONITOR_SLICE2 (2UL)
  1200. #define SYSCTL_MONITOR_SLICE3 (3UL)
  1201. /* GPR register group index macro definition */
  1202. #define SYSCTL_CPU_GPR_GPR0 (0UL)
  1203. #define SYSCTL_CPU_GPR_GPR1 (1UL)
  1204. #define SYSCTL_CPU_GPR_GPR2 (2UL)
  1205. #define SYSCTL_CPU_GPR_GPR3 (3UL)
  1206. #define SYSCTL_CPU_GPR_GPR4 (4UL)
  1207. #define SYSCTL_CPU_GPR_GPR5 (5UL)
  1208. #define SYSCTL_CPU_GPR_GPR6 (6UL)
  1209. #define SYSCTL_CPU_GPR_GPR7 (7UL)
  1210. #define SYSCTL_CPU_GPR_GPR8 (8UL)
  1211. #define SYSCTL_CPU_GPR_GPR9 (9UL)
  1212. #define SYSCTL_CPU_GPR_GPR10 (10UL)
  1213. #define SYSCTL_CPU_GPR_GPR11 (11UL)
  1214. #define SYSCTL_CPU_GPR_GPR12 (12UL)
  1215. #define SYSCTL_CPU_GPR_GPR13 (13UL)
  1216. /* WAKEUP_STATUS register group index macro definition */
  1217. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
  1218. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
  1219. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
  1220. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
  1221. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL)
  1222. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL)
  1223. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS6 (6UL)
  1224. #define SYSCTL_CPU_WAKEUP_STATUS_STATUS7 (7UL)
  1225. /* WAKEUP_ENABLE register group index macro definition */
  1226. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
  1227. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
  1228. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
  1229. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
  1230. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL)
  1231. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL)
  1232. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE6 (6UL)
  1233. #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE7 (7UL)
  1234. /* CPU register group index macro definition */
  1235. #define SYSCTL_CPU_CPU0 (0UL)
  1236. #define SYSCTL_CPU_CPU1 (1UL)
  1237. #endif /* HPM_SYSCTL_H */