drv_uart.c 8.2 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-01-09 Lyons first version
  9. */
  10. #include <rtconfig.h>
  11. #ifdef RT_USING_SERIAL
  12. #include "board.h"
  13. #include "drv_uart.h"
  14. #include "drv_common.h"
  15. enum
  16. {
  17. #ifdef BSP_USING_UART1
  18. eDevUart_UART1,
  19. #endif
  20. #ifdef BSP_USING_UART2
  21. eDevUart_UART2,
  22. #endif
  23. #ifdef BSP_USING_UART3
  24. eDevUart_UART3,
  25. #endif
  26. #ifdef BSP_USING_UART4
  27. eDevUart_UART4,
  28. #endif
  29. #ifdef BSP_USING_UART5
  30. eDevUart_UART5,
  31. #endif
  32. #ifdef BSP_USING_UART6
  33. eDevUart_UART6,
  34. #endif
  35. #ifdef BSP_USING_UART7
  36. eDevUart_UART7,
  37. #endif
  38. #ifdef BSP_USING_UART8
  39. eDevUart_UART8,
  40. #endif
  41. eDevUart_Max,
  42. };
  43. _internal_rw struct imx_uart _s_uart[eDevUart_Max] = {
  44. #ifdef BSP_USING_UART1
  45. {
  46. .name = "uart0",
  47. .periph.paddr = IMX6ULL_UART1_BASE,
  48. .irqno = UART1_IRQn,
  49. .gpio = {
  50. {IOMUXC_UART1_TX_DATA_UART1_TX, 0, 0x10B0},
  51. {IOMUXC_UART1_RX_DATA_UART1_RX, 0, 0x10B0},
  52. },
  53. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  54. .param = RT_SERIAL_CONFIG_115200N81,
  55. },
  56. #endif
  57. #ifdef BSP_USING_UART2
  58. {
  59. .name = "uart1",
  60. .periph.paddr = IMX6ULL_UART2_BASE,
  61. .irqno = UART2_IRQn,
  62. .gpio = {
  63. {IOMUXC_UART2_TX_DATA_UART2_TX, 0, 0x10B0},
  64. {IOMUXC_UART2_RX_DATA_UART2_RX, 0, 0x10B0},
  65. },
  66. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  67. .param = RT_SERIAL_CONFIG_DEFAULT,
  68. },
  69. #endif
  70. #ifdef BSP_USING_UART3
  71. {
  72. .name = "uart2",
  73. .periph.paddr = IMX6ULL_UART3_BASE,
  74. .irqno = UART3_IRQn,
  75. .gpio = {
  76. {IOMUXC_UART3_TX_DATA_UART3_TX, 0, 0x10B0},
  77. {IOMUXC_UART3_RX_DATA_UART3_RX, 0, 0x10B0},
  78. },
  79. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  80. .param = RT_SERIAL_CONFIG_DEFAULT,
  81. },
  82. #endif
  83. #ifdef BSP_USING_UART4
  84. {
  85. .name = "uart3",
  86. .periph.paddr = IMX6ULL_UART4_BASE,
  87. .irqno = UART4_IRQn,
  88. .gpio = {
  89. {IOMUXC_UART4_TX_DATA_UART4_TX, 0, 0x10B0},
  90. {IOMUXC_UART4_RX_DATA_UART4_RX, 0, 0x10B0},
  91. },
  92. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  93. .param = RT_SERIAL_CONFIG_DEFAULT,
  94. },
  95. #endif
  96. #ifdef BSP_USING_UART5
  97. {
  98. .name = "uart4",
  99. .periph.paddr = IMX6ULL_UART5_BASE,
  100. .irqno = UART5_IRQn,
  101. .gpio = {
  102. {IOMUXC_UART5_TX_DATA_UART5_TX, 0, 0x10B0},
  103. {IOMUXC_UART5_RX_DATA_UART5_RX, 0, 0x10B0},
  104. },
  105. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  106. .param = RT_SERIAL_CONFIG_DEFAULT,
  107. },
  108. #endif
  109. #ifdef BSP_USING_UART6
  110. {
  111. .name = "uart5",
  112. .periph.paddr = IMX6ULL_UART6_BASE,
  113. .irqno = UART6_IRQn,
  114. .gpio = {
  115. {IOMUXC_ENET2_RX_DATA1_UART6_TX, 0, 0x10B0},
  116. {IOMUXC_ENET2_RX_DATA0_UART6_RX, 0, 0x10B0},
  117. },
  118. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  119. .param = RT_SERIAL_CONFIG_DEFAULT,
  120. },
  121. #endif
  122. #ifdef BSP_USING_UART7
  123. {
  124. .name = "uart6",
  125. .periph.paddr = IMX6ULL_UART7_BASE,
  126. .irqno = UART7_IRQn,
  127. .gpio = {
  128. {IOMUXC_ENET2_TX_DATA0_UART7_TX, 0, 0x10B0},
  129. {IOMUXC_ENET2_RX_EN_UART7_RX, 0, 0x10B0},
  130. },
  131. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  132. .param = RT_SERIAL_CONFIG_DEFAULT,
  133. },
  134. #endif
  135. #ifdef BSP_USING_UART8
  136. {
  137. .name = "uart7",
  138. .periph.paddr = IMX6ULL_UART8_BASE,
  139. .irqno = UART8_IRQn,
  140. .gpio = {
  141. {IOMUXC_ENET2_TX_DATA1_UART8_TX, 0, 0x10B0},
  142. {IOMUXC_ENET2_TX_EN_UART8_RX, 0, 0x10B0},
  143. },
  144. .flag = (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX),
  145. .param = RT_SERIAL_CONFIG_DEFAULT,
  146. },
  147. #endif
  148. };
  149. static void _uart_gpio_init( struct imx_uart *device )
  150. {
  151. for (int i=0; i<GET_ARRAY_NUM(device->gpio); i++)
  152. {
  153. imx6ull_gpio_init(&device->gpio[i]);
  154. }
  155. }
  156. static rt_err_t _uart_ops_configure( struct rt_serial_device *dev,
  157. struct serial_configure *cfg )
  158. {
  159. struct imx_uart *uart = RT_NULL;
  160. UART_Type *periph = RT_NULL;
  161. rt_uint32_t reg_value;
  162. RT_ASSERT(RT_NULL != dev);
  163. RT_ASSERT(RT_NULL != cfg);
  164. uart = (struct imx_uart*)dev;
  165. periph = (UART_Type*)uart->periph.vaddr;
  166. _uart_gpio_init(uart);
  167. periph->UCR1 &= ~UART_UCR1_UARTEN_MASK;
  168. periph->UFCR &= ~UART_UFCR_RFDIV_MASK;
  169. periph->UFCR |= UART_UFCR_RFDIV(5);
  170. RT_ASSERT(cfg->baud_rate <= BAUD_RATE_921600);
  171. periph->UBIR = UART_UBIR_INC(15);
  172. periph->UBMR = UART_UBMR_MOD(HW_UART_BUS_CLOCK / cfg->baud_rate - 1);
  173. reg_value = 0;
  174. switch (cfg->data_bits)
  175. {
  176. case DATA_BITS_7:
  177. reg_value |= UART_UCR2_WS(0);
  178. break;
  179. default:
  180. reg_value |= UART_UCR2_WS(1);
  181. break;
  182. }
  183. switch (cfg->stop_bits)
  184. {
  185. case STOP_BITS_2:
  186. reg_value |= UART_UCR2_STPB(1);
  187. break;
  188. default:
  189. reg_value |= UART_UCR2_STPB(0);
  190. break;
  191. }
  192. switch (cfg->parity)
  193. {
  194. case PARITY_ODD:
  195. reg_value |= UART_UCR2_PREN(1);
  196. reg_value |= UART_UCR2_PROE(1);
  197. break;
  198. case PARITY_EVEN:
  199. reg_value |= UART_UCR2_PREN(1);
  200. reg_value |= UART_UCR2_PROE(0);
  201. break;
  202. default:
  203. reg_value |= UART_UCR2_PREN(0);
  204. reg_value |= UART_UCR2_PROE(0);
  205. break;
  206. }
  207. periph->UCR3 |= UART_UCR3_RXDMUXSEL(1); //this bit should always be set!
  208. periph->UCR2 |= reg_value | UART_UCR2_IRTS(1) | UART_UCR2_TXEN(1) | UART_UCR2_RXEN(1);
  209. periph->UCR1 |= UART_UCR1_UARTEN(1);
  210. return RT_EOK;
  211. }
  212. static rt_err_t _uart_ops_control( struct rt_serial_device *dev,
  213. int cmd,
  214. void *arg )
  215. {
  216. struct imx_uart *uart = RT_NULL;
  217. UART_Type *periph = RT_NULL;
  218. rt_err_t result;
  219. RT_ASSERT(RT_NULL != dev);
  220. uart = (struct imx_uart*)dev;
  221. periph = (UART_Type*)uart->periph.vaddr;
  222. result = RT_EOK;
  223. switch (cmd)
  224. {
  225. case RT_DEVICE_CTRL_CLR_INT:
  226. periph->UCR4 &= ~UART_UCR4_DREN_MASK;
  227. periph->UCR4 |= UART_UCR4_DREN(0);
  228. break;
  229. case RT_DEVICE_CTRL_SET_INT:
  230. periph->UCR4 |= UART_UCR4_DREN(1);
  231. rt_hw_interrupt_umask(uart->irqno);
  232. break;
  233. default:
  234. result = -RT_EINVAL;
  235. break;
  236. }
  237. return result;
  238. }
  239. static int _uart_ops_putc( struct rt_serial_device *dev,
  240. char ch )
  241. {
  242. struct imx_uart *uart = RT_NULL;
  243. UART_Type *periph = RT_NULL;
  244. RT_ASSERT(RT_NULL != dev);
  245. uart = (struct imx_uart*)dev;
  246. periph = (UART_Type*)uart->periph.vaddr;
  247. while (0 == (periph->USR2 & UART_USR2_TXDC_MASK));
  248. periph->UTXD = ch;
  249. return 1;
  250. }
  251. static int _uart_ops_getc( struct rt_serial_device *dev )
  252. {
  253. struct imx_uart *uart = RT_NULL;
  254. UART_Type *periph = RT_NULL;
  255. int ch;
  256. RT_ASSERT(RT_NULL != dev);
  257. uart = (struct imx_uart*)dev;
  258. periph = (UART_Type*)uart->periph.vaddr;
  259. ch = (0 == (periph->USR2 & UART_USR2_RDR_MASK)) ? -1 : periph->URXD;
  260. return ch;
  261. }
  262. _internal_ro struct rt_uart_ops _k_uart_ops =
  263. {
  264. _uart_ops_configure, /* configure */
  265. _uart_ops_control, /* control */
  266. _uart_ops_putc, /* putc */
  267. _uart_ops_getc, /* getc */
  268. RT_NULL, /* dma_transmit */
  269. };
  270. static void _uart_isr( int irqno, void* parameter )
  271. {
  272. struct rt_serial_device *serial;
  273. rt_interrupt_enter();
  274. serial = (struct rt_serial_device *)parameter;
  275. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  276. rt_interrupt_leave();
  277. }
  278. int rt_hw_uart_init(void)
  279. {
  280. for (int idx=0; idx<GET_ARRAY_NUM(_s_uart); idx++)
  281. {
  282. _s_uart[idx].periph.vaddr = platform_get_periph_vaddr(_s_uart[idx].periph.paddr);
  283. _s_uart[idx].parent.ops = &_k_uart_ops;
  284. rt_memcpy(&_s_uart[idx].parent.config, &_s_uart[idx].param, sizeof(struct serial_configure));
  285. rt_hw_serial_register( &_s_uart[idx].parent,
  286. _s_uart[idx].name,
  287. _s_uart[idx].flag,
  288. RT_NULL );
  289. rt_hw_interrupt_install(_s_uart[idx].irqno, _uart_isr, &_s_uart[idx].parent, _s_uart[idx].name);
  290. }
  291. return RT_EOK;
  292. }
  293. INIT_BOARD_EXPORT(rt_hw_uart_init);
  294. #endif //#ifdef RT_USING_SERIAL