cmsis_armclang.h 54 KB

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  1. /**************************************************************************//**
  2. * @file cmsis_armclang.h
  3. * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
  4. * @version V5.0.3
  5. * @date 27. March 2017
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
  25. #ifndef __CMSIS_ARMCLANG_H
  26. #define __CMSIS_ARMCLANG_H
  27. #ifndef __ARM_COMPAT_H
  28. #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
  29. #endif
  30. /* CMSIS compiler specific defines */
  31. #ifndef __ASM
  32. #define __ASM __asm
  33. #endif
  34. #ifndef __INLINE
  35. #define __INLINE __inline
  36. #endif
  37. #ifndef __STATIC_INLINE
  38. #define __STATIC_INLINE static __inline
  39. #endif
  40. #ifndef __NO_RETURN
  41. #define __NO_RETURN __attribute__((noreturn))
  42. #endif
  43. #ifndef __USED
  44. #define __USED __attribute__((used))
  45. #endif
  46. #ifndef __WEAK
  47. #define __WEAK __attribute__((weak))
  48. #endif
  49. #ifndef __PACKED
  50. #define __PACKED __attribute__((packed, aligned(1)))
  51. #endif
  52. #ifndef __PACKED_STRUCT
  53. #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
  54. #endif
  55. #ifndef __PACKED_UNION
  56. #define __PACKED_UNION union __attribute__((packed, aligned(1)))
  57. #endif
  58. #ifndef __UNALIGNED_UINT32 /* deprecated */
  59. #pragma clang diagnostic push
  60. #pragma clang diagnostic ignored "-Wpacked"
  61. /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
  62. struct __attribute__((packed)) T_UINT32
  63. {
  64. uint32_t v;
  65. };
  66. #pragma clang diagnostic pop
  67. #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
  68. #endif
  69. #ifndef __UNALIGNED_UINT16_WRITE
  70. #pragma clang diagnostic push
  71. #pragma clang diagnostic ignored "-Wpacked"
  72. /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
  73. __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  74. #pragma clang diagnostic pop
  75. #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
  76. #endif
  77. #ifndef __UNALIGNED_UINT16_READ
  78. #pragma clang diagnostic push
  79. #pragma clang diagnostic ignored "-Wpacked"
  80. /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
  81. __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  82. #pragma clang diagnostic pop
  83. #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
  84. #endif
  85. #ifndef __UNALIGNED_UINT32_WRITE
  86. #pragma clang diagnostic push
  87. #pragma clang diagnostic ignored "-Wpacked"
  88. /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
  89. __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  90. #pragma clang diagnostic pop
  91. #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
  92. #endif
  93. #ifndef __UNALIGNED_UINT32_READ
  94. #pragma clang diagnostic push
  95. #pragma clang diagnostic ignored "-Wpacked"
  96. /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
  97. __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
  98. #pragma clang diagnostic pop
  99. #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
  100. #endif
  101. #ifndef __ALIGNED
  102. #define __ALIGNED(x) __attribute__((aligned(x)))
  103. #endif
  104. #ifndef __RESTRICT
  105. #define __RESTRICT __restrict
  106. #endif
  107. /* ########################### Core Function Access ########################### */
  108. /** \ingroup CMSIS_Core_FunctionInterface
  109. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  110. @{
  111. */
  112. /**
  113. \brief Enable IRQ Interrupts
  114. \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
  115. Can only be executed in Privileged modes.
  116. */
  117. /* intrinsic void __enable_irq(); see arm_compat.h */
  118. /**
  119. \brief Disable IRQ Interrupts
  120. \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  121. Can only be executed in Privileged modes.
  122. */
  123. /* intrinsic void __disable_irq(); see arm_compat.h */
  124. /**
  125. \brief Get Control Register
  126. \details Returns the content of the Control Register.
  127. \return Control Register value
  128. */
  129. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
  130. {
  131. uint32_t result;
  132. __ASM volatile("MRS %0, control" : "=r"(result));
  133. return (result);
  134. }
  135. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  136. /**
  137. \brief Get Control Register (non-secure)
  138. \details Returns the content of the non-secure Control Register when in secure mode.
  139. \return non-secure Control Register value
  140. */
  141. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
  142. {
  143. uint32_t result;
  144. __ASM volatile("MRS %0, control_ns" : "=r"(result));
  145. return (result);
  146. }
  147. #endif
  148. /**
  149. \brief Set Control Register
  150. \details Writes the given value to the Control Register.
  151. \param [in] control Control Register value to set
  152. */
  153. __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
  154. {
  155. __ASM volatile("MSR control, %0" : : "r"(control) : "memory");
  156. }
  157. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  158. /**
  159. \brief Set Control Register (non-secure)
  160. \details Writes the given value to the non-secure Control Register when in secure state.
  161. \param [in] control Control Register value to set
  162. */
  163. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
  164. {
  165. __ASM volatile("MSR control_ns, %0" : : "r"(control) : "memory");
  166. }
  167. #endif
  168. /**
  169. \brief Get IPSR Register
  170. \details Returns the content of the IPSR Register.
  171. \return IPSR Register value
  172. */
  173. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
  174. {
  175. uint32_t result;
  176. __ASM volatile("MRS %0, ipsr" : "=r"(result));
  177. return (result);
  178. }
  179. /**
  180. \brief Get APSR Register
  181. \details Returns the content of the APSR Register.
  182. \return APSR Register value
  183. */
  184. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
  185. {
  186. uint32_t result;
  187. __ASM volatile("MRS %0, apsr" : "=r"(result));
  188. return (result);
  189. }
  190. /**
  191. \brief Get xPSR Register
  192. \details Returns the content of the xPSR Register.
  193. \return xPSR Register value
  194. */
  195. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
  196. {
  197. uint32_t result;
  198. __ASM volatile("MRS %0, xpsr" : "=r"(result));
  199. return (result);
  200. }
  201. /**
  202. \brief Get Process Stack Pointer
  203. \details Returns the current value of the Process Stack Pointer (PSP).
  204. \return PSP Register value
  205. */
  206. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
  207. {
  208. register uint32_t result;
  209. __ASM volatile("MRS %0, psp" : "=r"(result));
  210. return (result);
  211. }
  212. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  213. /**
  214. \brief Get Process Stack Pointer (non-secure)
  215. \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
  216. \return PSP Register value
  217. */
  218. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
  219. {
  220. register uint32_t result;
  221. __ASM volatile("MRS %0, psp_ns" : "=r"(result));
  222. return (result);
  223. }
  224. #endif
  225. /**
  226. \brief Set Process Stack Pointer
  227. \details Assigns the given value to the Process Stack Pointer (PSP).
  228. \param [in] topOfProcStack Process Stack Pointer value to set
  229. */
  230. __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
  231. {
  232. __ASM volatile("MSR psp, %0" : : "r"(topOfProcStack) :);
  233. }
  234. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  235. /**
  236. \brief Set Process Stack Pointer (non-secure)
  237. \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
  238. \param [in] topOfProcStack Process Stack Pointer value to set
  239. */
  240. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
  241. {
  242. __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack) :);
  243. }
  244. #endif
  245. /**
  246. \brief Get Main Stack Pointer
  247. \details Returns the current value of the Main Stack Pointer (MSP).
  248. \return MSP Register value
  249. */
  250. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
  251. {
  252. register uint32_t result;
  253. __ASM volatile("MRS %0, msp" : "=r"(result));
  254. return (result);
  255. }
  256. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  257. /**
  258. \brief Get Main Stack Pointer (non-secure)
  259. \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
  260. \return MSP Register value
  261. */
  262. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
  263. {
  264. register uint32_t result;
  265. __ASM volatile("MRS %0, msp_ns" : "=r"(result));
  266. return (result);
  267. }
  268. #endif
  269. /**
  270. \brief Set Main Stack Pointer
  271. \details Assigns the given value to the Main Stack Pointer (MSP).
  272. \param [in] topOfMainStack Main Stack Pointer value to set
  273. */
  274. __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
  275. {
  276. __ASM volatile("MSR msp, %0" : : "r"(topOfMainStack) :);
  277. }
  278. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  279. /**
  280. \brief Set Main Stack Pointer (non-secure)
  281. \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
  282. \param [in] topOfMainStack Main Stack Pointer value to set
  283. */
  284. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
  285. {
  286. __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack) :);
  287. }
  288. #endif
  289. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  290. /**
  291. \brief Get Stack Pointer (non-secure)
  292. \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
  293. \return SP Register value
  294. */
  295. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
  296. {
  297. register uint32_t result;
  298. __ASM volatile("MRS %0, sp_ns" : "=r"(result));
  299. return (result);
  300. }
  301. /**
  302. \brief Set Stack Pointer (non-secure)
  303. \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
  304. \param [in] topOfStack Stack Pointer value to set
  305. */
  306. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
  307. {
  308. __ASM volatile("MSR sp_ns, %0" : : "r"(topOfStack) :);
  309. }
  310. #endif
  311. /**
  312. \brief Get Priority Mask
  313. \details Returns the current state of the priority mask bit from the Priority Mask Register.
  314. \return Priority Mask value
  315. */
  316. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
  317. {
  318. uint32_t result;
  319. __ASM volatile("MRS %0, primask" : "=r"(result));
  320. return (result);
  321. }
  322. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  323. /**
  324. \brief Get Priority Mask (non-secure)
  325. \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
  326. \return Priority Mask value
  327. */
  328. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
  329. {
  330. uint32_t result;
  331. __ASM volatile("MRS %0, primask_ns" : "=r"(result));
  332. return (result);
  333. }
  334. #endif
  335. /**
  336. \brief Set Priority Mask
  337. \details Assigns the given value to the Priority Mask Register.
  338. \param [in] priMask Priority Mask
  339. */
  340. __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
  341. {
  342. __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory");
  343. }
  344. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  345. /**
  346. \brief Set Priority Mask (non-secure)
  347. \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
  348. \param [in] priMask Priority Mask
  349. */
  350. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
  351. {
  352. __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory");
  353. }
  354. #endif
  355. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  356. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  357. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  358. /**
  359. \brief Enable FIQ
  360. \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
  361. Can only be executed in Privileged modes.
  362. */
  363. #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
  364. /**
  365. \brief Disable FIQ
  366. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
  367. Can only be executed in Privileged modes.
  368. */
  369. #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
  370. /**
  371. \brief Get Base Priority
  372. \details Returns the current value of the Base Priority register.
  373. \return Base Priority register value
  374. */
  375. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
  376. {
  377. uint32_t result;
  378. __ASM volatile("MRS %0, basepri" : "=r"(result));
  379. return (result);
  380. }
  381. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  382. /**
  383. \brief Get Base Priority (non-secure)
  384. \details Returns the current value of the non-secure Base Priority register when in secure state.
  385. \return Base Priority register value
  386. */
  387. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
  388. {
  389. uint32_t result;
  390. __ASM volatile("MRS %0, basepri_ns" : "=r"(result));
  391. return (result);
  392. }
  393. #endif
  394. /**
  395. \brief Set Base Priority
  396. \details Assigns the given value to the Base Priority register.
  397. \param [in] basePri Base Priority value to set
  398. */
  399. __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
  400. {
  401. __ASM volatile("MSR basepri, %0" : : "r"(basePri) : "memory");
  402. }
  403. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  404. /**
  405. \brief Set Base Priority (non-secure)
  406. \details Assigns the given value to the non-secure Base Priority register when in secure state.
  407. \param [in] basePri Base Priority value to set
  408. */
  409. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
  410. {
  411. __ASM volatile("MSR basepri_ns, %0" : : "r"(basePri) : "memory");
  412. }
  413. #endif
  414. /**
  415. \brief Set Base Priority with condition
  416. \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
  417. or the new value increases the BASEPRI priority level.
  418. \param [in] basePri Base Priority value to set
  419. */
  420. __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
  421. {
  422. __ASM volatile("MSR basepri_max, %0" : : "r"(basePri) : "memory");
  423. }
  424. /**
  425. \brief Get Fault Mask
  426. \details Returns the current value of the Fault Mask register.
  427. \return Fault Mask register value
  428. */
  429. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
  430. {
  431. uint32_t result;
  432. __ASM volatile("MRS %0, faultmask" : "=r"(result));
  433. return (result);
  434. }
  435. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  436. /**
  437. \brief Get Fault Mask (non-secure)
  438. \details Returns the current value of the non-secure Fault Mask register when in secure state.
  439. \return Fault Mask register value
  440. */
  441. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
  442. {
  443. uint32_t result;
  444. __ASM volatile("MRS %0, faultmask_ns" : "=r"(result));
  445. return (result);
  446. }
  447. #endif
  448. /**
  449. \brief Set Fault Mask
  450. \details Assigns the given value to the Fault Mask register.
  451. \param [in] faultMask Fault Mask value to set
  452. */
  453. __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
  454. {
  455. __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory");
  456. }
  457. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  458. /**
  459. \brief Set Fault Mask (non-secure)
  460. \details Assigns the given value to the non-secure Fault Mask register when in secure state.
  461. \param [in] faultMask Fault Mask value to set
  462. */
  463. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
  464. {
  465. __ASM volatile("MSR faultmask_ns, %0" : : "r"(faultMask) : "memory");
  466. }
  467. #endif
  468. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  469. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  470. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  471. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  472. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  473. /**
  474. \brief Get Process Stack Pointer Limit
  475. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
  476. \return PSPLIM Register value
  477. */
  478. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
  479. {
  480. register uint32_t result;
  481. __ASM volatile("MRS %0, psplim" : "=r"(result));
  482. return (result);
  483. }
  484. #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
  485. (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  486. /**
  487. \brief Get Process Stack Pointer Limit (non-secure)
  488. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  489. \return PSPLIM Register value
  490. */
  491. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
  492. {
  493. register uint32_t result;
  494. __ASM volatile("MRS %0, psplim_ns" : "=r"(result));
  495. return (result);
  496. }
  497. #endif
  498. /**
  499. \brief Set Process Stack Pointer Limit
  500. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
  501. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
  502. */
  503. __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
  504. {
  505. __ASM volatile("MSR psplim, %0" : : "r"(ProcStackPtrLimit));
  506. }
  507. #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
  508. (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  509. /**
  510. \brief Set Process Stack Pointer (non-secure)
  511. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  512. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
  513. */
  514. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
  515. {
  516. __ASM volatile("MSR psplim_ns, %0\n" : : "r"(ProcStackPtrLimit));
  517. }
  518. #endif
  519. /**
  520. \brief Get Main Stack Pointer Limit
  521. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
  522. \return MSPLIM Register value
  523. */
  524. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
  525. {
  526. register uint32_t result;
  527. __ASM volatile("MRS %0, msplim" : "=r"(result));
  528. return (result);
  529. }
  530. #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
  531. (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  532. /**
  533. \brief Get Main Stack Pointer Limit (non-secure)
  534. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
  535. \return MSPLIM Register value
  536. */
  537. __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
  538. {
  539. register uint32_t result;
  540. __ASM volatile("MRS %0, msplim_ns" : "=r"(result));
  541. return (result);
  542. }
  543. #endif
  544. /**
  545. \brief Set Main Stack Pointer Limit
  546. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
  547. \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
  548. */
  549. __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
  550. {
  551. __ASM volatile("MSR msplim, %0" : : "r"(MainStackPtrLimit));
  552. }
  553. #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
  554. (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  555. /**
  556. \brief Set Main Stack Pointer Limit (non-secure)
  557. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
  558. \param [in] MainStackPtrLimit Main Stack Pointer value to set
  559. */
  560. __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
  561. {
  562. __ASM volatile("MSR msplim_ns, %0" : : "r"(MainStackPtrLimit));
  563. }
  564. #endif
  565. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  566. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  567. #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  568. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  569. /**
  570. \brief Get FPSCR
  571. \details Returns the current value of the Floating Point Status/Control register.
  572. \return Floating Point Status/Control register value
  573. */
  574. /* #define __get_FPSCR __builtin_arm_get_fpscr */
  575. __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
  576. {
  577. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  578. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  579. uint32_t result;
  580. __ASM volatile("VMRS %0, fpscr" : "=r"(result));
  581. return (result);
  582. #else
  583. return (0U);
  584. #endif
  585. }
  586. /**
  587. \brief Set FPSCR
  588. \details Assigns the given value to the Floating Point Status/Control register.
  589. \param [in] fpscr Floating Point Status/Control value to set
  590. */
  591. /* #define __set_FPSCR __builtin_arm_set_fpscr */
  592. __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
  593. {
  594. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  595. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  596. __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "memory");
  597. #else
  598. (void)fpscr;
  599. #endif
  600. }
  601. #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  602. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  603. /*@} end of CMSIS_Core_RegAccFunctions */
  604. /* ########################## Core Instruction Access ######################### */
  605. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  606. Access to dedicated instructions
  607. @{
  608. */
  609. /* Define macros for porting to both thumb1 and thumb2.
  610. * For thumb1, use low register (r0-r7), specified by constraint "l"
  611. * Otherwise, use general registers, specified by constraint "r" */
  612. #if defined (__thumb__) && !defined (__thumb2__)
  613. #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
  614. #define __CMSIS_GCC_USE_REG(r) "l" (r)
  615. #else
  616. #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
  617. #define __CMSIS_GCC_USE_REG(r) "r" (r)
  618. #endif
  619. /**
  620. \brief No Operation
  621. \details No Operation does nothing. This instruction can be used for code alignment purposes.
  622. */
  623. #define __NOP __builtin_arm_nop
  624. /**
  625. \brief Wait For Interrupt
  626. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  627. */
  628. #define __WFI __builtin_arm_wfi
  629. /**
  630. \brief Wait For Event
  631. \details Wait For Event is a hint instruction that permits the processor to enter
  632. a low-power state until one of a number of events occurs.
  633. */
  634. #define __WFE __builtin_arm_wfe
  635. /**
  636. \brief Send Event
  637. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  638. */
  639. #define __SEV __builtin_arm_sev
  640. /**
  641. \brief Instruction Synchronization Barrier
  642. \details Instruction Synchronization Barrier flushes the pipeline in the processor,
  643. so that all instructions following the ISB are fetched from cache or memory,
  644. after the instruction has been completed.
  645. */
  646. #define __ISB() __builtin_arm_isb(0xF);
  647. /**
  648. \brief Data Synchronization Barrier
  649. \details Acts as a special kind of Data Memory Barrier.
  650. It completes when all explicit memory accesses before this instruction complete.
  651. */
  652. #define __DSB() __builtin_arm_dsb(0xF);
  653. /**
  654. \brief Data Memory Barrier
  655. \details Ensures the apparent order of the explicit memory operations before
  656. and after the instruction, without ensuring their completion.
  657. */
  658. #define __DMB() __builtin_arm_dmb(0xF);
  659. /**
  660. \brief Reverse byte order (32 bit)
  661. \details Reverses the byte order in integer value.
  662. \param [in] value Value to reverse
  663. \return Reversed value
  664. */
  665. #define __REV __builtin_bswap32
  666. /**
  667. \brief Reverse byte order (16 bit)
  668. \details Reverses the byte order in two unsigned short values.
  669. \param [in] value Value to reverse
  670. \return Reversed value
  671. */
  672. #define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
  673. #if 0
  674. __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
  675. {
  676. uint32_t result;
  677. __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  678. return (result);
  679. }
  680. #endif
  681. /**
  682. \brief Reverse byte order in signed short value
  683. \details Reverses the byte order in a signed short value with sign extension to integer.
  684. \param [in] value Value to reverse
  685. \return Reversed value
  686. */
  687. /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
  688. __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
  689. {
  690. int32_t result;
  691. __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  692. return (result);
  693. }
  694. /**
  695. \brief Rotate Right in unsigned value (32 bit)
  696. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  697. \param [in] op1 Value to rotate
  698. \param [in] op2 Number of Bits to rotate
  699. \return Rotated value
  700. */
  701. __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
  702. {
  703. return (op1 >> op2) | (op1 << (32U - op2));
  704. }
  705. /**
  706. \brief Breakpoint
  707. \details Causes the processor to enter Debug state.
  708. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  709. \param [in] value is ignored by the processor.
  710. If required, a debugger can use it to store additional information about the breakpoint.
  711. */
  712. #define __BKPT(value) __ASM volatile ("bkpt "#value)
  713. /**
  714. \brief Reverse bit order of value
  715. \details Reverses the bit order of the given value.
  716. \param [in] value Value to reverse
  717. \return Reversed value
  718. */
  719. /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
  720. __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
  721. {
  722. uint32_t result;
  723. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  724. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  725. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  726. __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
  727. #else
  728. int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
  729. result = value; /* r will be reversed bits of v; first get LSB of v */
  730. for (value >>= 1U; value; value >>= 1U)
  731. {
  732. result <<= 1U;
  733. result |= value & 1U;
  734. s--;
  735. }
  736. result <<= s; /* shift when v's highest bits are zero */
  737. #endif
  738. return (result);
  739. }
  740. /**
  741. \brief Count leading zeros
  742. \details Counts the number of leading zeros of a data value.
  743. \param [in] value Value to count the leading zeros
  744. \return number of leading zeros in value
  745. */
  746. #define __CLZ __builtin_clz
  747. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  748. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  749. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  750. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  751. /**
  752. \brief LDR Exclusive (8 bit)
  753. \details Executes a exclusive LDR instruction for 8 bit value.
  754. \param [in] ptr Pointer to data
  755. \return value of type uint8_t at (*ptr)
  756. */
  757. #define __LDREXB (uint8_t)__builtin_arm_ldrex
  758. /**
  759. \brief LDR Exclusive (16 bit)
  760. \details Executes a exclusive LDR instruction for 16 bit values.
  761. \param [in] ptr Pointer to data
  762. \return value of type uint16_t at (*ptr)
  763. */
  764. #define __LDREXH (uint16_t)__builtin_arm_ldrex
  765. /**
  766. \brief LDR Exclusive (32 bit)
  767. \details Executes a exclusive LDR instruction for 32 bit values.
  768. \param [in] ptr Pointer to data
  769. \return value of type uint32_t at (*ptr)
  770. */
  771. #define __LDREXW (uint32_t)__builtin_arm_ldrex
  772. /**
  773. \brief STR Exclusive (8 bit)
  774. \details Executes a exclusive STR instruction for 8 bit values.
  775. \param [in] value Value to store
  776. \param [in] ptr Pointer to location
  777. \return 0 Function succeeded
  778. \return 1 Function failed
  779. */
  780. #define __STREXB (uint32_t)__builtin_arm_strex
  781. /**
  782. \brief STR Exclusive (16 bit)
  783. \details Executes a exclusive STR instruction for 16 bit values.
  784. \param [in] value Value to store
  785. \param [in] ptr Pointer to location
  786. \return 0 Function succeeded
  787. \return 1 Function failed
  788. */
  789. #define __STREXH (uint32_t)__builtin_arm_strex
  790. /**
  791. \brief STR Exclusive (32 bit)
  792. \details Executes a exclusive STR instruction for 32 bit values.
  793. \param [in] value Value to store
  794. \param [in] ptr Pointer to location
  795. \return 0 Function succeeded
  796. \return 1 Function failed
  797. */
  798. #define __STREXW (uint32_t)__builtin_arm_strex
  799. /**
  800. \brief Remove the exclusive lock
  801. \details Removes the exclusive lock which is created by LDREX.
  802. */
  803. #define __CLREX __builtin_arm_clrex
  804. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  805. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  806. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  807. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  808. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  809. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  810. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  811. /**
  812. \brief Signed Saturate
  813. \details Saturates a signed value.
  814. \param [in] value Value to be saturated
  815. \param [in] sat Bit position to saturate to (1..32)
  816. \return Saturated value
  817. */
  818. #define __SSAT __builtin_arm_ssat
  819. /**
  820. \brief Unsigned Saturate
  821. \details Saturates an unsigned value.
  822. \param [in] value Value to be saturated
  823. \param [in] sat Bit position to saturate to (0..31)
  824. \return Saturated value
  825. */
  826. #define __USAT __builtin_arm_usat
  827. /**
  828. \brief Rotate Right with Extend (32 bit)
  829. \details Moves each bit of a bitstring right by one bit.
  830. The carry input is shifted in at the left end of the bitstring.
  831. \param [in] value Value to rotate
  832. \return Rotated value
  833. */
  834. __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
  835. {
  836. uint32_t result;
  837. __ASM volatile("rrx %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value));
  838. return (result);
  839. }
  840. /**
  841. \brief LDRT Unprivileged (8 bit)
  842. \details Executes a Unprivileged LDRT instruction for 8 bit value.
  843. \param [in] ptr Pointer to data
  844. \return value of type uint8_t at (*ptr)
  845. */
  846. __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
  847. {
  848. uint32_t result;
  849. __ASM volatile("ldrbt %0, %1" : "=r"(result) : "Q"(*ptr));
  850. return ((uint8_t) result); /* Add explicit type cast here */
  851. }
  852. /**
  853. \brief LDRT Unprivileged (16 bit)
  854. \details Executes a Unprivileged LDRT instruction for 16 bit values.
  855. \param [in] ptr Pointer to data
  856. \return value of type uint16_t at (*ptr)
  857. */
  858. __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
  859. {
  860. uint32_t result;
  861. __ASM volatile("ldrht %0, %1" : "=r"(result) : "Q"(*ptr));
  862. return ((uint16_t) result); /* Add explicit type cast here */
  863. }
  864. /**
  865. \brief LDRT Unprivileged (32 bit)
  866. \details Executes a Unprivileged LDRT instruction for 32 bit values.
  867. \param [in] ptr Pointer to data
  868. \return value of type uint32_t at (*ptr)
  869. */
  870. __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
  871. {
  872. uint32_t result;
  873. __ASM volatile("ldrt %0, %1" : "=r"(result) : "Q"(*ptr));
  874. return (result);
  875. }
  876. /**
  877. \brief STRT Unprivileged (8 bit)
  878. \details Executes a Unprivileged STRT instruction for 8 bit values.
  879. \param [in] value Value to store
  880. \param [in] ptr Pointer to location
  881. */
  882. __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
  883. {
  884. __ASM volatile("strbt %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
  885. }
  886. /**
  887. \brief STRT Unprivileged (16 bit)
  888. \details Executes a Unprivileged STRT instruction for 16 bit values.
  889. \param [in] value Value to store
  890. \param [in] ptr Pointer to location
  891. */
  892. __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
  893. {
  894. __ASM volatile("strht %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
  895. }
  896. /**
  897. \brief STRT Unprivileged (32 bit)
  898. \details Executes a Unprivileged STRT instruction for 32 bit values.
  899. \param [in] value Value to store
  900. \param [in] ptr Pointer to location
  901. */
  902. __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
  903. {
  904. __ASM volatile("strt %1, %0" : "=Q"(*ptr) : "r"(value));
  905. }
  906. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  907. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  908. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  909. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  910. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  911. /**
  912. \brief Load-Acquire (8 bit)
  913. \details Executes a LDAB instruction for 8 bit value.
  914. \param [in] ptr Pointer to data
  915. \return value of type uint8_t at (*ptr)
  916. */
  917. __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
  918. {
  919. uint32_t result;
  920. __ASM volatile("ldab %0, %1" : "=r"(result) : "Q"(*ptr));
  921. return ((uint8_t) result);
  922. }
  923. /**
  924. \brief Load-Acquire (16 bit)
  925. \details Executes a LDAH instruction for 16 bit values.
  926. \param [in] ptr Pointer to data
  927. \return value of type uint16_t at (*ptr)
  928. */
  929. __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
  930. {
  931. uint32_t result;
  932. __ASM volatile("ldah %0, %1" : "=r"(result) : "Q"(*ptr));
  933. return ((uint16_t) result);
  934. }
  935. /**
  936. \brief Load-Acquire (32 bit)
  937. \details Executes a LDA instruction for 32 bit values.
  938. \param [in] ptr Pointer to data
  939. \return value of type uint32_t at (*ptr)
  940. */
  941. __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
  942. {
  943. uint32_t result;
  944. __ASM volatile("lda %0, %1" : "=r"(result) : "Q"(*ptr));
  945. return (result);
  946. }
  947. /**
  948. \brief Store-Release (8 bit)
  949. \details Executes a STLB instruction for 8 bit values.
  950. \param [in] value Value to store
  951. \param [in] ptr Pointer to location
  952. */
  953. __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
  954. {
  955. __ASM volatile("stlb %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
  956. }
  957. /**
  958. \brief Store-Release (16 bit)
  959. \details Executes a STLH instruction for 16 bit values.
  960. \param [in] value Value to store
  961. \param [in] ptr Pointer to location
  962. */
  963. __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
  964. {
  965. __ASM volatile("stlh %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
  966. }
  967. /**
  968. \brief Store-Release (32 bit)
  969. \details Executes a STL instruction for 32 bit values.
  970. \param [in] value Value to store
  971. \param [in] ptr Pointer to location
  972. */
  973. __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
  974. {
  975. __ASM volatile("stl %1, %0" : "=Q"(*ptr) : "r"((uint32_t)value));
  976. }
  977. /**
  978. \brief Load-Acquire Exclusive (8 bit)
  979. \details Executes a LDAB exclusive instruction for 8 bit value.
  980. \param [in] ptr Pointer to data
  981. \return value of type uint8_t at (*ptr)
  982. */
  983. #define __LDAEXB (uint8_t)__builtin_arm_ldaex
  984. /**
  985. \brief Load-Acquire Exclusive (16 bit)
  986. \details Executes a LDAH exclusive instruction for 16 bit values.
  987. \param [in] ptr Pointer to data
  988. \return value of type uint16_t at (*ptr)
  989. */
  990. #define __LDAEXH (uint16_t)__builtin_arm_ldaex
  991. /**
  992. \brief Load-Acquire Exclusive (32 bit)
  993. \details Executes a LDA exclusive instruction for 32 bit values.
  994. \param [in] ptr Pointer to data
  995. \return value of type uint32_t at (*ptr)
  996. */
  997. #define __LDAEX (uint32_t)__builtin_arm_ldaex
  998. /**
  999. \brief Store-Release Exclusive (8 bit)
  1000. \details Executes a STLB exclusive instruction for 8 bit values.
  1001. \param [in] value Value to store
  1002. \param [in] ptr Pointer to location
  1003. \return 0 Function succeeded
  1004. \return 1 Function failed
  1005. */
  1006. #define __STLEXB (uint32_t)__builtin_arm_stlex
  1007. /**
  1008. \brief Store-Release Exclusive (16 bit)
  1009. \details Executes a STLH exclusive instruction for 16 bit values.
  1010. \param [in] value Value to store
  1011. \param [in] ptr Pointer to location
  1012. \return 0 Function succeeded
  1013. \return 1 Function failed
  1014. */
  1015. #define __STLEXH (uint32_t)__builtin_arm_stlex
  1016. /**
  1017. \brief Store-Release Exclusive (32 bit)
  1018. \details Executes a STL exclusive instruction for 32 bit values.
  1019. \param [in] value Value to store
  1020. \param [in] ptr Pointer to location
  1021. \return 0 Function succeeded
  1022. \return 1 Function failed
  1023. */
  1024. #define __STLEX (uint32_t)__builtin_arm_stlex
  1025. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  1026. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  1027. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
  1028. /* ################### Compiler specific Intrinsics ########################### */
  1029. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  1030. Access to dedicated SIMD instructions
  1031. @{
  1032. */
  1033. #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
  1034. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
  1035. {
  1036. uint32_t result;
  1037. __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1038. return (result);
  1039. }
  1040. __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
  1041. {
  1042. uint32_t result;
  1043. __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1044. return (result);
  1045. }
  1046. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
  1047. {
  1048. uint32_t result;
  1049. __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1050. return (result);
  1051. }
  1052. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
  1053. {
  1054. uint32_t result;
  1055. __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1056. return (result);
  1057. }
  1058. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
  1059. {
  1060. uint32_t result;
  1061. __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1062. return (result);
  1063. }
  1064. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
  1065. {
  1066. uint32_t result;
  1067. __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1068. return (result);
  1069. }
  1070. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
  1071. {
  1072. uint32_t result;
  1073. __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1074. return (result);
  1075. }
  1076. __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
  1077. {
  1078. uint32_t result;
  1079. __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1080. return (result);
  1081. }
  1082. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
  1083. {
  1084. uint32_t result;
  1085. __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1086. return (result);
  1087. }
  1088. __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
  1089. {
  1090. uint32_t result;
  1091. __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1092. return (result);
  1093. }
  1094. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
  1095. {
  1096. uint32_t result;
  1097. __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1098. return (result);
  1099. }
  1100. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
  1101. {
  1102. uint32_t result;
  1103. __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1104. return (result);
  1105. }
  1106. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
  1107. {
  1108. uint32_t result;
  1109. __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1110. return (result);
  1111. }
  1112. __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
  1113. {
  1114. uint32_t result;
  1115. __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1116. return (result);
  1117. }
  1118. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
  1119. {
  1120. uint32_t result;
  1121. __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1122. return (result);
  1123. }
  1124. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
  1125. {
  1126. uint32_t result;
  1127. __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1128. return (result);
  1129. }
  1130. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
  1131. {
  1132. uint32_t result;
  1133. __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1134. return (result);
  1135. }
  1136. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
  1137. {
  1138. uint32_t result;
  1139. __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1140. return (result);
  1141. }
  1142. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
  1143. {
  1144. uint32_t result;
  1145. __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1146. return (result);
  1147. }
  1148. __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
  1149. {
  1150. uint32_t result;
  1151. __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1152. return (result);
  1153. }
  1154. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
  1155. {
  1156. uint32_t result;
  1157. __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1158. return (result);
  1159. }
  1160. __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
  1161. {
  1162. uint32_t result;
  1163. __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1164. return (result);
  1165. }
  1166. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
  1167. {
  1168. uint32_t result;
  1169. __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1170. return (result);
  1171. }
  1172. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
  1173. {
  1174. uint32_t result;
  1175. __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1176. return (result);
  1177. }
  1178. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
  1179. {
  1180. uint32_t result;
  1181. __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1182. return (result);
  1183. }
  1184. __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
  1185. {
  1186. uint32_t result;
  1187. __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1188. return (result);
  1189. }
  1190. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
  1191. {
  1192. uint32_t result;
  1193. __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1194. return (result);
  1195. }
  1196. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
  1197. {
  1198. uint32_t result;
  1199. __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1200. return (result);
  1201. }
  1202. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
  1203. {
  1204. uint32_t result;
  1205. __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1206. return (result);
  1207. }
  1208. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
  1209. {
  1210. uint32_t result;
  1211. __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1212. return (result);
  1213. }
  1214. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
  1215. {
  1216. uint32_t result;
  1217. __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1218. return (result);
  1219. }
  1220. __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
  1221. {
  1222. uint32_t result;
  1223. __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1224. return (result);
  1225. }
  1226. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
  1227. {
  1228. uint32_t result;
  1229. __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1230. return (result);
  1231. }
  1232. __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
  1233. {
  1234. uint32_t result;
  1235. __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1236. return (result);
  1237. }
  1238. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
  1239. {
  1240. uint32_t result;
  1241. __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1242. return (result);
  1243. }
  1244. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
  1245. {
  1246. uint32_t result;
  1247. __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1248. return (result);
  1249. }
  1250. __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
  1251. {
  1252. uint32_t result;
  1253. __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1254. return (result);
  1255. }
  1256. __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
  1257. {
  1258. uint32_t result;
  1259. __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  1260. return (result);
  1261. }
  1262. #define __SSAT16(ARG1,ARG2) \
  1263. ({ \
  1264. int32_t __RES, __ARG1 = (ARG1); \
  1265. __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1266. __RES; \
  1267. })
  1268. #define __USAT16(ARG1,ARG2) \
  1269. ({ \
  1270. uint32_t __RES, __ARG1 = (ARG1); \
  1271. __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1272. __RES; \
  1273. })
  1274. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
  1275. {
  1276. uint32_t result;
  1277. __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1));
  1278. return (result);
  1279. }
  1280. __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
  1281. {
  1282. uint32_t result;
  1283. __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1284. return (result);
  1285. }
  1286. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
  1287. {
  1288. uint32_t result;
  1289. __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1));
  1290. return (result);
  1291. }
  1292. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
  1293. {
  1294. uint32_t result;
  1295. __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1296. return (result);
  1297. }
  1298. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2)
  1299. {
  1300. uint32_t result;
  1301. __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1302. return (result);
  1303. }
  1304. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2)
  1305. {
  1306. uint32_t result;
  1307. __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1308. return (result);
  1309. }
  1310. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3)
  1311. {
  1312. uint32_t result;
  1313. __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  1314. return (result);
  1315. }
  1316. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3)
  1317. {
  1318. uint32_t result;
  1319. __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  1320. return (result);
  1321. }
  1322. __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc)
  1323. {
  1324. union llreg_u
  1325. {
  1326. uint32_t w32[2];
  1327. uint64_t w64;
  1328. } llr;
  1329. llr.w64 = acc;
  1330. #ifndef __ARMEB__ /* Little endian */
  1331. __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
  1332. #else /* Big endian */
  1333. __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
  1334. #endif
  1335. return (llr.w64);
  1336. }
  1337. __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc)
  1338. {
  1339. union llreg_u
  1340. {
  1341. uint32_t w32[2];
  1342. uint64_t w64;
  1343. } llr;
  1344. llr.w64 = acc;
  1345. #ifndef __ARMEB__ /* Little endian */
  1346. __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
  1347. #else /* Big endian */
  1348. __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
  1349. #endif
  1350. return (llr.w64);
  1351. }
  1352. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2)
  1353. {
  1354. uint32_t result;
  1355. __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1356. return (result);
  1357. }
  1358. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2)
  1359. {
  1360. uint32_t result;
  1361. __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1362. return (result);
  1363. }
  1364. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3)
  1365. {
  1366. uint32_t result;
  1367. __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  1368. return (result);
  1369. }
  1370. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3)
  1371. {
  1372. uint32_t result;
  1373. __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3));
  1374. return (result);
  1375. }
  1376. __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc)
  1377. {
  1378. union llreg_u
  1379. {
  1380. uint32_t w32[2];
  1381. uint64_t w64;
  1382. } llr;
  1383. llr.w64 = acc;
  1384. #ifndef __ARMEB__ /* Little endian */
  1385. __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
  1386. #else /* Big endian */
  1387. __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
  1388. #endif
  1389. return (llr.w64);
  1390. }
  1391. __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc)
  1392. {
  1393. union llreg_u
  1394. {
  1395. uint32_t w32[2];
  1396. uint64_t w64;
  1397. } llr;
  1398. llr.w64 = acc;
  1399. #ifndef __ARMEB__ /* Little endian */
  1400. __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1]));
  1401. #else /* Big endian */
  1402. __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0]));
  1403. #endif
  1404. return (llr.w64);
  1405. }
  1406. __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2)
  1407. {
  1408. uint32_t result;
  1409. __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1410. return (result);
  1411. }
  1412. __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD(int32_t op1, int32_t op2)
  1413. {
  1414. int32_t result;
  1415. __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1416. return (result);
  1417. }
  1418. __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB(int32_t op1, int32_t op2)
  1419. {
  1420. int32_t result;
  1421. __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2));
  1422. return (result);
  1423. }
  1424. #if 0
  1425. #define __PKHBT(ARG1,ARG2,ARG3) \
  1426. ({ \
  1427. uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
  1428. __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
  1429. __RES; \
  1430. })
  1431. #define __PKHTB(ARG1,ARG2,ARG3) \
  1432. ({ \
  1433. uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
  1434. if (ARG3 == 0) \
  1435. __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
  1436. else \
  1437. __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
  1438. __RES; \
  1439. })
  1440. #endif
  1441. #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
  1442. ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
  1443. #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
  1444. ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
  1445. __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
  1446. {
  1447. int32_t result;
  1448. __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3));
  1449. return (result);
  1450. }
  1451. #endif /* (__ARM_FEATURE_DSP == 1) */
  1452. /*@} end of group CMSIS_SIMD_intrinsics */
  1453. #endif /* __CMSIS_ARMCLANG_H */