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nu_clk.h

nu_clk.h 111 KB
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  1. /**************************************************************************//**
    2. 

  2.  * @file     CLK.h
    3. 

  3.  * @version  V3.00
    4. 

  4.  * @brief    M460 Series CLK Driver Header File
    5. 

  5.  *
    6. 

  6.  * @copyright SPDX-License-Identifier: Apache-2.0
    7. 

  7.  * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
    8. 

  8.  ******************************************************************************/
    9. 

  9. #ifndef __NU_CLK_H__
    10. 

  10. #define __NU_CLK_H__
    11. 

  11. 

  12. #ifdef __cplusplus
    13. 

  13. extern "C"
    14. 

  14. {
    15. 

  15. #endif
    16. 

  16. 

  17. 

  18. /** @addtogroup Standard_Driver Standard Driver
    19. 

  19.   @{
    20. 

  20. */
    21. 

  21. 

  22. /** @addtogroup CLK_Driver CLK Driver
    23. 

  23.   @{
    24. 

  24. */
    25. 

  25. 

  26. /** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
    27. 

  27.   @{
    28. 

  28. */
    29. 

  29. 

  30. 

  31. #define FREQ_1MHZ          1000000UL    /*!< 1 MHz \hideinitializer */
    32. 

  32. #define FREQ_4MHZ          4000000UL    /*!< 4 MHz \hideinitializer */
    33. 

  33. #define FREQ_8MHZ          8000000UL    /*!< 8 MHz \hideinitializer */
    34. 

  34. #define FREQ_25MHZ         25000000UL   /*!< 25 MHz \hideinitializer */
    35. 

  35. #define FREQ_50MHZ         50000000UL   /*!< 50 MHz \hideinitializer */
    36. 

  36. #define FREQ_75MHZ         75000000UL   /*!< 75 MHz \hideinitializer */
    37. 

  37. #define FREQ_100MHZ        100000000UL  /*!< 100 MHz \hideinitializer */
    38. 

  38. #define FREQ_125MHZ        125000000UL  /*!< 125 MHz \hideinitializer */
    39. 

  39. #define FREQ_150MHZ        150000000UL  /*!< 50 MHz \hideinitializer */
    40. 

  40. #define FREQ_175MHZ        175000000UL  /*!< 175 MHz \hideinitializer */
    41. 

  41. #define FREQ_180MHZ        180000000UL  /*!< 180 MHz \hideinitializer */
    42. 

  42. #define FREQ_192MHZ        192000000UL  /*!< 192 MHz \hideinitializer */
    43. 

  43. #define FREQ_200MHZ        200000000UL  /*!< 200 MHz \hideinitializer */
    44. 

  44. #define FREQ_500MHZ        500000000UL  /*!< 500 MHz \hideinitializer */
    45. 

  45. 

  46. /*---------------------------------------------------------------------------------------------------------*/
    47. 

  47. /*  CLKSEL0 constant definitions.  (Write-protection)                                                      */
    48. 

  48. /*---------------------------------------------------------------------------------------------------------*/
    49. 

  49. #define CLK_CLKSEL0_HCLKSEL_HXT          (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from high speed crystal \hideinitializer */
    50. 

  50. #define CLK_CLKSEL0_HCLKSEL_LXT          (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from low speed crystal \hideinitializer */
    51. 

  51. #define CLK_CLKSEL0_HCLKSEL_PLL          (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from PLL \hideinitializer */
    52. 

  52. #define CLK_CLKSEL0_HCLKSEL_LIRC         (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
    53. 

  53. #define CLK_CLKSEL0_HCLKSEL_HIRC         (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos)         /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
    54. 

  54. 

  55. #define CLK_CLKSEL0_STCLKSEL_HXT         (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from high speed crystal \hideinitializer */
    56. 

  56. #define CLK_CLKSEL0_STCLKSEL_LXT         (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from low speed crystal \hideinitializer */
    57. 

  57. #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2    (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from HXT/2 \hideinitializer */
    58. 

  58. #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
    59. 

  59. #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2   (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos)        /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
    60. 

  60. #define CLK_CLKSEL0_STCLKSEL_HCLK        (0x1UL << SysTick_CTRL_CLKSOURCE_Pos)      /*!< Select SysTick clock source from HCLK \hideinitializer */
    61. 

  61. 

  62. #define CLK_CLKSEL0_USBSEL_HIRC48M       (0x0UL << CLK_CLKSEL0_USBSEL_Pos)          /*!< Select USB clock source from HIRC48M \hideinitializer */
    63. 

  63. #define CLK_CLKSEL0_USBSEL_PLL_DIV2      (0x1UL << CLK_CLKSEL0_USBSEL_Pos)          /*!< Select USB clock source from PLL/2 \hideinitializer */
    64. 

  64. 

  65. #define CLK_CLKSEL0_EADC0SEL_PLLFN_DIV2  (0x0UL << CLK_CLKSEL0_EADC0SEL_Pos)        /*!< Select EADC0 clock source from PLLFN/2 \hideinitializer */
    66. 

  66. #define CLK_CLKSEL0_EADC0SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL0_EADC0SEL_Pos)        /*!< Select EADC0 clock source from PLL/2 \hideinitializer */
    67. 

  67. #define CLK_CLKSEL0_EADC0SEL_HCLK        (0x2UL << CLK_CLKSEL0_EADC0SEL_Pos)        /*!< Select EADC0 clock source from HCLK \hideinitializer */
    68. 

  68. 

  69. #define CLK_CLKSEL0_EADC1SEL_PLLFN_DIV2  (0x0UL << CLK_CLKSEL0_EADC1SEL_Pos)        /*!< Select EADC1 clock source from PLLFN/2 \hideinitializer */
    70. 

  70. #define CLK_CLKSEL0_EADC1SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL0_EADC1SEL_Pos)        /*!< Select EADC1 clock source from PLL/2 \hideinitializer */
    71. 

  71. #define CLK_CLKSEL0_EADC1SEL_HCLK        (0x2UL << CLK_CLKSEL0_EADC1SEL_Pos)        /*!< Select EADC1 clock source from HCLK \hideinitializer */
    72. 

  72. 

  73. #define CLK_CLKSEL0_EADC2SEL_PLLFN_DIV2  (0x0UL << CLK_CLKSEL0_EADC2SEL_Pos)        /*!< Select EADC2 clock source from PLLFN/2 \hideinitializer */
    74. 

  74. #define CLK_CLKSEL0_EADC2SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL0_EADC2SEL_Pos)        /*!< Select EADC2 clock source from PLL/2 \hideinitializer */
    75. 

  75. #define CLK_CLKSEL0_EADC2SEL_HCLK        (0x2UL << CLK_CLKSEL0_EADC2SEL_Pos)        /*!< Select EADC2 clock source from HCLK \hideinitializer */
    76. 

  76. 

  77. #define CLK_CLKSEL0_CCAPSEL_HXT          (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos)         /*!< Select CCAP sensor clock source from HXT \hideinitializer */
    78. 

  78. #define CLK_CLKSEL0_CCAPSEL_PLL_DIV2     (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos)         /*!< Select CCAP sensor clock source from PLL/2 \hideinitializer */
    79. 

  79. #define CLK_CLKSEL0_CCAPSEL_HCLK         (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos)         /*!< Select CCAP sensor clock source from HCLK \hideinitializer */
    80. 

  80. #define CLK_CLKSEL0_CCAPSEL_HIRC         (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos)         /*!< Select CCAP sensor clock source from HIRC \hideinitializer */
    81. 

  81. 

  82. #define CLK_CLKSEL0_SDH0SEL_HXT          (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
    83. 

  83. #define CLK_CLKSEL0_SDH0SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from PLL/2 \hideinitializer */
    84. 

  84. #define CLK_CLKSEL0_SDH0SEL_HCLK         (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from HCLK \hideinitializer */
    85. 

  85. #define CLK_CLKSEL0_SDH0SEL_HIRC         (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos)         /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
    86. 

  86. 

  87. #define CLK_CLKSEL0_SDH1SEL_HXT          (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
    88. 

  88. #define CLK_CLKSEL0_SDH1SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from PLL/2 \hideinitializer */
    89. 

  89. #define CLK_CLKSEL0_SDH1SEL_HCLK         (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from HCLK \hideinitializer */
    90. 

  90. #define CLK_CLKSEL0_SDH1SEL_HIRC         (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos)         /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
    91. 

  91. 

  92. #define CLK_CLKSEL0_CANFD0SEL_HXT        (0x0UL << CLK_CLKSEL0_CANFD0SEL_Pos)       /*!< Select CANFD0 clock source from HXT \hideinitializer */
    93. 

  93. #define CLK_CLKSEL0_CANFD0SEL_PLL_DIV2   (0x1UL << CLK_CLKSEL0_CANFD0SEL_Pos)       /*!< Select CANFD0 clock source from PLL/2 \hideinitializer */
    94. 

  94. #define CLK_CLKSEL0_CANFD0SEL_HCLK       (0x2UL << CLK_CLKSEL0_CANFD0SEL_Pos)       /*!< Select CANFD0 clock source from HCLK \hideinitializer */
    95. 

  95. #define CLK_CLKSEL0_CANFD0SEL_HIRC       (0x3UL << CLK_CLKSEL0_CANFD0SEL_Pos)       /*!< Select CANFD0 clock source from HIRC \hideinitializer */
    96. 

  96. 

  97. #define CLK_CLKSEL0_CANFD1SEL_HXT        (0x0UL << CLK_CLKSEL0_CANFD1SEL_Pos)       /*!< Select CANFD1 clock source from HXT \hideinitializer */
    98. 

  98. #define CLK_CLKSEL0_CANFD1SEL_PLL_DIV2   (0x1UL << CLK_CLKSEL0_CANFD1SEL_Pos)       /*!< Select CANFD1 clock source from PLL/2 \hideinitializer */
    99. 

  99. #define CLK_CLKSEL0_CANFD1SEL_HCLK       (0x2UL << CLK_CLKSEL0_CANFD1SEL_Pos)       /*!< Select CANFD1 clock source from HCLK \hideinitializer */
    100. 

  100. #define CLK_CLKSEL0_CANFD1SEL_HIRC       (0x3UL << CLK_CLKSEL0_CANFD1SEL_Pos)       /*!< Select CANFD1 clock source from HIRC \hideinitializer */
    101. 

  101. 

  102. #define CLK_CLKSEL0_CANFD2SEL_HXT        (0x0UL << CLK_CLKSEL0_CANFD2SEL_Pos)       /*!< Select CANFD2 clock source from HXT \hideinitializer */
    103. 

  103. #define CLK_CLKSEL0_CANFD2SEL_PLL_DIV2   (0x1UL << CLK_CLKSEL0_CANFD2SEL_Pos)       /*!< Select CANFD2 clock source from PLL/2 \hideinitializer */
    104. 

  104. #define CLK_CLKSEL0_CANFD2SEL_HCLK       (0x2UL << CLK_CLKSEL0_CANFD2SEL_Pos)       /*!< Select CANFD2 clock source from HCLK \hideinitializer */
    105. 

  105. #define CLK_CLKSEL0_CANFD2SEL_HIRC       (0x3UL << CLK_CLKSEL0_CANFD2SEL_Pos)       /*!< Select CANFD2 clock source from HIRC \hideinitializer */
    106. 

  106. 

  107. #define CLK_CLKSEL0_CANFD3SEL_HXT        (0x0UL << CLK_CLKSEL0_CANFD3SEL_Pos)       /*!< Select CANFD3 clock source from HXT \hideinitializer */
    108. 

  108. #define CLK_CLKSEL0_CANFD3SEL_PLL_DIV2   (0x1UL << CLK_CLKSEL0_CANFD3SEL_Pos)       /*!< Select CANFD3 clock source from PLL/2 \hideinitializer */
    109. 

  109. #define CLK_CLKSEL0_CANFD3SEL_HCLK       (0x2UL << CLK_CLKSEL0_CANFD3SEL_Pos)       /*!< Select CANFD3 clock source from HCLK \hideinitializer */
    110. 

  110. #define CLK_CLKSEL0_CANFD3SEL_HIRC       (0x3UL << CLK_CLKSEL0_CANFD3SEL_Pos)       /*!< Select CANFD3 clock source from HIRC \hideinitializer */
    111. 

  111. 

  112. 

  113. /*---------------------------------------------------------------------------------------------------------*/
    114. 

  114. /*  CLKSEL1 constant definitions.                                                                          */
    115. 

  115. /*---------------------------------------------------------------------------------------------------------*/
    116. 

  116. #define CLK_CLKSEL1_WDTSEL_LXT           (0x1UL << CLK_CLKSEL1_WDTSEL_Pos)          /*!< Select WDT clock source from low speed crystal \hideinitializer */
    117. 

  117. #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048  (0x2UL << CLK_CLKSEL1_WDTSEL_Pos)          /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
    118. 

  118. #define CLK_CLKSEL1_WDTSEL_LIRC          (0x3UL << CLK_CLKSEL1_WDTSEL_Pos)          /*!< Select WDT clock source from low speed oscillator \hideinitializer */
    119. 

  119. 

  120. #define CLK_CLKSEL1_CLKOSEL_HXT          (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from HXT \hideinitializer */
    121. 

  121. #define CLK_CLKSEL1_CLKOSEL_LXT          (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from LXT \hideinitializer */
    122. 

  122. #define CLK_CLKSEL1_CLKOSEL_HCLK         (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from HCLK \hideinitializer */
    123. 

  123. #define CLK_CLKSEL1_CLKOSEL_HIRC         (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from HIRC \hideinitializer */
    124. 

  124. #define CLK_CLKSEL1_CLKOSEL_LIRC         (0x4UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from LIRC \hideinitializer */
    125. 

  125. #define CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from PLLFN/2 \hideinitializer */
    126. 

  126. #define CLK_CLKSEL1_CLKOSEL_PLL_DIV2     (0x6UL << CLK_CLKSEL1_CLKOSEL_Pos)         /*!< Select CLKO clock source from PLL/2 \hideinitializer */
    127. 

  127. 

  128. #define CLK_CLKSEL1_TMR0SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
    129. 

  129. #define CLK_CLKSEL1_TMR0SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
    130. 

  130. #define CLK_CLKSEL1_TMR0SEL_PCLK0        (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
    131. 

  131. #define CLK_CLKSEL1_TMR0SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from external trigger \hideinitializer */
    132. 

  132. #define CLK_CLKSEL1_TMR0SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
    133. 

  133. #define CLK_CLKSEL1_TMR0SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos)         /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
    134. 

  134. 

  135. #define CLK_CLKSEL1_TMR1SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
    136. 

  136. #define CLK_CLKSEL1_TMR1SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
    137. 

  137. #define CLK_CLKSEL1_TMR1SEL_PCLK0        (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
    138. 

  138. #define CLK_CLKSEL1_TMR1SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from external trigger \hideinitializer */
    139. 

  139. #define CLK_CLKSEL1_TMR1SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
    140. 

  140. #define CLK_CLKSEL1_TMR1SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos)         /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
    141. 

  141. 

  142. #define CLK_CLKSEL1_TMR2SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
    143. 

  143. #define CLK_CLKSEL1_TMR2SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
    144. 

  144. #define CLK_CLKSEL1_TMR2SEL_PCLK1        (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
    145. 

  145. #define CLK_CLKSEL1_TMR2SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from external trigger \hideinitializer */
    146. 

  146. #define CLK_CLKSEL1_TMR2SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
    147. 

  147. #define CLK_CLKSEL1_TMR2SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos)         /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
    148. 

  148. 

  149. #define CLK_CLKSEL1_TMR3SEL_HXT          (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
    150. 

  150. #define CLK_CLKSEL1_TMR3SEL_LXT          (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
    151. 

  151. #define CLK_CLKSEL1_TMR3SEL_PCLK1        (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
    152. 

  152. #define CLK_CLKSEL1_TMR3SEL_EXT          (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from external trigger \hideinitializer */
    153. 

  153. #define CLK_CLKSEL1_TMR3SEL_LIRC         (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
    154. 

  154. #define CLK_CLKSEL1_TMR3SEL_HIRC         (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos)         /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
    155. 

  155. 

  156. #define CLK_CLKSEL1_UART0SEL_HXT         (0x0UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from high speed crystal \hideinitializer */
    157. 

  157. #define CLK_CLKSEL1_UART0SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from PLL/2 \hideinitializer */
    158. 

  158. #define CLK_CLKSEL1_UART0SEL_LXT         (0x2UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from low speed crystal \hideinitializer */
    159. 

  159. #define CLK_CLKSEL1_UART0SEL_HIRC        (0x3UL << CLK_CLKSEL1_UART0SEL_Pos)        /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
    160. 

  160. 

  161. #define CLK_CLKSEL1_UART1SEL_HXT         (0x0UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from high speed crystal \hideinitializer */
    162. 

  162. #define CLK_CLKSEL1_UART1SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from PLL/2 \hideinitializer */
    163. 

  163. #define CLK_CLKSEL1_UART1SEL_LXT         (0x2UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from low speed crystal \hideinitializer */
    164. 

  164. #define CLK_CLKSEL1_UART1SEL_HIRC        (0x3UL << CLK_CLKSEL1_UART1SEL_Pos)        /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
    165. 

  165. 

  166. #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos)         /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
    167. 

  167. #define CLK_CLKSEL1_WWDTSEL_LIRC         (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos)         /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
    168. 

  168. 

  169. 

  170. /*---------------------------------------------------------------------------------------------------------*/
    171. 

  171. /*  CLKSEL2 constant definitions.                                                                          */
    172. 

  172. /*---------------------------------------------------------------------------------------------------------*/
    173. 

  173. #define CLK_CLKSEL2_EPWM0SEL_HCLK        (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos)        /*!< Select EPWM0 clock source from HCLK \hideinitializer */
    174. 

  174. #define CLK_CLKSEL2_EPWM0SEL_PCLK0       (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos)        /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
    175. 

  175. 

  176. #define CLK_CLKSEL2_EPWM1SEL_HCLK        (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos)        /*!< Select EPWM1 clock source from HCLK \hideinitializer */
    177. 

  177. #define CLK_CLKSEL2_EPWM1SEL_PCLK1       (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos)        /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
    178. 

  178. 

  179. #define CLK_CLKSEL2_QSPI0SEL_HXT         (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos)        /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */
    180. 

  180. #define CLK_CLKSEL2_QSPI0SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos)        /*!< Select QSPI0 clock source from PLL/2 \hideinitializer */
    181. 

  181. #define CLK_CLKSEL2_QSPI0SEL_PCLK0       (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos)        /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */
    182. 

  182. #define CLK_CLKSEL2_QSPI0SEL_HIRC        (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos)        /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */
    183. 

  183. 

  184. #define CLK_CLKSEL2_SPI0SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
    185. 

  185. #define CLK_CLKSEL2_SPI0SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from PLL/2 \hideinitializer */
    186. 

  186. #define CLK_CLKSEL2_SPI0SEL_PCLK1        (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from PCLK1 \hideinitializer */
    187. 

  187. #define CLK_CLKSEL2_SPI0SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
    188. 

  188. #define CLK_CLKSEL2_SPI0SEL_HIRC48M      (0x4UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from HIRC48M \hideinitializer */
    189. 

  189. #define CLK_CLKSEL2_SPI0SEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL2_SPI0SEL_Pos)         /*!< Select SPI0 clock source from PLLFN/2 \hideinitializer */
    190. 

  190. 

  191. #define CLK_CLKSEL2_BPWM0SEL_HCLK        (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos)        /*!< Select BPWM0 clock source from HCLK \hideinitializer */
    192. 

  192. #define CLK_CLKSEL2_BPWM0SEL_PCLK0       (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos)        /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
    193. 

  193. 

  194. #define CLK_CLKSEL2_BPWM1SEL_HCLK        (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos)        /*!< Select BPWM1 clock source from HCLK \hideinitializer */
    195. 

  195. #define CLK_CLKSEL2_BPWM1SEL_PCLK1       (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos)        /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
    196. 

  196. 

  197. #define CLK_CLKSEL2_QSPI1SEL_HXT         (0x0UL << CLK_CLKSEL2_QSPI1SEL_Pos)        /*!< Select QSPI1 clock source from high speed crystal \hideinitializer */
    198. 

  198. #define CLK_CLKSEL2_QSPI1SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL2_QSPI1SEL_Pos)        /*!< Select QSPI1 clock source from PLL/2 \hideinitializer */
    199. 

  199. #define CLK_CLKSEL2_QSPI1SEL_PCLK1       (0x2UL << CLK_CLKSEL2_QSPI1SEL_Pos)        /*!< Select QSPI1 clock source from PCLK1 \hideinitializer */
    200. 

  200. #define CLK_CLKSEL2_QSPI1SEL_HIRC        (0x3UL << CLK_CLKSEL2_QSPI1SEL_Pos)        /*!< Select QSPI1 clock source from high speed oscillator \hideinitializer */
    201. 

  201. 

  202. #define CLK_CLKSEL2_SPI1SEL_HXT          (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
    203. 

  203. #define CLK_CLKSEL2_SPI1SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from PLL/2 \hideinitializer */
    204. 

  204. #define CLK_CLKSEL2_SPI1SEL_PCLK0        (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from PCLK0 \hideinitializer */
    205. 

  205. #define CLK_CLKSEL2_SPI1SEL_HIRC         (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
    206. 

  206. #define CLK_CLKSEL2_SPI1SEL_HIRC48M      (0x4UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from HIRC48M \hideinitializer */
    207. 

  207. #define CLK_CLKSEL2_SPI1SEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL2_SPI1SEL_Pos)         /*!< Select SPI1 clock source from PLLFN/2 \hideinitializer */
    208. 

  208. 

  209. #define CLK_CLKSEL2_I2S1SEL_HXT          (0x0UL << CLK_CLKSEL2_I2S1SEL_Pos)         /*!< Select I2S1 clock source from HXT \hideinitializer */
    210. 

  210. #define CLK_CLKSEL2_I2S1SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL2_I2S1SEL_Pos)         /*!< Select I2S1 clock source from PLL/2 \hideinitializer */
    211. 

  211. #define CLK_CLKSEL2_I2S1SEL_PCLK1        (0x2UL << CLK_CLKSEL2_I2S1SEL_Pos)         /*!< Select I2S1 clock source from PCLK1 \hideinitializer */
    212. 

  212. #define CLK_CLKSEL2_I2S1SEL_HIRC         (0x3UL << CLK_CLKSEL2_I2S1SEL_Pos)         /*!< Select I2S1 clock source from HIRC \hideinitializer */
    213. 

  213. #define CLK_CLKSEL2_I2S1SEL_HIRC48M      (0x4UL << CLK_CLKSEL2_I2S1SEL_Pos)         /*!< Select I2S1 clock source from HIRC48M \hideinitializer */
    214. 

  214. #define CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL2_I2S1SEL_Pos)         /*!< Select I2S1 clock source from PLLFN/2 \hideinitializer */
    215. 

  215. 

  216. #define CLK_CLKSEL2_UART8SEL_HXT         (0x0UL << CLK_CLKSEL2_UART8SEL_Pos)        /*!< Select UART8 clock source from HXT \hideinitializer */
    217. 

  217. #define CLK_CLKSEL2_UART8SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL2_UART8SEL_Pos)        /*!< Select UART8 clock source from PLL/2 \hideinitializer */
    218. 

  218. #define CLK_CLKSEL2_UART8SEL_LXT         (0x2UL << CLK_CLKSEL2_UART8SEL_Pos)        /*!< Select UART8 clock source from LXT \hideinitializer */
    219. 

  219. #define CLK_CLKSEL2_UART8SEL_HIRC        (0x3UL << CLK_CLKSEL2_UART8SEL_Pos)        /*!< Select UART8 clock source from HIRC \hideinitializer */
    220. 

  220. 

  221. #define CLK_CLKSEL2_UART9SEL_HXT         (0x0UL << CLK_CLKSEL2_UART9SEL_Pos)        /*!< Select UART9 clock source from HXT \hideinitializer */
    222. 

  222. #define CLK_CLKSEL2_UART9SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL2_UART9SEL_Pos)        /*!< Select UART9 clock source from PLL/2 \hideinitializer */
    223. 

  223. #define CLK_CLKSEL2_UART9SEL_LXT         (0x2UL << CLK_CLKSEL2_UART9SEL_Pos)        /*!< Select UART9 clock source from LXT \hideinitializer */
    224. 

  224. #define CLK_CLKSEL2_UART9SEL_HIRC        (0x3UL << CLK_CLKSEL2_UART9SEL_Pos)        /*!< Select UART9 clock source from HIRC \hideinitializer */
    225. 

  225. 

  226. #define CLK_CLKSEL2_TRNGSEL_LXT          (0x0UL << CLK_CLKSEL2_TRNGSEL_Pos)         /*!< Select TRNG clock source from LXT \hideinitializer */
    227. 

  227. #define CLK_CLKSEL2_TRNGSEL_LIRC         (0x1UL << CLK_CLKSEL2_TRNGSEL_Pos)         /*!< Select TRNG clock source from LIRC \hideinitializer */
    228. 

  228. 

  229. #define CLK_CLKSEL2_PSIOSEL_HXT          (0x0UL << CLK_CLKSEL2_PSIOSEL_Pos)         /*!< Select PSIO clock source from LXT \hideinitializer */
    230. 

  230. #define CLK_CLKSEL2_PSIOSEL_LXT          (0x1UL << CLK_CLKSEL2_PSIOSEL_Pos)         /*!< Select PSIO clock source from LIRC \hideinitializer */
    231. 

  231. #define CLK_CLKSEL2_PSIOSEL_PCLK1        (0x2UL << CLK_CLKSEL2_PSIOSEL_Pos)         /*!< Select PSIO clock source from PCLK1 \hideinitializer */
    232. 

  232. #define CLK_CLKSEL2_PSIOSEL_PLL_DIV2     (0x3UL << CLK_CLKSEL2_PSIOSEL_Pos)         /*!< Select PSIO clock source from PLL/2 \hideinitializer */
    233. 

  233. #define CLK_CLKSEL2_PSIOSEL_LIRC         (0x4UL << CLK_CLKSEL2_PSIOSEL_Pos)         /*!< Select PSIO clock source from LIRC \hideinitializer */
    234. 

  234. #define CLK_CLKSEL2_PSIOSEL_HIRC         (0x5UL << CLK_CLKSEL2_PSIOSEL_Pos)         /*!< Select PSIO clock source from HIRC \hideinitializer */
    235. 

  235. 

  236. /*---------------------------------------------------------------------------------------------------------*/
    237. 

  237. /*  CLKSEL3 constant definitions.                                                                          */
    238. 

  238. /*---------------------------------------------------------------------------------------------------------*/
    239. 

  239. #define CLK_CLKSEL3_SC0SEL_HXT           (0x0UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from high speed crystal \hideinitializer */
    240. 

  240. #define CLK_CLKSEL3_SC0SEL_PLL_DIV2      (0x1UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from PLL/2 \hideinitializer */
    241. 

  241. #define CLK_CLKSEL3_SC0SEL_PCLK0         (0x2UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from PCLK0 \hideinitializer */
    242. 

  242. #define CLK_CLKSEL3_SC0SEL_HIRC          (0x3UL << CLK_CLKSEL3_SC0SEL_Pos)          /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
    243. 

  243. 

  244. #define CLK_CLKSEL3_SC1SEL_HXT           (0x0UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from high speed crystal \hideinitializer */
    245. 

  245. #define CLK_CLKSEL3_SC1SEL_PLL_DIV2      (0x1UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from PLL/2 \hideinitializer */
    246. 

  246. #define CLK_CLKSEL3_SC1SEL_PCLK1         (0x2UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from PCLK1 \hideinitializer */
    247. 

  247. #define CLK_CLKSEL3_SC1SEL_HIRC          (0x3UL << CLK_CLKSEL3_SC1SEL_Pos)          /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
    248. 

  248. 

  249. #define CLK_CLKSEL3_SC2SEL_HXT           (0x0UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from high speed crystal \hideinitializer */
    250. 

  250. #define CLK_CLKSEL3_SC2SEL_PLL_DIV2      (0x1UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from PLL/2 \hideinitializer */
    251. 

  251. #define CLK_CLKSEL3_SC2SEL_PCLK0         (0x2UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from PCLK0 \hideinitializer */
    252. 

  252. #define CLK_CLKSEL3_SC2SEL_HIRC          (0x3UL << CLK_CLKSEL3_SC2SEL_Pos)          /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
    253. 

  253. 

  254. #define CLK_CLKSEL3_KPISEL_HXT           (0x0UL << CLK_CLKSEL3_KPISEL_Pos)          /*!< Select KPI clock source from high speed crystal \hideinitializer */
    255. 

  255. #define CLK_CLKSEL3_KPISEL_LIRC          (0x1UL << CLK_CLKSEL3_KPISEL_Pos)          /*!< Select KPI clock source from low speed oscillator \hideinitializer */
    256. 

  256. #define CLK_CLKSEL3_KPISEL_HIRC          (0x2UL << CLK_CLKSEL3_KPISEL_Pos)          /*!< Select KPI clock source from high speed oscillator \hideinitializer */
    257. 

  257. 

  258. #define CLK_CLKSEL3_SPI2SEL_HXT          (0x0UL << CLK_CLKSEL3_SPI2SEL_Pos)         /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
    259. 

  259. #define CLK_CLKSEL3_SPI2SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL3_SPI2SEL_Pos)         /*!< Select SPI2 clock source from PLL/2 \hideinitializer */
    260. 

  260. #define CLK_CLKSEL3_SPI2SEL_PCLK1        (0x2UL << CLK_CLKSEL3_SPI2SEL_Pos)         /*!< Select SPI2 clock source from PCLK1 \hideinitializer */
    261. 

  261. #define CLK_CLKSEL3_SPI2SEL_HIRC         (0x3UL << CLK_CLKSEL3_SPI2SEL_Pos)         /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
    262. 

  262. #define CLK_CLKSEL3_SPI2SEL_HIRC48M      (0x4UL << CLK_CLKSEL3_SPI2SEL_Pos)         /*!< Select SPI2 clock source from HIRC48M \hideinitializer */
    263. 

  263. #define CLK_CLKSEL3_SPI2SEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL3_SPI2SEL_Pos)         /*!< Select SPI2 clock source from PLLFN/2 \hideinitializer */
    264. 

  264. 

  265. #define CLK_CLKSEL3_SPI3SEL_HXT          (0x0UL << CLK_CLKSEL3_SPI3SEL_Pos)         /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
    266. 

  266. #define CLK_CLKSEL3_SPI3SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL3_SPI3SEL_Pos)         /*!< Select SPI3 clock source from PLL/2 \hideinitializer */
    267. 

  267. #define CLK_CLKSEL3_SPI3SEL_PCLK0        (0x2UL << CLK_CLKSEL3_SPI3SEL_Pos)         /*!< Select SPI3 clock source from PCLK0 \hideinitializer */
    268. 

  268. #define CLK_CLKSEL3_SPI3SEL_HIRC         (0x3UL << CLK_CLKSEL3_SPI3SEL_Pos)         /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
    269. 

  269. #define CLK_CLKSEL3_SPI3SEL_HIRC48M      (0x4UL << CLK_CLKSEL3_SPI3SEL_Pos)         /*!< Select SPI3 clock source from HIRC48M \hideinitializer */
    270. 

  270. #define CLK_CLKSEL3_SPI3SEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL3_SPI3SEL_Pos)         /*!< Select SPI3 clock source from PLLFN/2 \hideinitializer */
    271. 

  271. 

  272. #define CLK_CLKSEL3_I2S0SEL_HXT          (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
    273. 

  273. #define CLK_CLKSEL3_I2S0SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from PLL/2 \hideinitializer */
    274. 

  274. #define CLK_CLKSEL3_I2S0SEL_PCLK0        (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
    275. 

  275. #define CLK_CLKSEL3_I2S0SEL_HIRC         (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
    276. 

  276. #define CLK_CLKSEL3_I2S0SEL_HIRC48M      (0x4UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from HIRC48M \hideinitializer */
    277. 

  277. #define CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2   (0x5UL << CLK_CLKSEL3_I2S0SEL_Pos)         /*!< Select I2S0 clock source from PLLFN/2 \hideinitializer */
    278. 

  278. 

  279. #define CLK_CLKSEL3_UART6SEL_HXT         (0x0UL << CLK_CLKSEL3_UART6SEL_Pos)        /*!< Select UART6 clock source from HXT \hideinitializer */
    280. 

  280. #define CLK_CLKSEL3_UART6SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL3_UART6SEL_Pos)        /*!< Select UART6 clock source from PLL/2 \hideinitializer */
    281. 

  281. #define CLK_CLKSEL3_UART6SEL_LXT         (0x2UL << CLK_CLKSEL3_UART6SEL_Pos)        /*!< Select UART6 clock source from LXT \hideinitializer */
    282. 

  282. #define CLK_CLKSEL3_UART6SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART6SEL_Pos)        /*!< Select UART6 clock source from HIRC \hideinitializer */
    283. 

  283. 

  284. #define CLK_CLKSEL3_UART7SEL_HXT         (0x0UL << CLK_CLKSEL3_UART7SEL_Pos)        /*!< Select UART7 clock source from HXT \hideinitializer */
    285. 

  285. #define CLK_CLKSEL3_UART7SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL3_UART7SEL_Pos)        /*!< Select UART7 clock source from PLL/2 \hideinitializer */
    286. 

  286. #define CLK_CLKSEL3_UART7SEL_LXT         (0x2UL << CLK_CLKSEL3_UART7SEL_Pos)        /*!< Select UART7 clock source from LXT \hideinitializer */
    287. 

  287. #define CLK_CLKSEL3_UART7SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART7SEL_Pos)        /*!< Select UART7 clock source from HIRC \hideinitializer */
    288. 

  288. 

  289. #define CLK_CLKSEL3_UART2SEL_HXT         (0x0UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from high speed crystal \hideinitializer */
    290. 

  290. #define CLK_CLKSEL3_UART2SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from PLL/2 \hideinitializer */
    291. 

  291. #define CLK_CLKSEL3_UART2SEL_LXT         (0x2UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from low speed crystal \hideinitializer */
    292. 

  292. #define CLK_CLKSEL3_UART2SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART2SEL_Pos)        /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
    293. 

  293. 

  294. #define CLK_CLKSEL3_UART3SEL_HXT         (0x0UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from high speed crystal \hideinitializer */
    295. 

  295. #define CLK_CLKSEL3_UART3SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from PLL/2 \hideinitializer */
    296. 

  296. #define CLK_CLKSEL3_UART3SEL_LXT         (0x2UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from low speed crystal \hideinitializer */
    297. 

  297. #define CLK_CLKSEL3_UART3SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART3SEL_Pos)        /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
    298. 

  298. 

  299. #define CLK_CLKSEL3_UART4SEL_HXT         (0x0UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from high speed crystal \hideinitializer */
    300. 

  300. #define CLK_CLKSEL3_UART4SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from PLL/2 \hideinitializer */
    301. 

  301. #define CLK_CLKSEL3_UART4SEL_LXT         (0x2UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from low speed crystal \hideinitializer */
    302. 

  302. #define CLK_CLKSEL3_UART4SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART4SEL_Pos)        /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
    303. 

  303. 

  304. #define CLK_CLKSEL3_UART5SEL_HXT         (0x0UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from high speed crystal \hideinitializer */
    305. 

  305. #define CLK_CLKSEL3_UART5SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from PLL/2 \hideinitializer */
    306. 

  306. #define CLK_CLKSEL3_UART5SEL_LXT         (0x2UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from low speed crystal \hideinitializer */
    307. 

  307. #define CLK_CLKSEL3_UART5SEL_HIRC        (0x3UL << CLK_CLKSEL3_UART5SEL_Pos)        /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
    308. 

  308. 

  309. /*---------------------------------------------------------------------------------------------------------*/
    310. 

  310. /*  CLKSEL4 constant definitions.                                                                          */
    311. 

  311. /*---------------------------------------------------------------------------------------------------------*/
    312. 

  312. #define CLK_CLKSEL4_SPI4SEL_HXT          (0x0UL << CLK_CLKSEL4_SPI4SEL_Pos)         /*!< Select SPI4 clock source from high speed crystal \hideinitializer */
    313. 

  313. #define CLK_CLKSEL4_SPI4SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL4_SPI4SEL_Pos)         /*!< Select SPI4 clock source from PLL/2 \hideinitializer */
    314. 

  314. #define CLK_CLKSEL4_SPI4SEL_PCLK1        (0x2UL << CLK_CLKSEL4_SPI4SEL_Pos)         /*!< Select SPI4 clock source from PCLK1 \hideinitializer */
    315. 

  315. #define CLK_CLKSEL4_SPI4SEL_HIRC         (0x3UL << CLK_CLKSEL4_SPI4SEL_Pos)         /*!< Select SPI4 clock source from high speed oscillator \hideinitializer */
    316. 

  316. 

  317. #define CLK_CLKSEL4_SPI5SEL_HXT          (0x0UL << CLK_CLKSEL4_SPI5SEL_Pos)         /*!< Select SPI5 clock source from high speed crystal \hideinitializer */
    318. 

  318. #define CLK_CLKSEL4_SPI5SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL4_SPI5SEL_Pos)         /*!< Select SPI5 clock source from PLL/2 \hideinitializer */
    319. 

  319. #define CLK_CLKSEL4_SPI5SEL_PCLK0        (0x2UL << CLK_CLKSEL4_SPI5SEL_Pos)         /*!< Select SPI5 clock source from PCLK0 \hideinitializer */
    320. 

  320. #define CLK_CLKSEL4_SPI5SEL_HIRC         (0x3UL << CLK_CLKSEL4_SPI5SEL_Pos)         /*!< Select SPI5 clock source from high speed oscillator \hideinitializer */
    321. 

  321. 

  322. #define CLK_CLKSEL4_SPI6SEL_HXT          (0x0UL << CLK_CLKSEL4_SPI6SEL_Pos)         /*!< Select SPI6 clock source from high speed crystal \hideinitializer */
    323. 

  323. #define CLK_CLKSEL4_SPI6SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL4_SPI6SEL_Pos)         /*!< Select SPI6 clock source from PLL/2 \hideinitializer */
    324. 

  324. #define CLK_CLKSEL4_SPI6SEL_PCLK1        (0x2UL << CLK_CLKSEL4_SPI6SEL_Pos)         /*!< Select SPI6 clock source from PCLK1 \hideinitializer */
    325. 

  325. #define CLK_CLKSEL4_SPI6SEL_HIRC         (0x3UL << CLK_CLKSEL4_SPI6SEL_Pos)         /*!< Select SPI6 clock source from high speed oscillator \hideinitializer */
    326. 

  326. 

  327. #define CLK_CLKSEL4_SPI7SEL_HXT          (0x0UL << CLK_CLKSEL4_SPI7SEL_Pos)         /*!< Select SPI7 clock source from high speed crystal \hideinitializer */
    328. 

  328. #define CLK_CLKSEL4_SPI7SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL4_SPI7SEL_Pos)         /*!< Select SPI7 clock source from PLL/2 \hideinitializer */
    329. 

  329. #define CLK_CLKSEL4_SPI7SEL_PCLK0        (0x2UL << CLK_CLKSEL4_SPI7SEL_Pos)         /*!< Select SPI7 clock source from PCLK0 \hideinitializer */
    330. 

  330. #define CLK_CLKSEL4_SPI7SEL_HIRC         (0x3UL << CLK_CLKSEL4_SPI7SEL_Pos)         /*!< Select SPI7 clock source from high speed oscillator \hideinitializer */
    331. 

  331. 

  332. #define CLK_CLKSEL4_SPI8SEL_HXT          (0x0UL << CLK_CLKSEL4_SPI8SEL_Pos)         /*!< Select SPI8 clock source from high speed crystal \hideinitializer */
    333. 

  333. #define CLK_CLKSEL4_SPI8SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL4_SPI8SEL_Pos)         /*!< Select SPI8 clock source from PLL/2 \hideinitializer */
    334. 

  334. #define CLK_CLKSEL4_SPI8SEL_PCLK1        (0x2UL << CLK_CLKSEL4_SPI8SEL_Pos)         /*!< Select SPI8 clock source from PCLK1 \hideinitializer */
    335. 

  335. #define CLK_CLKSEL4_SPI8SEL_HIRC         (0x3UL << CLK_CLKSEL4_SPI8SEL_Pos)         /*!< Select SPI8 clock source from high speed oscillator \hideinitializer */
    336. 

  336. 

  337. #define CLK_CLKSEL4_SPI9SEL_HXT          (0x0UL << CLK_CLKSEL4_SPI9SEL_Pos)         /*!< Select SPI9 clock source from high speed crystal \hideinitializer */
    338. 

  338. #define CLK_CLKSEL4_SPI9SEL_PLL_DIV2     (0x1UL << CLK_CLKSEL4_SPI9SEL_Pos)         /*!< Select SPI9 clock source from PLL/2 \hideinitializer */
    339. 

  339. #define CLK_CLKSEL4_SPI9SEL_PCLK0        (0x2UL << CLK_CLKSEL4_SPI9SEL_Pos)         /*!< Select SPI9 clock source from PCLK0 \hideinitializer */
    340. 

  340. #define CLK_CLKSEL4_SPI9SEL_HIRC         (0x3UL << CLK_CLKSEL4_SPI9SEL_Pos)         /*!< Select SPI9 clock source from high speed oscillator \hideinitializer */
    341. 

  341. 

  342. #define CLK_CLKSEL4_SPI10SEL_HXT         (0x0UL << CLK_CLKSEL4_SPI10SEL_Pos)        /*!< Select SPI10 clock source from high speed crystal \hideinitializer */
    343. 

  343. #define CLK_CLKSEL4_SPI10SEL_PLL_DIV2    (0x1UL << CLK_CLKSEL4_SPI10SEL_Pos)        /*!< Select SPI10 clock source from PLL/2 \hideinitializer */
    344. 

  344. #define CLK_CLKSEL4_SPI10SEL_PCLK1       (0x2UL << CLK_CLKSEL4_SPI10SEL_Pos)        /*!< Select SPI10 clock source from PCLK1 \hideinitializer */
    345. 

  345. #define CLK_CLKSEL4_SPI10SEL_HIRC        (0x3UL << CLK_CLKSEL4_SPI10SEL_Pos)        /*!< Select SPI10 clock source from high speed oscillator \hideinitializer */
    346. 

  346. 

  347. /*---------------------------------------------------------------------------------------------------------*/
    348. 

  348. /*  RTC clock source constant definitions.                                                                 */
    349. 

  349. /*---------------------------------------------------------------------------------------------------------*/
    350. 

  350. #define RTC_LXTCTL_RTCCKSEL_LXT          (0x0UL<<RTC_LXTCTL_RTCCKSEL_Pos)           /*!< Setting RTC clock source as LXT \hideinitializer */
    351. 

  351. #define RTC_LXTCTL_RTCCKSEL_LIRC         (0x1UL<<RTC_LXTCTL_RTCCKSEL_Pos)           /*!< Setting RTC clock source as LIRC \hideinitializer */
    352. 

  352. 

  353. /*---------------------------------------------------------------------------------------------------------*/
    354. 

  354. /*  CLKDIV0 constant definitions.                                                                          */
    355. 

  355. /*---------------------------------------------------------------------------------------------------------*/
    356. 

  356. #define CLK_CLKDIV0_HCLK(x)              (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos)   /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
    357. 

  357. #define CLK_CLKDIV0_USB(x)               (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos)    /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
    358. 

  358. #define CLK_CLKDIV0_SDH0(x)              (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos)   /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
    359. 

  359. #define CLK_CLKDIV0_UART0(x)             (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos)  /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
    360. 

  360. #define CLK_CLKDIV0_UART1(x)             (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos)  /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
    361. 

  361. #define CLK_CLKDIV0_EADC0(x)             (((x) - 1UL) << CLK_CLKDIV0_EADC0DIV_Pos)  /*!< CLKDIV0 Setting for EADC0 clock divider. It could be 1~256 \hideinitializer */
    362. 

  362. 

  363. /*---------------------------------------------------------------------------------------------------------*/
    364. 

  364. /*  CLKDIV1 constant definitions.                                                                          */
    365. 

  365. /*---------------------------------------------------------------------------------------------------------*/
    366. 

  366. #define CLK_CLKDIV1_SC0(x)               (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos)    /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
    367. 

  367. #define CLK_CLKDIV1_SC1(x)               (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos)    /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
    368. 

  368. #define CLK_CLKDIV1_SC2(x)               (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos)    /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
    369. 

  369. #define CLK_CLKDIV1_PSIO(x)              (((x) - 1UL) << CLK_CLKDIV1_PSIODIV_Pos)   /*!< CLKDIV1 Setting for PSIO clock divider. It could be 1~256 \hideinitializer */
    370. 

  370. 

  371. /*---------------------------------------------------------------------------------------------------------*/
    372. 

  372. /*  CLKDIV2 constant definitions.                                                                          */
    373. 

  373. /*---------------------------------------------------------------------------------------------------------*/
    374. 

  374. #define CLK_CLKDIV2_I2S0(x)              (((x) - 1UL) << CLK_CLKDIV2_I2S0DIV_Pos)   /*!< CLKDIV2 Setting for I2S0 clock divider. It could be 1~16 */
    375. 

  375. #define CLK_CLKDIV2_I2S1(x)              (((x) - 1UL) << CLK_CLKDIV2_I2S1DIV_Pos)   /*!< CLKDIV2 Setting for I2S1 clock divider. It could be 1~16 */
    376. 

  376. #define CLK_CLKDIV2_KPI(x)               (((x) - 1UL) << CLK_CLKDIV2_KPIDIV_Pos)    /*!< CLKDIV2 Setting for KPI clock divider. It could be 1~256 */
    377. 

  377. #define CLK_CLKDIV2_EADC1(x)             (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos)  /*!< CLKDIV2 Setting for EADC1 clock divider. It could be 1~256 */
    378. 

  378. 

  379. /*---------------------------------------------------------------------------------------------------------*/
    380. 

  380. /*  CLKDIV3 constant definitions.                                                                          */
    381. 

  381. /*---------------------------------------------------------------------------------------------------------*/
    382. 

  382. #define CLK_CLKDIV3_VSENSE(x)            (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV3 Setting for VSENSE clock divider. It could be 1~256 \hideinitializer */
    383. 

  383. #define CLK_CLKDIV3_EMAC0(x)             (((x) - 1UL) << CLK_CLKDIV3_EMAC0DIV_Pos)  /*!< CLKDIV3 Setting for EMAC0 clock divider. It could be 1~256 \hideinitializer */
    384. 

  384. #define CLK_CLKDIV3_SDH1(x)              (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos)   /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
    385. 

  385. 

  386. /*---------------------------------------------------------------------------------------------------------*/
    387. 

  387. /*  CLKDIV4 constant definitions.                                                                          */
    388. 

  388. /*---------------------------------------------------------------------------------------------------------*/
    389. 

  389. #define CLK_CLKDIV4_UART2(x)             (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos)  /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
    390. 

  390. #define CLK_CLKDIV4_UART3(x)             (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos)  /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
    391. 

  391. #define CLK_CLKDIV4_UART4(x)             (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos)  /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
    392. 

  392. #define CLK_CLKDIV4_UART5(x)             (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos)  /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
    393. 

  393. #define CLK_CLKDIV4_UART6(x)             (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos)  /*!< CLKDIV4 Setting for UART6 clock divider. It could be 1~16 \hideinitializer */
    394. 

  394. #define CLK_CLKDIV4_UART7(x)             (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos)  /*!< CLKDIV4 Setting for UART7 clock divider. It could be 1~16 \hideinitializer */
    395. 

  395. 

  396. /*---------------------------------------------------------------------------------------------------------*/
    397. 

  397. /*  CLKDIV5 constant definitions.                                                                          */
    398. 

  398. /*---------------------------------------------------------------------------------------------------------*/
    399. 

  399. #define CLK_CLKDIV5_CANFD0(x)            (((x) - 1UL) << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLKDIV5 Setting for CANFD0 clock divider. It could be 1~16 \hideinitializer */
    400. 

  400. #define CLK_CLKDIV5_CANFD1(x)            (((x) - 1UL) << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLKDIV5 Setting for CANFD1 clock divider. It could be 1~16 \hideinitializer */
    401. 

  401. #define CLK_CLKDIV5_CANFD2(x)            (((x) - 1UL) << CLK_CLKDIV5_CANFD2DIV_Pos) /*!< CLKDIV5 Setting for CANFD2 clock divider. It could be 1~16 \hideinitializer */
    402. 

  402. #define CLK_CLKDIV5_CANFD3(x)            (((x) - 1UL) << CLK_CLKDIV5_CANFD3DIV_Pos) /*!< CLKDIV5 Setting for CANFD3 clock divider. It could be 1~16 \hideinitializer */
    403. 

  403. #define CLK_CLKDIV5_UART8(x)             (((x) - 1UL) << CLK_CLKDIV5_UART8DIV_Pos)  /*!< CLKDIV5 Setting for UART8 clock divider. It could be 1~16 \hideinitializer */
    404. 

  404. #define CLK_CLKDIV5_UART9(x)             (((x) - 1UL) << CLK_CLKDIV5_UART9DIV_Pos)  /*!< CLKDIV5 Setting for UART9 clock divider. It could be 1~16 \hideinitializer */
    405. 

  405. #define CLK_CLKDIV5_EADC2(x)             (((x) - 1UL) << CLK_CLKDIV5_EADC2DIV_Pos)  /*!< CLKDIV5 Setting for EADC2 clock divider. It could be 1~256 \hideinitializer */
    406. 

  406. 

  407. /*---------------------------------------------------------------------------------------------------------*/
    408. 

  408. /*  PCLKDIV constant definitions.                                                                          */
    409. 

  409. /*---------------------------------------------------------------------------------------------------------*/
    410. 

  410. #define CLK_PCLKDIV_PCLK0DIV1            (0x0UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
    411. 

  411. #define CLK_PCLKDIV_PCLK0DIV2            (0x1UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
    412. 

  412. #define CLK_PCLKDIV_PCLK0DIV4            (0x2UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
    413. 

  413. #define CLK_PCLKDIV_PCLK0DIV8            (0x3UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
    414. 

  414. #define CLK_PCLKDIV_PCLK0DIV16           (0x4UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
    415. 

  415. #define CLK_PCLKDIV_PCLK1DIV1            (0x0UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
    416. 

  416. #define CLK_PCLKDIV_PCLK1DIV2            (0x1UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
    417. 

  417. #define CLK_PCLKDIV_PCLK1DIV4            (0x2UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
    418. 

  418. #define CLK_PCLKDIV_PCLK1DIV8            (0x3UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
    419. 

  419. #define CLK_PCLKDIV_PCLK1DIV16           (0x4UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
    420. 

  420. 

  421. #define CLK_PCLKDIV_APB0DIV_DIV1         (0x0UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
    422. 

  422. #define CLK_PCLKDIV_APB0DIV_DIV2         (0x1UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
    423. 

  423. #define CLK_PCLKDIV_APB0DIV_DIV4         (0x2UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
    424. 

  424. #define CLK_PCLKDIV_APB0DIV_DIV8         (0x3UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
    425. 

  425. #define CLK_PCLKDIV_APB0DIV_DIV16        (0x4UL << CLK_PCLKDIV_APB0DIV_Pos)  /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
    426. 

  426. #define CLK_PCLKDIV_APB1DIV_DIV1         (0x0UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
    427. 

  427. #define CLK_PCLKDIV_APB1DIV_DIV2         (0x1UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
    428. 

  428. #define CLK_PCLKDIV_APB1DIV_DIV4         (0x2UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
    429. 

  429. #define CLK_PCLKDIV_APB1DIV_DIV8         (0x3UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
    430. 

  430. #define CLK_PCLKDIV_APB1DIV_DIV16        (0x4UL << CLK_PCLKDIV_APB1DIV_Pos)  /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
    431. 

  431. 

  432. /*---------------------------------------------------------------------------------------------------------*/
    433. 

  433. /*  PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO                                              */
    434. 

  434. /*---------------------------------------------------------------------------------------------------------*/
    435. 

  435. #define CLK_PLLCTL_PLLSRC_HXT   0x00000000UL    /*!< For PLL clock source is HXT.  4MHz < FIN/NR < 8MHz \hideinitializer */
    436. 

  436. #define CLK_PLLCTL_PLLSRC_HIRC  0x00080000UL    /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
    437. 

  437. 

  438. #define CLK_PLLCTL_NF(x)        (((x)-2UL))       /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
    439. 

  439. #define CLK_PLLCTL_NR(x)        (((x)-1UL)<<9)    /*!< x must be constant and 1 <= x <= 32.  4MHz < FIN/NR < 8MHz \hideinitializer */
    440. 

  440. 

  441. #define CLK_PLLCTL_NO_1         0x0000UL        /*!< For output divider is 1 \hideinitializer */
    442. 

  442. #define CLK_PLLCTL_NO_2         0x4000UL        /*!< For output divider is 2 \hideinitializer */
    443. 

  443. #define CLK_PLLCTL_NO_4         0xC000UL        /*!< For output divider is 4 \hideinitializer */
    444. 

  444. 

  445. #define CLK_PLLCTL_72MHz_HXT    (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    446. 

  446. #define CLK_PLLCTL_80MHz_HXT    (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    447. 

  447. #define CLK_PLLCTL_144MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    448. 

  448. #define CLK_PLLCTL_160MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    449. 

  449. #define CLK_PLLCTL_180MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 45UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 180MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    450. 

  450. #define CLK_PLLCTL_192MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    451. 

  451. #define CLK_PLLCTL_200MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT  | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 25UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 200MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
    452. 

  452. 

  453. #define CLK_PLLCTL_72MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    454. 

  454. #define CLK_PLLCTL_80MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    455. 

  455. #define CLK_PLLCTL_144MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    456. 

  456. #define CLK_PLLCTL_160MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    457. 

  457. #define CLK_PLLCTL_180MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 45UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 180MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    458. 

  458. #define CLK_PLLCTL_192MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    459. 

  459. #define CLK_PLLCTL_200MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 25UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 200MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    460. 

  460. #define CLK_PLLCTL_384MHz_HIRC  (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 48UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 384MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
    461. 

  461. 

  462. /*---------------------------------------------------------------------------------------------------------*/
    463. 

  463. /*  PLLFNCTL constant definitions.                                                                         */
    464. 

  464. /*---------------------------------------------------------------------------------------------------------*/
    465. 

  465. #define CLK_PLLFNCTL1_PLLSRC_HXT   0x00000000UL
    466. 

  466. #define CLK_PLLFNCTL1_PLLSRC_HIRC  CLK_PLLFNCTL1_PLLSRC_Msk
    467. 

  467. 

  468. /*---------------------------------------------------------------------------------------------------------*/
    469. 

  469. /*  MODULE constant definitions.                                                                           */
    470. 

  470. /*---------------------------------------------------------------------------------------------------------*/
    471. 

  471. /* APBCLK(31:29)|CLKSEL(28:26)|CLKSEL_Msk(25:22)|CLKSEL_Pos(21:17)|CLKDIV(16:14)|CLKDIV_Msk(13:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
    472. 

  472. 

  473. #define MODULE_APBCLK(x)        (((x) >>29) & 0x07UL)   /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 \hideinitializer */
    474. 

  474. #define MODULE_CLKSEL(x)        (((x) >>26) & 0x07UL)   /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */
    475. 

  475. #define MODULE_CLKSEL_Msk(x)    (((x) >>22) & 0x0fUL)   /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
    476. 

  476. #define MODULE_CLKSEL_Pos(x)    (((x) >>17) & 0x1fUL)   /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
    477. 

  477. #define MODULE_CLKDIV(x)        (((x) >>14) & 0x07UL)   /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4, 0x5:CLKDIV5 \hideinitializer */
    478. 

  478. #define MODULE_CLKDIV_Msk(x)    (((x) >>10) & 0x0fUL)   /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
    479. 

  479. #define MODULE_CLKDIV_Pos(x)    (((x) >>5 ) & 0x1fUL)   /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
    480. 

  480. #define MODULE_IP_EN_Pos(x)     (((x) >>0 ) & 0x1fUL)   /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
    481. 

  481. #define MODULE_NoMsk            0x0UL                   /*!< Not mask on MODULE index \hideinitializer */
    482. 

  482. #define NA                      MODULE_NoMsk            /*!< Not Available \hideinitializer */
    483. 

  483. 

  484. #define MODULE_APBCLK_ENC(x)        (((x) & 0x07UL) << 29)   /*!< MODULE index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2 0x4:AHBCLK1 \hideinitializer */
    485. 

  485. #define MODULE_CLKSEL_ENC(x)        (((x) & 0x07UL) << 26)   /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4, 0x5:CLKSEL5 \hideinitializer */
    486. 

  486. #define MODULE_CLKSEL_Msk_ENC(x)    (((x) & 0x0fUL) << 22)   /*!< CLKSEL mask offset on MODULE index \hideinitializer */
    487. 

  487. #define MODULE_CLKSEL_Pos_ENC(x)    (((x) & 0x1fUL) << 17)   /*!< CLKSEL position offset on MODULE index \hideinitializer */
    488. 

  488. #define MODULE_CLKDIV_ENC(x)        (((x) & 0x07UL) << 14)   /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4, 0x4:CLKDIV5 \hideinitializer */
    489. 

  489. #define MODULE_CLKDIV_Msk_ENC(x)    (((x) & 0x0fUL) << 10)   /*!< CLKDIV mask offset on MODULE index \hideinitializer */
    490. 

  490. #define MODULE_CLKDIV_Pos_ENC(x)    (((x) & 0x1fUL) <<  5)   /*!< CLKDIV position offset on MODULE index \hideinitializer */
    491. 

  491. #define MODULE_IP_EN_Pos_ENC(x)     (((x) & 0x1fUL) <<  0)   /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
    492. 

  492. 

  493. /* AHBCLK0 */
    494. 

  494. #define PDMA0_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_PDMA0CKEN_Pos)|\
    495. 

  495.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    496. 

  496.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< PDMA0 Module */
    497. 

  497. 

  498. #define ISP_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_ISPCKEN_Pos)|\
    499. 

  499.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    500. 

  500.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ISP Module */
    501. 

  501. 

  502. #define EBI_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_EBICKEN_Pos)|\
    503. 

  503.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    504. 

  504.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EBI Module */
    505. 

  505. 

  506. #define ST_MODULE      (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_STCKEN_Pos)|\
    507. 

  507.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    508. 

  508.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ST Module */
    509. 

  509. 

  510. #define EMAC0_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_EMAC0CKEN_Pos)|\
    511. 

  511.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(    NA)|MODULE_CLKSEL_Pos_ENC(  NA)|\
    512. 

  512.                         MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL))  /*!< EMAC0 Module */
    513. 

  513. 

  514. #define SDH0_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SDH0CKEN_Pos)|\
    515. 

  515.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
    516. 

  516.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL))  /*!< SDH0 Module */
    517. 

  517. 

  518. #define CRC_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CRCCKEN_Pos)|\
    519. 

  519.                         MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    520. 

  520.                         MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))         /*!< CRC Module */
    521. 

  521. 

  522. #define CCAP_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CCAPCKEN_Pos)|\
    523. 

  523.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
    524. 

  524.                         MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))         /*!< CCAP Module */
    525. 

  525. 

  526. #define SEN_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SENCKEN_Pos)|\
    527. 

  527.                         MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(   NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    528. 

  528.                         MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< SEN Module */
    529. 

  529. 

  530. #define HSUSBD_MODULE  (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_HSUSBDCKEN_Pos)|\
    531. 

  531.                         MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    532. 

  532.                         MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))         /*!< HSUSBD Module */
    533. 

  533. 

  534. #define HBI_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_HBICKEN_Pos)|\
    535. 

  535.                         MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    536. 

  536.                         MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))         /*!< HBI Module */
    537. 

  537. 

  538. #define CRPT_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CRPTCKEN_Pos)|\
    539. 

  539.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    540. 

  540.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< CRPT Module */
    541. 

  541. 

  542. #define KS_MODULE      (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_KSCKEN_Pos)|\
    543. 

  543.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    544. 

  544.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< KS Module */
    545. 

  545. 

  546. #define SPIM_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SPIMCKEN_Pos)|\
    547. 

  547.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    548. 

  548.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPIM Module */
    549. 

  549. 

  550. #define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_FMCIDLE_Pos)|\
    551. 

  551.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    552. 

  552.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< FMCIDLE Module */
    553. 

  553. 

  554. #define USBH_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_USBHCKEN_Pos)|\
    555. 

  555.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(  1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
    556. 

  556.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL))   /*!< USBH Module */
    557. 

  557. 

  558. #define SDH1_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SDH1CKEN_Pos)|\
    559. 

  559.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\
    560. 

  560.                         MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL))  /*!< SDH1 Module */
    561. 

  561. 

  562. #define PDMA1_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_PDMA1CKEN_Pos)|\
    563. 

  563.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    564. 

  564.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< PDMA1 Module */
    565. 

  565. 

  566. #define TRACE_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_TRACECKEN_Pos)|\
    567. 

  567.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    568. 

  568.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< TRACE Module */
    569. 

  569. 

  570. #define GPA_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPACKEN_Pos)|\
    571. 

  571.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    572. 

  572.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPA Module */
    573. 

  573. 

  574. #define GPB_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPBCKEN_Pos)|\
    575. 

  575.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    576. 

  576.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPB Module */
    577. 

  577. 

  578. #define GPC_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPCCKEN_Pos)|\
    579. 

  579.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    580. 

  580.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPC Module */
    581. 

  581. 

  582. #define GPD_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPDCKEN_Pos)|\
    583. 

  583.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    584. 

  584.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPD Module */
    585. 

  585. 

  586. #define GPE_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPECKEN_Pos)|\
    587. 

  587.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    588. 

  588.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPE Module */
    589. 

  589. 

  590. #define GPF_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPFCKEN_Pos)|\
    591. 

  591.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    592. 

  592.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPF Module */
    593. 

  593. 

  594. #define GPG_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPGCKEN_Pos)|\
    595. 

  595.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    596. 

  596.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPG Module */
    597. 

  597. 

  598. #define GPH_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPHCKEN_Pos)|\
    599. 

  599.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    600. 

  600.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPH Module */
    601. 

  601. 

  602. /* AHBCLK1 */
    603. 

  603. #define CANFD0_MODULE  (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD0CKEN_Pos)|\
    604. 

  604.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
    605. 

  605.                         MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL))  /*!< CANFD0 Module */
    606. 

  606. 

  607. #define CANFD1_MODULE  (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD1CKEN_Pos)|\
    608. 

  608.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\
    609. 

  609.                         MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL))  /*!< CANFD1 Module */
    610. 

  610. 

  611. #define CANFD2_MODULE  (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD2CKEN_Pos)|\
    612. 

  612.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
    613. 

  613.                         MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< CANFD2 Module */
    614. 

  614. 

  615. #define CANFD3_MODULE  (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD3CKEN_Pos)|\
    616. 

  616.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
    617. 

  617.                         MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL))  /*!< CANFD3 Module */
    618. 

  618. 

  619. #define GPI_MODULE     (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_GPICKEN_Pos)|\
    620. 

  620.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    621. 

  621.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPI Module */
    622. 

  622. 

  623. #define GPJ_MODULE     (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_GPJCKEN_Pos)|\
    624. 

  624.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    625. 

  625.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< GPJ Module */
    626. 

  626. 

  627. #define BMC_MODULE     (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_BMCCKEN_Pos)|\
    628. 

  628.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    629. 

  629.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< BMC Module */
    630. 

  630. 

  631. /* APBCLK0 */
    632. 

  632. #define WDT_MODULE     (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
    633. 

  633.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
    634. 

  634.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC( NA))     /*!< WDT Module */
    635. 

  635. 

  636. #define WWDT_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
    637. 

  637.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
    638. 

  638.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< WWDT Module */
    639. 

  639. 

  640. #define RTC_MODULE     (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\
    641. 

  641.                         MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    642. 

  642.                         MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< RTC Module */
    643. 

  643. 

  644. #define TMR0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\
    645. 

  645.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
    646. 

  646.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< TMR0 Module */
    647. 

  647. 

  648. #define TMR1_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\
    649. 

  649.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
    650. 

  650.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< TMR1 Module */
    651. 

  651. 

  652. #define TMR2_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\
    653. 

  653.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
    654. 

  654.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(    NA))    /*!< TMR2 Module */
    655. 

  655. 

  656. #define TMR3_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\
    657. 

  657.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
    658. 

  658.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< TMR3 Module */
    659. 

  659. 

  660. #define CLKO_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\
    661. 

  661.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
    662. 

  662.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< CLKO Module */
    663. 

  663. 

  664. #define ACMP01_MODULE  (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\
    665. 

  665.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    666. 

  666.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ACMP01 Module */
    667. 

  667. 

  668. #define I2C0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\
    669. 

  669.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    670. 

  670.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C0 Module */
    671. 

  671. 

  672. #define I2C1_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\
    673. 

  673.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    674. 

  674.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C1 Module */
    675. 

  675. 

  676. #define I2C2_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\
    677. 

  677.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    678. 

  678.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C2 Module */
    679. 

  679. 

  680. #define I2C3_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C3CKEN_Pos) |\
    681. 

  681.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    682. 

  682.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C3 Module */
    683. 

  683. 

  684. #define QSPI0_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\
    685. 

  685.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
    686. 

  686.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< QSPI0 Module */
    687. 

  687. 

  688. #define SPI0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\
    689. 

  689.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
    690. 

  690.                         MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(   NA)|MODULE_CLKDIV_Pos_ENC(  NA))     /*!< SPI0 Module */
    691. 

  691. 

  692. #define SPI1_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\
    693. 

  693.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
    694. 

  694.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< SPI1 Module */
    695. 

  695. 

  696. #define SPI2_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\
    697. 

  697.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 9UL)|\
    698. 

  698.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< SPI2 Module */
    699. 

  699. 

  700. #define UART0_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\
    701. 

  701.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
    702. 

  702.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< UART0 Module */
    703. 

  703. 

  704. #define UART1_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\
    705. 

  705.                         MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\
    706. 

  706.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL))  /*!< UART1 Module */
    707. 

  707. 

  708. #define UART2_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\
    709. 

  709.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
    710. 

  710.                         MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL))  /*!< UART2 Module */
    711. 

  711. 

  712. #define UART3_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\
    713. 

  713.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\
    714. 

  714.                         MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL))  /*!< UART3 Module */
    715. 

  715. 

  716. #define UART4_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\
    717. 

  717.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
    718. 

  718.                         MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< UART4 Module */
    719. 

  719. 

  720. #define UART5_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\
    721. 

  721.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
    722. 

  722.                         MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL))  /*!< UART5 Module */
    723. 

  723. 

  724. #define UART6_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART6CKEN_Pos)|\
    725. 

  725.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
    726. 

  726.                         MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL))  /*!< UART6 Module */
    727. 

  727. 

  728. #define UART7_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART7CKEN_Pos)|\
    729. 

  729.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\
    730. 

  730.                         MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(20UL))  /*!< UART7 Module */
    731. 

  731. 

  732. #define OTG_MODULE     (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\
    733. 

  733.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(  1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
    734. 

  734.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL))   /*!< OTG Module */
    735. 

  735. 

  736. #define USBD_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\
    737. 

  737.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(  1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
    738. 

  738.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL))   /*!< USBD Module */
    739. 

  739. 

  740. #define EADC0_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADC0CKEN_Pos)|\
    741. 

  741.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\
    742. 

  742.                         MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL))  /*!< EADC0 Module */
    743. 

  743. 

  744. #define I2S0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\
    745. 

  745.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
    746. 

  746.                         MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL))  /*!< I2S0 Module */
    747. 

  747. 

  748. #define HSOTG_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_HSOTGCKEN_Pos)|\
    749. 

  749.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    750. 

  750.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< HSOTG Module */
    751. 

  751. 

  752. /* APBCLK1 */
    753. 

  753. #define SC0_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos)  |\
    754. 

  754.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
    755. 

  755.                         MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL))  /*!< SC0 Module */
    756. 

  756. 

  757. #define SC1_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos)  |\
    758. 

  758.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
    759. 

  759.                         MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< SC1 Module */
    760. 

  760. 

  761. #define SC2_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos)  |\
    762. 

  762.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
    763. 

  763.                         MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL))  /*!< SC2 Module */
    764. 

  764. 

  765. #define I2C4_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_I2C4CKEN_Pos)|\
    766. 

  766.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    767. 

  767.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C4 Module */
    768. 

  768. 

  769. #define QSPI1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QSPI1CKEN_Pos)|\
    770. 

  770.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\
    771. 

  771.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< QSPI1 Module */
    772. 

  772. 

  773. #define SPI3_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos)|\
    774. 

  774.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
    775. 

  775.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI3 Module */
    776. 

  776. 

  777. #define SPI4_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI4CKEN_Pos)|\
    778. 

  778.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
    779. 

  779.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI4 Module */
    780. 

  780. 

  781. #define USCI0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\
    782. 

  782.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    783. 

  783.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< USCI0 Module */
    784. 

  784. 

  785. #define PSIO_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_PSIOCKEN_Pos)|\
    786. 

  786.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
    787. 

  787.                         MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL))  /*!< PSIO Module */
    788. 

  788. 

  789. #define DAC_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\
    790. 

  790.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    791. 

  791.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< DAC Module */
    792. 

  792. 

  793. #define ECAP2_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP2CKEN_Pos)|\
    794. 

  794.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    795. 

  795.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ECAP2 Module */
    796. 

  796. 

  797. #define ECAP3_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP3CKEN_Pos)|\
    798. 

  798.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    799. 

  799.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ECAP3 Module */
    800. 

  800. 

  801. #define EPWM0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\
    802. 

  802.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
    803. 

  803.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EPWM0 Module */
    804. 

  804. 

  805. #define EPWM1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\
    806. 

  806.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 1UL)|\
    807. 

  807.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EPWM1 Module */
    808. 

  808. 

  809. #define BPWM0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\
    810. 

  810.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
    811. 

  811.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< BPWM0 Module */
    812. 

  812. 

  813. #define BPWM1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\
    814. 

  814.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 9UL)|\
    815. 

  815.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< BPWM1 Module */
    816. 

  816. 

  817. #define EQEI0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI0CKEN_Pos)|\
    818. 

  818.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    819. 

  819.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EQEI0 Module */
    820. 

  820. 

  821. #define EQEI1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI1CKEN_Pos)|\
    822. 

  822.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    823. 

  823.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EQEI1 Module */
    824. 

  824. 

  825. #define EQEI2_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI2CKEN_Pos)|\
    826. 

  826.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    827. 

  827.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EQEI2 Module */
    828. 

  828. 

  829. #define EQEI3_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI3CKEN_Pos)|\
    830. 

  830.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    831. 

  831.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EQEI3 Module */
    832. 

  832. 

  833. #define TRNG_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\
    834. 

  834.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC(27UL)|\
    835. 

  835.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< TRNG Module */
    836. 

  836. 

  837. #define ECAP0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\
    838. 

  838.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    839. 

  839.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ECAP0 Module */
    840. 

  840. 

  841. #define ECAP1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\
    842. 

  842.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    843. 

  843.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ECAP1 Module */
    844. 

  844. 

  845. #define I2S1_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_I2S1CKEN_Pos)|\
    846. 

  846.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
    847. 

  847.                         MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL))  /*!< I2S1 Module */
    848. 

  848. 

  849. #define EADC1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EADC1CKEN_Pos)|\
    850. 

  850.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
    851. 

  851.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< EADC1 Module */
    852. 

  852. 

  853. /* APBCLK2 */
    854. 

  854. #define KPI_MODULE     (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_KPICKEN_Pos)  |\
    855. 

  855.                         MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\
    856. 

  856.                         MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< KPI Module */
    857. 

  857. 

  858. #define EADC2_MODULE   (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_EADC2CKEN_Pos)|\
    859. 

  859.                         MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(14UL)|\
    860. 

  860.                         MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL))  /*!< EADC2 Module */
    861. 

  861. 

  862. #define ACMP23_MODULE  (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_ACMP23CKEN_Pos)  |\
    863. 

  863.                         MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
    864. 

  864.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ACMP23 Module */
    865. 

  865. 

  866. #define SPI5_MODULE    (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI5CKEN_Pos)|\
    867. 

  867.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
    868. 

  868.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI5 Module */
    869. 

  869. 

  870. #define SPI6_MODULE    (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI6CKEN_Pos)|\
    871. 

  871.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
    872. 

  872.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI6 Module */
    873. 

  873. 

  874. #define SPI7_MODULE    (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI7CKEN_Pos)|\
    875. 

  875.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
    876. 

  876.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI7 Module */
    877. 

  877. 

  878. #define SPI8_MODULE    (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI8CKEN_Pos)|\
    879. 

  879.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
    880. 

  880.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI8 Module */
    881. 

  881. 

  882. #define SPI9_MODULE    (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI9CKEN_Pos)|\
    883. 

  883.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
    884. 

  884.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI9 Module */
    885. 

  885. 

  886. #define SPI10_MODULE   (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI10CKEN_Pos)|\
    887. 

  887.                         MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
    888. 

  888.                         MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< SPI10 Module */
    889. 

  889. 

  890. #define UART8_MODULE   (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_UART8CKEN_Pos)|\
    891. 

  891.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
    892. 

  892.                         MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL))  /*!< UART8 Module */
    893. 

  893. 

  894. #define UART9_MODULE   (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_UART9CKEN_Pos)|\
    895. 

  895.                         MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\
    896. 

  896.                         MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(20UL))  /*!< UART9 Module */
    897. 

  897. 

  898. 

  899. /*---------------------------------------------------------------------------------------------------------*/
    900. 

  900. /*  PDMSEL constant definitions.                                                                           */
    901. 

  901. /*---------------------------------------------------------------------------------------------------------*/
    902. 

  902. #define CLK_PMUCTL_PDMSEL_PD          (0x0UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mode is Power-down mode \hideinitializer */
    903. 

  903. #define CLK_PMUCTL_PDMSEL_LLPD        (0x1UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */
    904. 

  904. #define CLK_PMUCTL_PDMSEL_FWPD        (0x2UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */
    905. 

  905. #define CLK_PMUCTL_PDMSEL_SPD         (0x4UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mode is Standby Power-down mode \hideinitializer */
    906. 

  906. #define CLK_PMUCTL_PDMSEL_DPD         (0x6UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select power down mode is Deep Power-down mode \hideinitializer */
    907. 

  907. 

  908. /*---------------------------------------------------------------------------------------------------------*/
    909. 

  909. /*  WKTMRIS constant definitions.                                                                          */
    910. 

  910. /*---------------------------------------------------------------------------------------------------------*/
    911. 

  911. #define CLK_PMUCTL_WKTMRIS_128          (0x0UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
    912. 

  912. #define CLK_PMUCTL_WKTMRIS_256          (0x1UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
    913. 

  913. #define CLK_PMUCTL_WKTMRIS_512          (0x2UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
    914. 

  914. #define CLK_PMUCTL_WKTMRIS_1024         (0x3UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
    915. 

  915. #define CLK_PMUCTL_WKTMRIS_4096         (0x4UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
    916. 

  916. #define CLK_PMUCTL_WKTMRIS_8192         (0x5UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
    917. 

  917. #define CLK_PMUCTL_WKTMRIS_16384        (0x6UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
    918. 

  918. #define CLK_PMUCTL_WKTMRIS_65536        (0x7UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
    919. 

  919. #define CLK_PMUCTL_WKTMRIS_131072       (0x8UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms) \hideinitializer */
    920. 

  920. #define CLK_PMUCTL_WKTMRIS_262144       (0x9UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms) \hideinitializer */
    921. 

  921. #define CLK_PMUCTL_WKTMRIS_524288       (0xaUL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms) \hideinitializer */
    922. 

  922. #define CLK_PMUCTL_WKTMRIS_1048576      (0xbUL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms) \hideinitializer */
    923. 

  923. 

  924. /*---------------------------------------------------------------------------------------------------------*/
    925. 

  925. /*  SWKDBCLKSEL constant definitions.                                                                      */
    926. 

  926. /*---------------------------------------------------------------------------------------------------------*/
    927. 

  927. #define CLK_SWKDBCTL_SWKDBCLKSEL_1          (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
    928. 

  928. #define CLK_SWKDBCTL_SWKDBCLKSEL_2          (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
    929. 

  929. #define CLK_SWKDBCTL_SWKDBCLKSEL_4          (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
    930. 

  930. #define CLK_SWKDBCTL_SWKDBCLKSEL_8          (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
    931. 

  931. #define CLK_SWKDBCTL_SWKDBCLKSEL_16         (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
    932. 

  932. #define CLK_SWKDBCTL_SWKDBCLKSEL_32         (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
    933. 

  933. #define CLK_SWKDBCTL_SWKDBCLKSEL_64         (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
    934. 

  934. #define CLK_SWKDBCTL_SWKDBCLKSEL_128        (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
    935. 

  935. #define CLK_SWKDBCTL_SWKDBCLKSEL_256        (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
    936. 

  936. #define CLK_SWKDBCTL_SWKDBCLKSEL_2x256      (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
    937. 

  937. #define CLK_SWKDBCTL_SWKDBCLKSEL_4x256      (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
    938. 

  938. #define CLK_SWKDBCTL_SWKDBCLKSEL_8x256      (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
    939. 

  939. #define CLK_SWKDBCTL_SWKDBCLKSEL_16x256     (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
    940. 

  940. #define CLK_SWKDBCTL_SWKDBCLKSEL_32x256     (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
    941. 

  941. #define CLK_SWKDBCTL_SWKDBCLKSEL_64x256     (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
    942. 

  942. #define CLK_SWKDBCTL_SWKDBCLKSEL_128x256    (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
    943. 

  943. 

  944. /*---------------------------------------------------------------------------------------------------------*/
    945. 

  945. /*  DPD Pin Rising/Falling Edge Wake-up Enable constant definitions.                                       */
    946. 

  946. /*---------------------------------------------------------------------------------------------------------*/
    947. 

  947. #define CLK_DPDWKPIN0_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN0_Pos)    /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
    948. 

  948. #define CLK_DPDWKPIN0_RISING     (0x1UL << CLK_PMUCTL_WKPINEN0_Pos)    /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
    949. 

  949. #define CLK_DPDWKPIN0_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN0_Pos)    /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
    950. 

  950. #define CLK_DPDWKPIN0_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN0_Pos)    /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */
    951. 

  951. 

  952. #define CLK_DPDWKPIN1_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
    953. 

  953. #define CLK_DPDWKPIN1_RISING     (0x1UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */
    954. 

  954. #define CLK_DPDWKPIN1_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */
    955. 

  955. #define CLK_DPDWKPIN1_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */
    956. 

  956. 

  957. #define CLK_DPDWKPIN2_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
    958. 

  958. #define CLK_DPDWKPIN2_RISING     (0x1UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */
    959. 

  959. #define CLK_DPDWKPIN2_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */
    960. 

  960. #define CLK_DPDWKPIN2_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */
    961. 

  961. 

  962. #define CLK_DPDWKPIN3_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
    963. 

  963. #define CLK_DPDWKPIN3_RISING     (0x1UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */
    964. 

  964. #define CLK_DPDWKPIN3_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */
    965. 

  965. #define CLK_DPDWKPIN3_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */
    966. 

  966. 

  967. #define CLK_DPDWKPIN4_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
    968. 

  968. #define CLK_DPDWKPIN4_RISING     (0x1UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */
    969. 

  969. #define CLK_DPDWKPIN4_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */
    970. 

  970. #define CLK_DPDWKPIN4_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */
    971. 

  971. 

  972. /*---------------------------------------------------------------------------------------------------------*/
    973. 

  973. /*  SPD Pin Rising/Falling Edge Wake-up Enable constant definitions.                                       */
    974. 

  974. /*---------------------------------------------------------------------------------------------------------*/
    975. 

  975. #define CLK_SPDWKPIN_ENABLE         (0x1UL << 0)     /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
    976. 

  976. #define CLK_SPDWKPIN_RISING         (0x1UL << 1)     /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
    977. 

  977. #define CLK_SPDWKPIN_FALLING        (0x1UL << 2)     /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
    978. 

  978. #define CLK_SPDWKPIN_DEBOUNCEEN     (0x1UL << 8)     /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
    979. 

  979. #define CLK_SPDWKPIN_DEBOUNCEDIS    (0x0UL << 8)     /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
    980. 

  980. 

  981. #define CLK_SPDSRETSEL_NO           (0x0UL << CLK_PMUCTL_SRETSEL_Pos)     /*!< No SRAM retention when chip enter SPD mode \hideinitializer */
    982. 

  982. #define CLK_SPDSRETSEL_16K          (0x1UL << CLK_PMUCTL_SRETSEL_Pos)     /*!< 16K SRAM retention when chip enter SPD mode \hideinitializer */
    983. 

  983. #define CLK_SPDSRETSEL_32K          (0x2UL << CLK_PMUCTL_SRETSEL_Pos)     /*!< 32K SRAM retention when chip enter SPD mode \hideinitializer */
    984. 

  984. #define CLK_SPDSRETSEL_64K          (0x3UL << CLK_PMUCTL_SRETSEL_Pos)     /*!< 64K SRAM retention when chip enter SPD mode \hideinitializer */
    985. 

  985. #define CLK_SPDSRETSEL_128K         (0x4UL << CLK_PMUCTL_SRETSEL_Pos)     /*!< 128K SRAM retention when chip enter SPD mode \hideinitializer */
    986. 

  986. #define CLK_SPDSRETSEL_256K         (0x5UL << CLK_PMUCTL_SRETSEL_Pos)     /*!< 256K SRAM retention when chip enter SPD mode \hideinitializer */
    987. 

  987. 

  988. /*---------------------------------------------------------------------------------------------------------*/
    989. 

  989. /* CLK Time-out Handler Constant Definitions                                                               */
    990. 

  990. /*---------------------------------------------------------------------------------------------------------*/
    991. 

  991. #define CLK_TIMEOUT_ERR             (-1)     /*!< Clock timeout error value \hideinitializer */
    992. 

  992. 

  993. /*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
    994. 

  994. 

  995. extern int32_t g_CLK_i32ErrCode;
    996. 

  996. 

  997. /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
    998. 

  998.   @{
    999. 

  999. */
    1000. 

  1000. 

  1001. /**
    1002. 

  1002.   * @brief      Disable Wake-up Timer
    1003. 

  1003.   * @param      None
    1004. 

  1004.   * @return     None
    1005. 

  1005.   * @details    This macro disables Wake-up timer at Standby or Deep Power-down mode.
    1006. 

  1006.   */
    1007. 

  1007. #define CLK_DISABLE_WKTMR()       (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk)
    1008. 

  1008. 

  1009. /**
    1010. 

  1010.   * @brief      Enable Wake-up Timer
    1011. 

  1011.   * @param      None
    1012. 

  1012.   * @return     None
    1013. 

  1013.   * @details    This macro enables Wake-up timer at Standby or Deep Power-down mode.
    1014. 

  1014.   */
    1015. 

  1015. #define CLK_ENABLE_WKTMR()        (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk)
    1016. 

  1016. 

  1017. /**
    1018. 

  1018.   * @brief      Disable DPD Mode Wake-up Pin 0
    1019. 

  1019.   * @param      None
    1020. 

  1020.   * @return     None
    1021. 

  1021.   * @details    This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode.
    1022. 

  1022.   */
    1023. 

  1023. #define CLK_DISABLE_DPDWKPIN0()   (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN0_Msk)
    1024. 

  1024. 

  1025. /**
    1026. 

  1026.   * @brief      Disable DPD Mode Wake-up Pin 1
    1027. 

  1027.   * @param      None
    1028. 

  1028.   * @return     None
    1029. 

  1029.   * @details    This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode.
    1030. 

  1030.   */
    1031. 

  1031. #define CLK_DISABLE_DPDWKPIN1()   (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk)
    1032. 

  1032. 

  1033. /**
    1034. 

  1034.   * @brief      Disable DPD Mode Wake-up Pin 2
    1035. 

  1035.   * @param      None
    1036. 

  1036.   * @return     None
    1037. 

  1037.   * @details    This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode.
    1038. 

  1038.   */
    1039. 

  1039. #define CLK_DISABLE_DPDWKPIN2()   (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk)
    1040. 

  1040. 

  1041. /**
    1042. 

  1042.   * @brief      Disable DPD Mode Wake-up Pin 3
    1043. 

  1043.   * @param      None
    1044. 

  1044.   * @return     None
    1045. 

  1045.   * @details    This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode.
    1046. 

  1046.   */
    1047. 

  1047. #define CLK_DISABLE_DPDWKPIN3()   (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk)
    1048. 

  1048. 

  1049. /**
    1050. 

  1050.   * @brief      Disable DPD Mode Wake-up Pin 4
    1051. 

  1051.   * @param      None
    1052. 

  1052.   * @return     None
    1053. 

  1053.   * @details    This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode.
    1054. 

  1054.   */
    1055. 

  1055. #define CLK_DISABLE_DPDWKPIN4()   (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk)
    1056. 

  1056. 

  1057. /**
    1058. 

  1058.   * @brief      Disable SPD Mode ACMP Wake-up
    1059. 

  1059.   * @param      None
    1060. 

  1060.   * @return     None
    1061. 

  1061.   * @details    This macro disables ACMP wake-up at Standby Power-down mode.
    1062. 

  1062.   */
    1063. 

  1063. #define CLK_DISABLE_SPDACMP()     (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk)
    1064. 

  1064. 

  1065. /**
    1066. 

  1066.   * @brief      Enable SPD Mode ACMP Wake-up
    1067. 

  1067.   * @param      None
    1068. 

  1068.   * @return     None
    1069. 

  1069.   * @details    This macro enables ACMP wake-up at Standby Power-down mode.
    1070. 

  1070.   */
    1071. 

  1071. #define CLK_ENABLE_SPDACMP()      (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk)
    1072. 

  1072. 

  1073. /**
    1074. 

  1074.   * @brief      Disable SPD and DPD Mode RTC Wake-up
    1075. 

  1075.   * @param      None
    1076. 

  1076.   * @return     None
    1077. 

  1077.   * @details    This macro disables RTC Wake-up at Standby or Deep Power-down mode.
    1078. 

  1078.   */
    1079. 

  1079. #define CLK_DISABLE_RTCWK()       (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk)
    1080. 

  1080. 

  1081. /**
    1082. 

  1082.   * @brief      Enable SPD and DPD Mode RTC Wake-up
    1083. 

  1083.   * @param      None
    1084. 

  1084.   * @return     None
    1085. 

  1085.   * @details    This macro enables RTC Wake-up at Standby or Deep Power-down mode.
    1086. 

  1086.   */
    1087. 

  1087. #define CLK_ENABLE_RTCWK()        (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk)
    1088. 

  1088. 

  1089. /**
    1090. 

  1090.  * @brief       Set Wake-up Timer Time-out Interval
    1091. 

  1091.  *
    1092. 

  1092.  * @param[in]   u32Interval   The Wake-up Timer Time-out Interval selection. It could be
    1093. 

  1093.  *                             - \ref CLK_PMUCTL_WKTMRIS_128
    1094. 

  1094.  *                             - \ref CLK_PMUCTL_WKTMRIS_256
    1095. 

  1095.  *                             - \ref CLK_PMUCTL_WKTMRIS_512
    1096. 

  1096.  *                             - \ref CLK_PMUCTL_WKTMRIS_1024
    1097. 

  1097.  *                             - \ref CLK_PMUCTL_WKTMRIS_4096
    1098. 

  1098.  *                             - \ref CLK_PMUCTL_WKTMRIS_8192
    1099. 

  1099.  *                             - \ref CLK_PMUCTL_WKTMRIS_16384
    1100. 

  1100.  *                             - \ref CLK_PMUCTL_WKTMRIS_65536
    1101. 

  1101.  *                             - \ref CLK_PMUCTL_WKTMRIS_131072
    1102. 

  1102.  *                             - \ref CLK_PMUCTL_WKTMRIS_262144
    1103. 

  1103.  *                             - \ref CLK_PMUCTL_WKTMRIS_524288
    1104. 

  1104.  *                             - \ref CLK_PMUCTL_WKTMRIS_1048576
    1105. 

  1105.  *
    1106. 

  1106.  * @return      None
    1107. 

  1107.  *
    1108. 

  1108.  * @details     This function set Wake-up Timer Time-out Interval.
    1109. 

  1109.  *
    1110. 

  1110.  * \hideinitializer
    1111. 

  1111.  */
    1112. 

  1112. #define CLK_SET_WKTMR_INTERVAL(u32Interval)   CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval)
    1113. 

  1113. 

  1114. /**
    1115. 

  1115.  * @brief       Set De-bounce Sampling Cycle Time
    1116. 

  1116.  *
    1117. 

  1117.  * @param[in]   u32CycleSel   The de-bounce sampling cycle selection. It could be
    1118. 

  1118.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
    1119. 

  1119.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
    1120. 

  1120.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
    1121. 

  1121.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
    1122. 

  1122.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
    1123. 

  1123.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
    1124. 

  1124.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
    1125. 

  1125.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
    1126. 

  1126.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
    1127. 

  1127.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
    1128. 

  1128.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
    1129. 

  1129.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
    1130. 

  1130.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
    1131. 

  1131.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
    1132. 

  1132.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
    1133. 

  1133.  *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
    1134. 

  1134.  *
    1135. 

  1135.  * @return      None
    1136. 

  1136.  *
    1137. 

  1137.  * @details     This function set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up.
    1138. 

  1138.  *
    1139. 

  1139.  * \hideinitializer
    1140. 

  1140.  */
    1141. 

  1141. #define CLK_SET_SPDDEBOUNCETIME(u32CycleSel)    (CLK->SWKDBCTL = (u32CycleSel))
    1142. 

  1142. 

  1143. /*---------------------------------------------------------------------------------------------------------*/
    1144. 

  1144. /* static inline functions                                                                                 */
    1145. 

  1145. /*---------------------------------------------------------------------------------------------------------*/
    1146. 

  1146. /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
    1147. 

  1147. __STATIC_INLINE int32_t CLK_SysTickDelay(uint32_t us);
    1148. 

  1148. __STATIC_INLINE int32_t CLK_SysTickLongDelay(uint32_t us);
    1149. 

  1149. 

  1150. /**
    1151. 

  1151.   * @brief      This function execute delay function.
    1152. 

  1152.   * @param[in]  us  Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
    1153. 

  1153.   *                             200MHz => 83886us, 180MHz => 93206us ...
    1154. 

  1154.   * @retval     0 Delay success. Target delay time reached.
    1155. 

  1155.   * @retval     CLK_TIMEOUT_ERR Delay function execute failed due to SysTick stop working.
    1156. 

  1156.   * @details    Use the SysTick to generate the delay time and the unit is in us.
    1157. 

  1157.   *             The SysTick clock source is from HCLK, i.e the same as system core clock.
    1158. 

  1158.   *             User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
    1159. 

  1159.   */
    1160. 

  1160. __STATIC_INLINE int32_t CLK_SysTickDelay(uint32_t us)
    1161. 

  1161. {
    1162. 

  1162.     /* The u32TimeOutCnt value must be greater than the max delay time of 1398ms if HCLK=12MHz */
    1163. 

  1163.     uint32_t u32TimeOutCnt = SystemCoreClock << 1; /* 2 second time-out */
    1164. 

  1164. 

  1165.     SysTick->LOAD = us * CyclesPerUs;
    1166. 

  1166.     SysTick->VAL  = (0x00);
    1167. 

  1167.     SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
    1168. 

  1168. 

  1169.     /* Waiting for down-count to zero */
    1170. 

  1170.     while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0)
    1171. 

  1171.     {
    1172. 

  1172.         if (--u32TimeOutCnt == 0)
    1173. 

  1173.         {
    1174. 

  1174.             break;
    1175. 

  1175.         }
    1176. 

  1176.     }
    1177. 

  1177. 

  1178.     /* Disable SysTick counter */
    1179. 

  1179.     SysTick->CTRL = 0;
    1180. 

  1180. 

  1181.     if (u32TimeOutCnt == 0)
    1182. 

  1182.         return CLK_TIMEOUT_ERR;
    1183. 

  1183.     else
    1184. 

  1184.         return 0;
    1185. 

  1185. }
    1186. 

  1186. 

  1187. /**
    1188. 

  1188.   * @brief      This function execute long delay function.
    1189. 

  1189.   * @param[in]  us  Delay time.
    1190. 

  1190.   * @retval     0 Delay success. Target delay time reached.
    1191. 

  1191.   * @retval     CLK_TIMEOUT_ERR Delay function execute failed due to SysTick stop working.
    1192. 

  1192.   * @details    Use the SysTick to generate the long delay time and the UNIT is in us.
    1193. 

  1193.   *             The SysTick clock source is from HCLK, i.e the same as system core clock.
    1194. 

  1194.   *             User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
    1195. 

  1195.   */
    1196. 

  1196. __STATIC_INLINE int32_t CLK_SysTickLongDelay(uint32_t us)
    1197. 

  1197. {
    1198. 

  1198.     /* The u32TimeOutCnt value must be greater than the max delay time of 1398ms if HCLK=12MHz */
    1199. 

  1199.     uint32_t u32Delay, u32TimeOutCnt;
    1200. 

  1200. 

  1201.     /* It should <= 65536us for each delay loop */
    1202. 

  1202.     u32Delay = 65536UL;
    1203. 

  1203. 

  1204.     do
    1205. 

  1205.     {
    1206. 

  1206.         if (us > u32Delay)
    1207. 

  1207.         {
    1208. 

  1208.             us -= u32Delay;
    1209. 

  1209.         }
    1210. 

  1210.         else
    1211. 

  1211.         {
    1212. 

  1212.             u32Delay = us;
    1213. 

  1213.             us = 0UL;
    1214. 

  1214.         }
    1215. 

  1215. 

  1216.         SysTick->LOAD = u32Delay * CyclesPerUs;
    1217. 

  1217.         SysTick->VAL  = (0x0UL);
    1218. 

  1218.         SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
    1219. 

  1219. 

  1220.         /* Waiting for down-count to zero */
    1221. 

  1221.         u32TimeOutCnt = SystemCoreClock << 1; /* 2 second time-out */
    1222. 

  1222.         while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
    1223. 

  1223.             if (--u32TimeOutCnt == 0) break;
    1224. 

  1224. 

  1225.         /* Disable SysTick counter */
    1226. 

  1226.         SysTick->CTRL = 0UL;
    1227. 

  1227.     }
    1228. 

  1228.     while ((us > 0UL) && (u32TimeOutCnt != 0));
    1229. 

  1229. 

  1230.     if (u32TimeOutCnt == 0)
    1231. 

  1231.         return CLK_TIMEOUT_ERR;
    1232. 

  1232.     else
    1233. 

  1233.         return 0;
    1234. 

  1234. }
    1235. 

  1235. 

  1236. 

  1237. void CLK_DisableCKO(void);
    1238. 

  1238. void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
    1239. 

  1239. void CLK_PowerDown(void);
    1240. 

  1240. void CLK_Idle(void);
    1241. 

  1241. uint32_t CLK_GetHXTFreq(void);
    1242. 

  1242. uint32_t CLK_GetLXTFreq(void);
    1243. 

  1243. uint32_t CLK_GetHCLKFreq(void);
    1244. 

  1244. uint32_t CLK_GetPCLK0Freq(void);
    1245. 

  1245. uint32_t CLK_GetPCLK1Freq(void);
    1246. 

  1246. uint32_t CLK_GetCPUFreq(void);
    1247. 

  1247. uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
    1248. 

  1248. void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
    1249. 

  1249. void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
    1250. 

  1250. void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
    1251. 

  1251. void CLK_EnableXtalRC(uint32_t u32ClkMask);
    1252. 

  1252. void CLK_DisableXtalRC(uint32_t u32ClkMask);
    1253. 

  1253. void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
    1254. 

  1254. void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
    1255. 

  1255. uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
    1256. 

  1256. void CLK_DisablePLL(void);
    1257. 

  1257. uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
    1258. 

  1258. void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
    1259. 

  1259. void CLK_DisableSysTick(void);
    1260. 

  1260. void CLK_SetPowerDownMode(uint32_t u32PDMode);
    1261. 

  1261. void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
    1262. 

  1262. uint32_t CLK_GetPMUWKSrc(void);
    1263. 

  1263. void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
    1264. 

  1264. uint32_t CLK_GetPLLClockFreq(void);
    1265. 

  1265. uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
    1266. 

  1266. uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
    1267. 

  1267. void CLK_DisablePLLFN(void);
    1268. 

  1268. uint32_t CLK_EnablePLLFN(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
    1269. 

  1269. uint32_t CLK_GetPLLFNClockFreq(void);
    1270. 

  1270. 

  1271. /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
    1272. 

  1272. 

  1273. /*@}*/ /* end of group CLK_Driver */
    1274. 

  1274. 

  1275. /*@}*/ /* end of group Standard_Driver */
    1276. 

  1276. 

  1277. #ifdef __cplusplus
    1278. 

  1278. }
    1279. 

  1279. #endif
    1280. 

  1280. 

  1281. #endif  /* __NU_CLK_H__ */
    1282.