drv_spii2s.c 22 KB

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  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2022-3-15 Wayne First version
  10. *
  11. ******************************************************************************/
  12. #include <rtconfig.h>
  13. #if defined(BSP_USING_SPII2S)
  14. #include <rtdevice.h>
  15. #include <drv_pdma.h>
  16. #include <drv_i2s.h>
  17. /* Private define ---------------------------------------------------------------*/
  18. #define DBG_ENABLE
  19. #define DBG_LEVEL DBG_LOG
  20. #define DBG_SECTION_NAME "spii2s"
  21. #define DBG_COLOR
  22. #include <rtdbg.h>
  23. enum
  24. {
  25. SPII2S_START = -1,
  26. #if defined(BSP_USING_SPII2S0)
  27. SPII2S0_IDX,
  28. #endif
  29. #if defined(BSP_USING_SPII2S1)
  30. SPII2S1_IDX,
  31. #endif
  32. #if defined(BSP_USING_SPII2S2)
  33. SPII2S2_IDX,
  34. #endif
  35. #if defined(BSP_USING_SPII2S3)
  36. SPII2S3_IDX,
  37. #endif
  38. #if defined(BSP_USING_SPII2S4)
  39. SPII2S4_IDX,
  40. #endif
  41. #if defined(BSP_USING_SPII2S5)
  42. SPII2S5_IDX,
  43. #endif
  44. #if defined(BSP_USING_SPII2S6)
  45. SPII2S6_IDX,
  46. #endif
  47. #if defined(BSP_USING_SPII2S7)
  48. SPII2S7_IDX,
  49. #endif
  50. #if defined(BSP_USING_SPII2S8)
  51. SPII2S8_IDX,
  52. #endif
  53. #if defined(BSP_USING_SPII2S9)
  54. SPII2S9_IDX,
  55. #endif
  56. #if defined(BSP_USING_SPII2S10)
  57. SPII2S10_IDX,
  58. #endif
  59. SPII2S_CNT
  60. };
  61. /* Private functions ------------------------------------------------------------*/
  62. static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps);
  63. static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps);
  64. static rt_err_t nu_spii2s_init(struct rt_audio_device *audio);
  65. static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream);
  66. static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream);
  67. static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
  68. /* Public functions -------------------------------------------------------------*/
  69. rt_err_t nu_spii2s_acodec_register(struct rt_audio_device *audio, nu_acodec_ops_t);
  70. /* Private variables ------------------------------------------------------------*/
  71. static struct nu_i2s g_nu_spii2s_arr [] =
  72. {
  73. #if defined(BSP_USING_SPII2S0)
  74. {
  75. .name = "spii2s0",
  76. .i2s_base = (I2S_T *)SPI0, //Avoid warning
  77. .i2s_rst = SPI0_RST,
  78. .i2s_dais = {
  79. [NU_I2S_DAI_PLAYBACK] = {
  80. .pdma_perp = PDMA_SPI0_TX,
  81. },
  82. [NU_I2S_DAI_CAPTURE] = {
  83. .pdma_perp = PDMA_SPI0_RX,
  84. }
  85. }
  86. },
  87. #endif
  88. #if defined(BSP_USING_SPII2S1)
  89. {
  90. .name = "spii2s1",
  91. .i2s_base = (I2S_T *)SPI1, //Avoid warning
  92. .i2s_rst = SPI1_RST,
  93. .i2s_dais = {
  94. [NU_I2S_DAI_PLAYBACK] = {
  95. .pdma_perp = PDMA_SPI1_TX,
  96. },
  97. [NU_I2S_DAI_CAPTURE] = {
  98. .pdma_perp = PDMA_SPI1_RX,
  99. }
  100. }
  101. },
  102. #endif
  103. #if defined(BSP_USING_SPII2S2)
  104. {
  105. .name = "spii2s2",
  106. .i2s_base = (I2S_T *)SPI2, //Avoid warning
  107. .i2s_rst = SPI2_RST,
  108. .i2s_dais = {
  109. [NU_I2S_DAI_PLAYBACK] = {
  110. .pdma_perp = PDMA_SPI2_TX,
  111. },
  112. [NU_I2S_DAI_CAPTURE] = {
  113. .pdma_perp = PDMA_SPI2_RX,
  114. }
  115. }
  116. },
  117. #endif
  118. #if defined(BSP_USING_SPII2S3)
  119. {
  120. .name = "spii2s3",
  121. .i2s_base = (I2S_T *)SPI3, //Avoid warning
  122. .i2s_rst = SPI3_RST,
  123. .i2s_dais = {
  124. [NU_I2S_DAI_PLAYBACK] = {
  125. .pdma_perp = PDMA_SPI3_TX,
  126. },
  127. [NU_I2S_DAI_CAPTURE] = {
  128. .pdma_perp = PDMA_SPI3_RX,
  129. }
  130. }
  131. },
  132. #endif
  133. #if defined(BSP_USING_SPII2S4)
  134. {
  135. .name = "spii2s4",
  136. .i2s_base = (I2S_T *)SPI4, //Avoid warning
  137. .i2s_rst = SPI4_RST,
  138. .i2s_dais = {
  139. [NU_I2S_DAI_PLAYBACK] = {
  140. .pdma_perp = PDMA_SPI4_TX,
  141. },
  142. [NU_I2S_DAI_CAPTURE] = {
  143. .pdma_perp = PDMA_SPI4_RX,
  144. }
  145. }
  146. },
  147. #endif
  148. #if defined(BSP_USING_SPII2S5)
  149. {
  150. .name = "spii2s5",
  151. .i2s_base = (I2S_T *)SPI5, //Avoid warning
  152. .i2s_rst = SPI5_RST,
  153. .i2s_dais = {
  154. [NU_I2S_DAI_PLAYBACK] = {
  155. .pdma_perp = PDMA_SPI5_TX,
  156. },
  157. [NU_I2S_DAI_CAPTURE] = {
  158. .pdma_perp = PDMA_SPI5_RX,
  159. }
  160. }
  161. },
  162. #endif
  163. #if defined(BSP_USING_SPII2S6)
  164. {
  165. .name = "spii2s6",
  166. .i2s_base = (I2S_T *)SPI6, //Avoid warning
  167. .i2s_rst = SPI6_RST,
  168. .i2s_dais = {
  169. [NU_I2S_DAI_PLAYBACK] = {
  170. .pdma_perp = PDMA_SPI6_TX,
  171. },
  172. [NU_I2S_DAI_CAPTURE] = {
  173. .pdma_perp = PDMA_SPI6_RX,
  174. }
  175. }
  176. },
  177. #endif
  178. #if defined(BSP_USING_SPII2S7)
  179. {
  180. .name = "spii2s7",
  181. .i2s_base = (I2S_T *)SPI7, //Avoid warning
  182. .i2s_rst = SPI7_RST,
  183. .i2s_dais = {
  184. [NU_I2S_DAI_PLAYBACK] = {
  185. .pdma_perp = PDMA_SPI7_TX,
  186. },
  187. [NU_I2S_DAI_CAPTURE] = {
  188. .pdma_perp = PDMA_SPI7_RX,
  189. }
  190. }
  191. },
  192. #endif
  193. #if defined(BSP_USING_SPII2S8)
  194. {
  195. .name = "spii2s8",
  196. .i2s_base = (I2S_T *)SPI8, //Avoid warning
  197. .i2s_rst = SPI8_RST,
  198. .i2s_dais = {
  199. [NU_I2S_DAI_PLAYBACK] = {
  200. .pdma_perp = PDMA_SPI8_TX,
  201. },
  202. [NU_I2S_DAI_CAPTURE] = {
  203. .pdma_perp = PDMA_SPI8_RX,
  204. }
  205. }
  206. },
  207. #endif
  208. #if defined(BSP_USING_SPII2S9)
  209. {
  210. .name = "spii2s9",
  211. .i2s_base = (I2S_T *)SPI9, //Avoid warning
  212. .i2s_rst = SPI9_RST,
  213. .i2s_dais = {
  214. [NU_I2S_DAI_PLAYBACK] = {
  215. .pdma_perp = PDMA_SPI9_TX,
  216. },
  217. [NU_I2S_DAI_CAPTURE] = {
  218. .pdma_perp = PDMA_SPI9_RX,
  219. }
  220. }
  221. },
  222. #endif
  223. #if defined(BSP_USING_SPII2S10)
  224. {
  225. .name = "spii2s10",
  226. .i2s_base = (I2S_T *)SPI10, //Avoid warning
  227. .i2s_rst = SPI10_RST,
  228. .i2s_dais = {
  229. [NU_I2S_DAI_PLAYBACK] = {
  230. .pdma_perp = PDMA_SPI10_TX,
  231. },
  232. [NU_I2S_DAI_CAPTURE] = {
  233. .pdma_perp = PDMA_SPI10_RX,
  234. }
  235. }
  236. },
  237. #endif
  238. };
  239. static void nu_pdma_spii2s_rx_cb(void *pvUserData, uint32_t u32EventFilter)
  240. {
  241. nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData;
  242. nu_i2s_dai_t psNuSPII2sDai;
  243. RT_ASSERT(psNuSPII2s != RT_NULL);
  244. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE];
  245. if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
  246. {
  247. // Report a buffer ready.
  248. rt_uint8_t *pbuf_old = &psNuSPII2sDai->fifo[psNuSPII2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ;
  249. psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
  250. /* Report upper layer. */
  251. rt_audio_rx_done(&psNuSPII2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE);
  252. }
  253. }
  254. static void nu_pdma_spii2s_tx_cb(void *pvUserData, uint32_t u32EventFilter)
  255. {
  256. nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData;
  257. nu_i2s_dai_t psNuSPII2sDai;
  258. RT_ASSERT(psNuSPII2s != RT_NULL);
  259. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
  260. if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
  261. {
  262. rt_audio_tx_complete(&psNuSPII2s->audio);
  263. psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
  264. }
  265. }
  266. static rt_err_t nu_spii2s_pdma_sc_config(nu_i2s_t psNuSPII2s, E_NU_I2S_DAI dai)
  267. {
  268. rt_err_t result = RT_EOK;
  269. SPI_T *spii2s_base;
  270. nu_i2s_dai_t psNuSPII2sDai;
  271. int i;
  272. uint32_t u32Src, u32Dst;
  273. nu_pdma_cb_handler_t pfm_pdma_cb;
  274. struct nu_pdma_chn_cb sChnCB;
  275. RT_ASSERT(psNuSPII2s != RT_NULL);
  276. /* Get base address of spii2s register */
  277. spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  278. psNuSPII2sDai = &psNuSPII2s->i2s_dais[dai];
  279. switch ((int)dai)
  280. {
  281. case NU_I2S_DAI_PLAYBACK:
  282. pfm_pdma_cb = nu_pdma_spii2s_tx_cb;
  283. u32Src = (uint32_t)&psNuSPII2sDai->fifo[0];
  284. u32Dst = (uint32_t)&spii2s_base->TX;
  285. break;
  286. case NU_I2S_DAI_CAPTURE:
  287. pfm_pdma_cb = nu_pdma_spii2s_rx_cb;
  288. u32Src = (uint32_t)&spii2s_base->RX;
  289. u32Dst = (uint32_t)&psNuSPII2sDai->fifo[0];
  290. break;
  291. default:
  292. return -RT_EINVAL;
  293. }
  294. /* Register ISR callback function */
  295. sChnCB.m_eCBType = eCBType_Event;
  296. sChnCB.m_pfnCBHandler = pfm_pdma_cb;
  297. sChnCB.m_pvUserData = (void *)psNuSPII2s;
  298. nu_pdma_filtering_set(psNuSPII2sDai->pdma_chanid, NU_PDMA_EVENT_TRANSFER_DONE);
  299. result = nu_pdma_callback_register(psNuSPII2sDai->pdma_chanid, &sChnCB);
  300. RT_ASSERT(result == RT_EOK);
  301. for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++)
  302. {
  303. /* Setup dma descriptor entry */
  304. result = nu_pdma_desc_setup(psNuSPII2sDai->pdma_chanid, // Channel ID
  305. psNuSPII2sDai->pdma_descs[i], // this descriptor
  306. 32, // 32-bits
  307. (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO
  308. (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory
  309. (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count
  310. psNuSPII2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER], // Next descriptor
  311. 0); // Interrupt assert when every SG-table done.
  312. RT_ASSERT(result == RT_EOK);
  313. }
  314. /* Assign head descriptor */
  315. result = nu_pdma_sg_transfer(psNuSPII2sDai->pdma_chanid, psNuSPII2sDai->pdma_descs[0], 0);
  316. RT_ASSERT(result == RT_EOK);
  317. return result;
  318. }
  319. static rt_bool_t nu_spii2s_capacity_check(struct rt_audio_configure *pconfig)
  320. {
  321. switch (pconfig->samplebits)
  322. {
  323. case 8:
  324. case 16:
  325. /* case 24: PDMA constrain */
  326. case 32:
  327. break;
  328. default:
  329. goto exit_nu_spii2s_capacity_check;
  330. }
  331. switch (pconfig->channels)
  332. {
  333. case 1:
  334. case 2:
  335. break;
  336. default:
  337. goto exit_nu_spii2s_capacity_check;
  338. }
  339. return RT_TRUE;
  340. exit_nu_spii2s_capacity_check:
  341. return RT_FALSE;
  342. }
  343. static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configure *pconfig)
  344. {
  345. rt_err_t result = RT_EOK;
  346. nu_acodec_ops_t pNuACodecOps;
  347. SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  348. RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
  349. pNuACodecOps = psNuSPII2s->AcodecOps;
  350. /* Open SPII2S */
  351. if (nu_spii2s_capacity_check(pconfig) == RT_TRUE)
  352. {
  353. /* Reset audio codec */
  354. if (pNuACodecOps->nu_acodec_reset)
  355. result = pNuACodecOps->nu_acodec_reset();
  356. if (result != RT_EOK)
  357. goto exit_nu_spii2s_dai_setup;
  358. /* Setup audio codec */
  359. if (pNuACodecOps->nu_acodec_init)
  360. result = pNuACodecOps->nu_acodec_init();
  361. if (!pNuACodecOps->nu_acodec_init || result != RT_EOK)
  362. goto exit_nu_spii2s_dai_setup;
  363. /* Setup acodec samplerate/samplebit/channel */
  364. if (pNuACodecOps->nu_acodec_dsp_control)
  365. result = pNuACodecOps->nu_acodec_dsp_control(pconfig);
  366. if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK)
  367. goto exit_nu_spii2s_dai_setup;
  368. SPII2S_Open(spii2s_base,
  369. (psNuSPII2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? SPII2S_MODE_SLAVE : SPII2S_MODE_MASTER,
  370. pconfig->samplerate,
  371. (((pconfig->samplebits / 8) - 1) << SPI_I2SCTL_WDWIDTH_Pos),
  372. (pconfig->channels == 1) ? SPII2S_MONO : SPII2S_STEREO,
  373. SPII2S_FORMAT_I2S);
  374. LOG_I("Open SPII2S.");
  375. /* Set MCLK and enable MCLK */
  376. /* The target MCLK is related to audio codec setting. */
  377. SPII2S_EnableMCLK(spii2s_base, 12000000);
  378. /* Set un-mute */
  379. if (pNuACodecOps->nu_acodec_mixer_control)
  380. pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE);
  381. }
  382. else
  383. result = -RT_EINVAL;
  384. exit_nu_spii2s_dai_setup:
  385. return result;
  386. }
  387. static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
  388. {
  389. rt_err_t result = RT_EOK;
  390. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  391. nu_acodec_ops_t pNuACodecOps;
  392. RT_ASSERT(audio != RT_NULL);
  393. RT_ASSERT(caps != RT_NULL);
  394. RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
  395. pNuACodecOps = psNuSPII2s->AcodecOps;
  396. switch (caps->main_type)
  397. {
  398. case AUDIO_TYPE_QUERY:
  399. switch (caps->sub_type)
  400. {
  401. case AUDIO_TYPE_QUERY:
  402. caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
  403. break;
  404. default:
  405. result = -RT_ERROR;
  406. break;
  407. } // switch (caps->sub_type)
  408. break;
  409. case AUDIO_TYPE_MIXER:
  410. if (pNuACodecOps->nu_acodec_mixer_query)
  411. {
  412. switch (caps->sub_type)
  413. {
  414. case AUDIO_MIXER_QUERY:
  415. return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask);
  416. default:
  417. return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value);
  418. } // switch (caps->sub_type)
  419. } // if (pNuACodecOps->nu_acodec_mixer_query)
  420. result = -RT_ERROR;
  421. break;
  422. case AUDIO_TYPE_INPUT:
  423. case AUDIO_TYPE_OUTPUT:
  424. switch (caps->sub_type)
  425. {
  426. case AUDIO_DSP_PARAM:
  427. caps->udata.config.channels = psNuSPII2s->config.channels;
  428. caps->udata.config.samplebits = psNuSPII2s->config.samplebits;
  429. caps->udata.config.samplerate = psNuSPII2s->config.samplerate;
  430. break;
  431. case AUDIO_DSP_SAMPLERATE:
  432. caps->udata.config.samplerate = psNuSPII2s->config.samplerate;
  433. break;
  434. case AUDIO_DSP_CHANNELS:
  435. caps->udata.config.channels = psNuSPII2s->config.channels;
  436. break;
  437. case AUDIO_DSP_SAMPLEBITS:
  438. caps->udata.config.samplebits = psNuSPII2s->config.samplebits;
  439. break;
  440. default:
  441. result = -RT_ERROR;
  442. break;
  443. } // switch (caps->sub_type)
  444. break;
  445. default:
  446. result = -RT_ERROR;
  447. break;
  448. } // switch (caps->main_type)
  449. return result;
  450. }
  451. static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
  452. {
  453. rt_err_t result = RT_EOK;
  454. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  455. nu_acodec_ops_t pNuACodecOps;
  456. int stream = -1;
  457. RT_ASSERT(audio != RT_NULL);
  458. RT_ASSERT(caps != RT_NULL);
  459. RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
  460. pNuACodecOps = psNuSPII2s->AcodecOps;
  461. switch (caps->main_type)
  462. {
  463. case AUDIO_TYPE_MIXER:
  464. if (psNuSPII2s->AcodecOps->nu_acodec_mixer_control)
  465. psNuSPII2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value);
  466. break;
  467. case AUDIO_TYPE_INPUT:
  468. stream = AUDIO_STREAM_RECORD;
  469. case AUDIO_TYPE_OUTPUT:
  470. {
  471. rt_bool_t bNeedReset = RT_FALSE;
  472. if (stream < 0)
  473. stream = AUDIO_STREAM_REPLAY;
  474. switch (caps->sub_type)
  475. {
  476. case AUDIO_DSP_PARAM:
  477. if (rt_memcmp(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0)
  478. {
  479. rt_memcpy(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure));
  480. bNeedReset = RT_TRUE;
  481. }
  482. break;
  483. case AUDIO_DSP_SAMPLEBITS:
  484. if (psNuSPII2s->config.samplerate != caps->udata.config.samplebits)
  485. {
  486. psNuSPII2s->config.samplerate = caps->udata.config.samplebits;
  487. bNeedReset = RT_TRUE;
  488. }
  489. break;
  490. case AUDIO_DSP_CHANNELS:
  491. if (psNuSPII2s->config.channels != caps->udata.config.channels)
  492. {
  493. pNuACodecOps->config.channels = caps->udata.config.channels;
  494. bNeedReset = RT_TRUE;
  495. }
  496. break;
  497. case AUDIO_DSP_SAMPLERATE:
  498. if (psNuSPII2s->config.samplerate != caps->udata.config.samplerate)
  499. {
  500. psNuSPII2s->config.samplerate = caps->udata.config.samplerate;
  501. bNeedReset = RT_TRUE;
  502. }
  503. break;
  504. default:
  505. result = -RT_ERROR;
  506. break;
  507. } // switch (caps->sub_type)
  508. if (bNeedReset)
  509. {
  510. return nu_spii2s_start(audio, stream);
  511. }
  512. }
  513. break;
  514. default:
  515. result = -RT_ERROR;
  516. break;
  517. } // switch (caps->main_type)
  518. return result;
  519. }
  520. static rt_err_t nu_spii2s_init(struct rt_audio_device *audio)
  521. {
  522. rt_err_t result = RT_EOK;
  523. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  524. RT_ASSERT(audio != RT_NULL);
  525. /* Reset this module */
  526. SYS_ResetModule(psNuSPII2s->i2s_rst);
  527. return -(result);
  528. }
  529. static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream)
  530. {
  531. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  532. SPI_T *spii2s_base;
  533. RT_ASSERT(audio != RT_NULL);
  534. spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  535. /* Restart all: SPII2S and codec. */
  536. nu_spii2s_stop(audio, stream);
  537. if (nu_spii2s_dai_setup(psNuSPII2s, &psNuSPII2s->config) != RT_EOK)
  538. return -RT_ERROR;
  539. switch (stream)
  540. {
  541. case AUDIO_STREAM_REPLAY:
  542. {
  543. nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_PLAYBACK);
  544. /* Start TX DMA */
  545. SPII2S_ENABLE_TXDMA(spii2s_base);
  546. /* Enable I2S Tx function */
  547. SPII2S_ENABLE_TX(spii2s_base);
  548. LOG_I("Start replay.");
  549. }
  550. break;
  551. case AUDIO_STREAM_RECORD:
  552. {
  553. nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_CAPTURE);
  554. /* Start RX DMA */
  555. SPII2S_ENABLE_RXDMA(spii2s_base);
  556. /* Enable I2S Rx function */
  557. SPII2S_ENABLE_RX(spii2s_base);
  558. LOG_I("Start record.");
  559. }
  560. break;
  561. default:
  562. return -RT_ERROR;
  563. }
  564. return RT_EOK;
  565. }
  566. static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream)
  567. {
  568. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  569. nu_i2s_dai_t psNuSPII2sDai = RT_NULL;
  570. SPI_T *spii2s_base;
  571. RT_ASSERT(audio != RT_NULL);
  572. spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
  573. switch (stream)
  574. {
  575. case AUDIO_STREAM_REPLAY:
  576. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
  577. // Disable TX
  578. SPII2S_DISABLE_TXDMA(spii2s_base);
  579. SPII2S_DISABLE_TX(spii2s_base);
  580. LOG_I("Stop replay.");
  581. break;
  582. case AUDIO_STREAM_RECORD:
  583. psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE];
  584. // Disable RX
  585. SPII2S_DISABLE_RXDMA(spii2s_base);
  586. SPII2S_DISABLE_RX(spii2s_base);
  587. LOG_I("Stop record.");
  588. break;
  589. default:
  590. return -RT_EINVAL;
  591. }
  592. /* Stop DMA transfer. */
  593. nu_pdma_channel_terminate(psNuSPII2sDai->pdma_chanid);
  594. /* Close SPII2S */
  595. if (!(spii2s_base->I2SCTL & (SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_RXEN_Msk)))
  596. {
  597. SPII2S_DisableMCLK(spii2s_base);
  598. SPII2S_Close(spii2s_base);
  599. LOG_I("Close SPII2S.");
  600. }
  601. /* Silence */
  602. rt_memset((void *)psNuSPII2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE);
  603. psNuSPII2sDai->fifo_block_idx = 0;
  604. return RT_EOK;
  605. }
  606. static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
  607. {
  608. nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
  609. RT_ASSERT(audio != RT_NULL);
  610. RT_ASSERT(info != RT_NULL);
  611. info->buffer = (rt_uint8_t *)psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ;
  612. info->total_size = NU_I2S_DMA_FIFO_SIZE;
  613. info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE;
  614. info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER;
  615. return;
  616. }
  617. static struct rt_audio_ops nu_spii2s_audio_ops =
  618. {
  619. .getcaps = nu_spii2s_getcaps,
  620. .configure = nu_spii2s_configure,
  621. .init = nu_spii2s_init,
  622. .start = nu_spii2s_start,
  623. .stop = nu_spii2s_stop,
  624. .transmit = RT_NULL,
  625. .buffer_info = nu_spii2s_buffer_info
  626. };
  627. static rt_err_t nu_hw_spii2s_pdma_allocate(nu_i2s_dai_t psNuSPII2sDai)
  628. {
  629. /* Allocate I2S nu_dma channel */
  630. if ((psNuSPII2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuSPII2sDai->pdma_perp)) < 0)
  631. {
  632. goto nu_hw_spii2s_pdma_allocate;
  633. }
  634. return RT_EOK;
  635. nu_hw_spii2s_pdma_allocate:
  636. return -(RT_ERROR);
  637. }
  638. int rt_hw_spii2s_init(void)
  639. {
  640. int j = 0;
  641. nu_i2s_dai_t psNuSPII2sDai;
  642. for (j = (SPII2S_START + 1); j < SPII2S_CNT; j++)
  643. {
  644. int i = 0;
  645. SYS_ResetModule(g_nu_spii2s_arr[i].i2s_rst);
  646. for (i = 0; i < NU_I2S_DAI_CNT; i++)
  647. {
  648. uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE);
  649. psNuSPII2sDai = &g_nu_spii2s_arr[j].i2s_dais[i];
  650. psNuSPII2sDai->fifo = pu8ptr;
  651. rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE);
  652. RT_ASSERT(psNuSPII2sDai->fifo != RT_NULL);
  653. psNuSPII2sDai->pdma_chanid = -1;
  654. psNuSPII2sDai->fifo_block_idx = 0;
  655. RT_ASSERT(nu_hw_spii2s_pdma_allocate(psNuSPII2sDai) == RT_EOK);
  656. RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuSPII2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK);
  657. }
  658. /* Register ops of audio device */
  659. g_nu_spii2s_arr[j].audio.ops = &nu_spii2s_audio_ops;
  660. /* Register device, RW: it is with replay and record functions. */
  661. rt_audio_register(&g_nu_spii2s_arr[j].audio, g_nu_spii2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &g_nu_spii2s_arr[j]);
  662. }
  663. return RT_EOK;
  664. }
  665. INIT_DEVICE_EXPORT(rt_hw_spii2s_init);
  666. #endif //#if defined(BSP_USING_SPII2S)