nu_uart.h 61 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888
  1. /**************************************************************************//**
  2. * @file uart.h
  3. * @version V3.00
  4. * @brief NUC980 series UART driver header file
  5. *
  6. * SPDX-License-Identifier: Apache-2.0
  7. * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
  8. *****************************************************************************/
  9. #ifndef __NU_UART_H__
  10. #define __NU_UART_H__
  11. #include <stdio.h>
  12. #include <stdlib.h>
  13. #include <string.h>
  14. #include "nuc980.h"
  15. /** @addtogroup Standard_Driver Standard Driver
  16. @{
  17. */
  18. /** @addtogroup UART_Driver UART Driver
  19. @{
  20. */
  21. /** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
  22. @{
  23. */
  24. /*---------------------------------------------------------------------------------------------------------*/
  25. /* UART FIFO size constants definitions */
  26. /*---------------------------------------------------------------------------------------------------------*/
  27. #define UART0_FIFO_SIZE 16ul /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
  28. #define UART1_FIFO_SIZE 16ul /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
  29. #define UART2_FIFO_SIZE 16ul /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
  30. #define UART3_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
  31. #define UART4_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
  32. #define UART5_FIFO_SIZE 16ul /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */
  33. /*---------------------------------------------------------------------------------------------------------*/
  34. /* UART_FIFO constants definitions */
  35. /*---------------------------------------------------------------------------------------------------------*/
  36. #define UART_FIFO_RFITL_1BYTE (0x0ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte \hideinitializer */
  37. #define UART_FIFO_RFITL_4BYTES (0x1ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes \hideinitializer */
  38. #define UART_FIFO_RFITL_8BYTES (0x2ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes \hideinitializer */
  39. #define UART_FIFO_RFITL_14BYTES (0x3ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes \hideinitializer */
  40. #define UART_FIFO_RTSTRGLV_1BYTE (0x0ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte \hideinitializer */
  41. #define UART_FIFO_RTSTRGLV_4BYTES (0x1ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes \hideinitializer */
  42. #define UART_FIFO_RTSTRGLV_8BYTES (0x2ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes \hideinitializer */
  43. #define UART_FIFO_RTSTRGLV_14BYTES (0x3ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes \hideinitializer */
  44. /*---------------------------------------------------------------------------------------------------------*/
  45. /* UART_LINE constants definitions */
  46. /*---------------------------------------------------------------------------------------------------------*/
  47. #define UART_WORD_LEN_5 (0ul) /*!< UART_LINE setting to set UART word length to 5 bits \hideinitializer */
  48. #define UART_WORD_LEN_6 (1ul) /*!< UART_LINE setting to set UART word length to 6 bits \hideinitializer */
  49. #define UART_WORD_LEN_7 (2ul) /*!< UART_LINE setting to set UART word length to 7 bits \hideinitializer */
  50. #define UART_WORD_LEN_8 (3ul) /*!< UART_LINE setting to set UART word length to 8 bits \hideinitializer */
  51. #define UART_PARITY_NONE (0x0ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity \hideinitializer */
  52. #define UART_PARITY_ODD (0x1ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity \hideinitializer */
  53. #define UART_PARITY_EVEN (0x3ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity \hideinitializer */
  54. #define UART_PARITY_MARK (0x5ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' \hideinitializer */
  55. #define UART_PARITY_SPACE (0x7ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' \hideinitializer */
  56. #define UART_STOP_BIT_1 (0x0ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit \hideinitializer */
  57. #define UART_STOP_BIT_1_5 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length \hideinitializer */
  58. #define UART_STOP_BIT_2 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length \hideinitializer */
  59. /*---------------------------------------------------------------------------------------------------------*/
  60. /* UART RTS ACTIVE LEVEL constants definitions */
  61. /*---------------------------------------------------------------------------------------------------------*/
  62. #define UART_RTS_IS_LOW_LEV_ACTIVE (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active \hideinitializer */
  63. #define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active \hideinitializer */
  64. /*---------------------------------------------------------------------------------------------------------*/
  65. /* UART_IRDA constants definitions */
  66. /*---------------------------------------------------------------------------------------------------------*/
  67. #define UART_IRDA_TXEN (0x1ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode \hideinitializer */
  68. #define UART_IRDA_RXEN (0x0ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode \hideinitializer */
  69. /*---------------------------------------------------------------------------------------------------------*/
  70. /* UART_FUNCSEL constants definitions */
  71. /*---------------------------------------------------------------------------------------------------------*/
  72. #define UART_FUNCSEL_UART (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) \hideinitializer */
  73. #define UART_FUNCSEL_LIN (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function \hideinitializer */
  74. #define UART_FUNCSEL_IrDA (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function \hideinitializer */
  75. #define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function \hideinitializer */
  76. /*---------------------------------------------------------------------------------------------------------*/
  77. /* UART_LINCTL constants definitions */
  78. /*---------------------------------------------------------------------------------------------------------*/
  79. #define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 \hideinitializer */
  80. #define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 \hideinitializer */
  81. #define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field \hideinitializer */
  82. #define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field \hideinitializer */
  83. #define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field \hideinitializer */
  84. #define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value \hideinitializer */
  85. /*---------------------------------------------------------------------------------------------------------*/
  86. /* UART BAUDRATE MODE constants definitions */
  87. /*---------------------------------------------------------------------------------------------------------*/
  88. #define UART_BAUD_MODE0 (0ul) /*!< Set UART Baudrate Mode is Mode0 \hideinitializer */
  89. #define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 \hideinitializer */
  90. /*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
  91. typedef struct
  92. {
  93. __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */
  94. __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */
  95. __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */
  96. __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */
  97. __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */
  98. __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */
  99. __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */
  100. __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */
  101. __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */
  102. __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */
  103. __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */
  104. __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */
  105. __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */
  106. __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */
  107. __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */
  108. __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */
  109. __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */
  110. __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */
  111. __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */
  112. } UART_T;
  113. #define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
  114. #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
  115. #define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */
  116. #define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */
  117. #define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
  118. #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
  119. #define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
  120. #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
  121. #define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
  122. #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
  123. #define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
  124. #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
  125. #define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
  126. #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
  127. #define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
  128. #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
  129. #define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */
  130. #define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */
  131. #define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
  132. #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
  133. #define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
  134. #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
  135. #define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
  136. #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
  137. #define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
  138. #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
  139. #define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
  140. #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
  141. #define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
  142. #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
  143. #define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
  144. #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
  145. #define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */
  146. #define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */
  147. #define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
  148. #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
  149. #define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
  150. #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
  151. #define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
  152. #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
  153. #define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
  154. #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
  155. #define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
  156. #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
  157. #define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
  158. #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
  159. #define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
  160. #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
  161. #define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
  162. #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
  163. #define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
  164. #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
  165. #define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
  166. #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
  167. #define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
  168. #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
  169. #define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */
  170. #define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */
  171. #define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */
  172. #define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */
  173. #define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */
  174. #define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */
  175. #define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
  176. #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
  177. #define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
  178. #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
  179. #define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
  180. #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
  181. #define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
  182. #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
  183. #define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
  184. #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
  185. #define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
  186. #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
  187. #define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
  188. #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
  189. #define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
  190. #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
  191. #define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
  192. #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
  193. #define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
  194. #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
  195. #define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
  196. #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
  197. #define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
  198. #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
  199. #define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
  200. #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
  201. #define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
  202. #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
  203. #define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
  204. #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
  205. #define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
  206. #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
  207. #define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
  208. #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
  209. #define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
  210. #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
  211. #define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
  212. #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
  213. #define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
  214. #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
  215. #define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
  216. #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
  217. #define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */
  218. #define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */
  219. #define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */
  220. #define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */
  221. #define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
  222. #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
  223. #define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
  224. #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
  225. #define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
  226. #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
  227. #define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
  228. #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
  229. #define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
  230. #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
  231. #define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
  232. #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
  233. #define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
  234. #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
  235. #define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
  236. #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
  237. #define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
  238. #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
  239. #define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
  240. #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
  241. #define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
  242. #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
  243. #define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
  244. #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
  245. #define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
  246. #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
  247. #define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
  248. #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
  249. #define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */
  250. #define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */
  251. #define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
  252. #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
  253. #define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
  254. #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
  255. #define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
  256. #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
  257. #define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
  258. #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
  259. #define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
  260. #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
  261. #define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */
  262. #define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */
  263. #define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
  264. #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
  265. #define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
  266. #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
  267. #define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
  268. #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
  269. #define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
  270. #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
  271. #define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */
  272. #define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */
  273. #define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */
  274. #define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */
  275. #define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
  276. #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
  277. #define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
  278. #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
  279. #define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
  280. #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
  281. #define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
  282. #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
  283. #define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
  284. #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
  285. #define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
  286. #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
  287. #define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
  288. #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
  289. #define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
  290. #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
  291. #define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
  292. #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
  293. #define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
  294. #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
  295. #define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
  296. #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
  297. #define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
  298. #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
  299. #define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
  300. #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
  301. #define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
  302. #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
  303. #define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
  304. #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
  305. #define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
  306. #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
  307. #define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
  308. #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
  309. #define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
  310. #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
  311. #define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
  312. #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
  313. #define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
  314. #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
  315. #define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
  316. #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
  317. #define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */
  318. #define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */
  319. #define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
  320. #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
  321. #define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
  322. #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
  323. #define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
  324. #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
  325. #define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
  326. #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
  327. #define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
  328. #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
  329. #define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
  330. #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
  331. #define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
  332. #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
  333. #define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
  334. #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
  335. #define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */
  336. #define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */
  337. #define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
  338. #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
  339. #define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
  340. #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
  341. #define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
  342. #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
  343. #define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
  344. #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
  345. #define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
  346. #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
  347. #define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
  348. #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
  349. #define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
  350. #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
  351. #define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
  352. #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
  353. #define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
  354. #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
  355. #define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
  356. #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
  357. #define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
  358. #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
  359. #define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */
  360. #define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */
  361. #define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */
  362. #define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */
  363. #define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */
  364. #define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */
  365. #define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */
  366. #define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */
  367. #define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */
  368. #define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */
  369. #define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */
  370. #define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */
  371. #define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */
  372. #define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */
  373. #define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */
  374. #define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */
  375. #define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */
  376. #define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */
  377. #define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */
  378. #define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */
  379. #define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */
  380. #define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */
  381. #define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */
  382. #define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */
  383. #define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */
  384. #define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */
  385. #define UART0 ((UART_T *) UART0_BA)
  386. #define UART1 ((UART_T *) UART1_BA)
  387. #define UART2 ((UART_T *) UART2_BA)
  388. #define UART3 ((UART_T *) UART3_BA)
  389. #define UART4 ((UART_T *) UART4_BA)
  390. #define UART5 ((UART_T *) UART5_BA)
  391. #define UART6 ((UART_T *) UART6_BA)
  392. #define UART7 ((UART_T *) UART7_BA)
  393. #define UART8 ((UART_T *) UART8_BA)
  394. #define UART9 ((UART_T *) UART9_BA)
  395. /** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
  396. @{
  397. */
  398. /**
  399. * @brief Calculate UART baudrate mode0 divider
  400. *
  401. * @param[in] u32SrcFreq UART clock frequency
  402. * @param[in] u32BaudRate Baudrate of UART module
  403. *
  404. * @return UART baudrate mode0 divider
  405. *
  406. * @details This macro calculate UART baudrate mode0 divider.
  407. * \hideinitializer
  408. */
  409. #define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul)
  410. /**
  411. * @brief Calculate UART baudrate mode2 divider
  412. *
  413. * @param[in] u32SrcFreq UART clock frequency
  414. * @param[in] u32BaudRate Baudrate of UART module
  415. *
  416. * @return UART baudrate mode2 divider
  417. *
  418. * @details This macro calculate UART baudrate mode2 divider.
  419. * \hideinitializer
  420. */
  421. #define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
  422. /**
  423. * @brief Write UART data
  424. *
  425. * @param[in] uart The pointer of the specified UART module
  426. * @param[in] u8Data Data byte to transmit.
  427. *
  428. * @return None
  429. *
  430. * @details This macro write Data to Tx data register.
  431. * \hideinitializer
  432. */
  433. #define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
  434. /**
  435. * @brief Read UART data
  436. *
  437. * @param[in] uart The pointer of the specified UART module
  438. *
  439. * @return The oldest data byte in RX FIFO.
  440. *
  441. * @details This macro read Rx data register.
  442. * \hideinitializer
  443. */
  444. #define UART_READ(uart) ((uart)->DAT)
  445. /**
  446. * @brief Get Tx empty
  447. *
  448. * @param[in] uart The pointer of the specified UART module
  449. *
  450. * @retval 0 Tx FIFO is not empty
  451. * @retval >=1 Tx FIFO is empty
  452. *
  453. * @details This macro get Transmitter FIFO empty register value.
  454. * \hideinitializer
  455. */
  456. #define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
  457. /**
  458. * @brief Get Rx empty
  459. *
  460. * @param[in] uart The pointer of the specified UART module
  461. *
  462. * @retval 0 Rx FIFO is not empty
  463. * @retval >=1 Rx FIFO is empty
  464. *
  465. * @details This macro get Receiver FIFO empty register value.
  466. * \hideinitializer
  467. */
  468. #define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
  469. /**
  470. * @brief Check specified UART port transmission is over.
  471. *
  472. * @param[in] uart The pointer of the specified UART module
  473. *
  474. * @retval 0 Tx transmission is not over
  475. * @retval 1 Tx transmission is over
  476. *
  477. * @details This macro return Transmitter Empty Flag register bit value.
  478. * It indicates if specified UART port transmission is over nor not.
  479. * \hideinitializer
  480. */
  481. #define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
  482. /**
  483. * @brief Wait specified UART port transmission is over
  484. *
  485. * @param[in] uart The pointer of the specified UART module
  486. *
  487. * @return None
  488. *
  489. * @details This macro wait specified UART port transmission is over.
  490. * \hideinitializer
  491. */
  492. #define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
  493. /**
  494. * @brief Check RX is ready or not
  495. *
  496. * @param[in] uart The pointer of the specified UART module
  497. *
  498. * @retval 0 The number of bytes in the RX FIFO is less than the RFITL
  499. * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
  500. *
  501. * @details This macro check receive data available interrupt flag is set or not.
  502. * \hideinitializer
  503. */
  504. #define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
  505. /**
  506. * @brief Check TX FIFO is full or not
  507. *
  508. * @param[in] uart The pointer of the specified UART module
  509. *
  510. * @retval 1 TX FIFO is full
  511. * @retval 0 TX FIFO is not full
  512. *
  513. * @details This macro check TX FIFO is full or not.
  514. * \hideinitializer
  515. */
  516. #define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
  517. /**
  518. * @brief Check RX FIFO is full or not
  519. *
  520. * @param[in] uart The pointer of the specified UART module
  521. *
  522. * @retval 1 RX FIFO is full
  523. * @retval 0 RX FIFO is not full
  524. *
  525. * @details This macro check RX FIFO is full or not.
  526. * \hideinitializer
  527. */
  528. #define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
  529. /**
  530. * @brief Get Tx full register value
  531. *
  532. * @param[in] uart The pointer of the specified UART module
  533. *
  534. * @retval 0 Tx FIFO is not full.
  535. * @retval >=1 Tx FIFO is full.
  536. *
  537. * @details This macro get Tx full register value.
  538. * \hideinitializer
  539. */
  540. #define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
  541. /**
  542. * @brief Get Rx full register value
  543. *
  544. * @param[in] uart The pointer of the specified UART module
  545. *
  546. * @retval 0 Rx FIFO is not full.
  547. * @retval >=1 Rx FIFO is full.
  548. *
  549. * @details This macro get Rx full register value.
  550. * \hideinitializer
  551. */
  552. #define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
  553. /**
  554. * @brief Enable specified UART interrupt
  555. *
  556. * @param[in] uart The pointer of the specified UART module
  557. * @param[in] u32eIntSel Interrupt type select
  558. * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
  559. * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
  560. * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
  561. * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
  562. * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
  563. * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
  564. * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
  565. * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
  566. * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
  567. *
  568. * @return None
  569. *
  570. * @details This macro enable specified UART interrupt.
  571. * \hideinitializer
  572. */
  573. #define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
  574. /**
  575. * @brief Disable specified UART interrupt
  576. *
  577. * @param[in] uart The pointer of the specified UART module
  578. * @param[in] u32eIntSel Interrupt type select
  579. * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
  580. * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt
  581. * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
  582. * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
  583. * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
  584. * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
  585. * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
  586. * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
  587. * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
  588. *
  589. * @return None
  590. *
  591. * @details This macro enable specified UART interrupt.
  592. * \hideinitializer
  593. */
  594. #define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
  595. /**
  596. * @brief Get specified interrupt flag/status
  597. *
  598. * @param[in] uart The pointer of the specified UART module
  599. * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
  600. * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
  601. * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator
  602. * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator
  603. * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator
  604. * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag
  605. * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag
  606. * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag
  607. * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag
  608. * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
  609. * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
  610. * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
  611. * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
  612. * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
  613. * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
  614. * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
  615. * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag
  616. * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
  617. * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
  618. * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
  619. * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
  620. * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
  621. * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
  622. *
  623. * @retval 0 The specified interrupt is not happened.
  624. * 1 The specified interrupt is happened.
  625. *
  626. * @details This macro get specified interrupt flag or interrupt indicator status.
  627. * \hideinitializer
  628. */
  629. #define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
  630. /**
  631. * @brief Clear RS-485 Address Byte Detection Flag
  632. *
  633. * @param[in] uart The pointer of the specified UART module
  634. *
  635. * @return None
  636. *
  637. * @details This macro clear RS-485 address byte detection flag.
  638. * \hideinitializer
  639. */
  640. #define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
  641. /**
  642. * @brief Get RS-485 Address Byte Detection Flag
  643. *
  644. * @param[in] uart The pointer of the specified UART module
  645. *
  646. * @retval 0 Receiver detects a data that is not an address bit.
  647. * @retval 1 Receiver detects a data that is an address bit.
  648. *
  649. * @details This macro get RS-485 address byte detection flag.
  650. * \hideinitializer
  651. */
  652. #define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
  653. /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
  654. void UART_CLEAR_RTS(UART_T *uart);
  655. void UART_SET_RTS(UART_T *uart);
  656. void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag);
  657. void UART_Close(UART_T *uart);
  658. void UART_DisableFlowCtrl(UART_T *uart);
  659. void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag);
  660. void UART_EnableFlowCtrl(UART_T *uart);
  661. void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag);
  662. void UART_Open(UART_T *uart, uint32_t u32baudrate);
  663. uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
  664. void UART_SetLineConfig(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
  665. void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC);
  666. void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction);
  667. void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr);
  668. void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength);
  669. uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
  670. /*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
  671. /*@}*/ /* end of group UART_Driver */
  672. /*@}*/ /* end of group Standard_Driver */
  673. #endif /*__NU_UART_H__*/
  674. /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/