drv_uart.c 23 KB

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  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2020-12-12 Wayne First version
  10. *
  11. ******************************************************************************/
  12. #include <rtconfig.h>
  13. #if defined(BSP_USING_UART)
  14. #include <rtdevice.h>
  15. #include <rthw.h>
  16. #include "NuMicro.h"
  17. #include <drv_uart.h>
  18. #include <drv_sys.h>
  19. #if defined(RT_SERIAL_USING_DMA)
  20. #include <drv_pdma.h>
  21. #endif
  22. /* Private define ---------------------------------------------------------------*/
  23. enum
  24. {
  25. UART_START = -1,
  26. #if defined(BSP_USING_UART0)
  27. UART0_IDX,
  28. #endif
  29. #if defined(BSP_USING_UART1)
  30. UART1_IDX,
  31. #endif
  32. #if defined(BSP_USING_UART2)
  33. UART2_IDX,
  34. #endif
  35. #if defined(BSP_USING_UART3)
  36. UART3_IDX,
  37. #endif
  38. #if defined(BSP_USING_UART4)
  39. UART4_IDX,
  40. #endif
  41. #if defined(BSP_USING_UART5)
  42. UART5_IDX,
  43. #endif
  44. #if defined(BSP_USING_UART6)
  45. UART6_IDX,
  46. #endif
  47. #if defined(BSP_USING_UART7)
  48. UART7_IDX,
  49. #endif
  50. #if defined(BSP_USING_UART8)
  51. UART8_IDX,
  52. #endif
  53. #if defined(BSP_USING_UART9)
  54. UART9_IDX,
  55. #endif
  56. UART_CNT
  57. };
  58. /* Private typedef --------------------------------------------------------------*/
  59. struct nu_uart
  60. {
  61. rt_serial_t dev;
  62. char *name;
  63. UART_T *uart_base;
  64. IRQn_Type irqn;
  65. E_SYS_IPRST rstidx;
  66. E_SYS_IPCLK clkidx;
  67. #if defined(RT_SERIAL_USING_DMA)
  68. uint32_t dma_flag;
  69. int16_t pdma_perp_tx;
  70. int8_t pdma_chanid_tx;
  71. int16_t pdma_perp_rx;
  72. int8_t pdma_chanid_rx;
  73. int32_t rx_write_offset;
  74. int32_t rxdma_trigger_len;
  75. nu_pdma_desc_t pdma_rx_desc;
  76. #endif
  77. };
  78. typedef struct nu_uart *nu_uart_t;
  79. /* Private functions ------------------------------------------------------------*/
  80. static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
  81. static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg);
  82. static int nu_uart_send(struct rt_serial_device *serial, char c);
  83. static int nu_uart_receive(struct rt_serial_device *serial);
  84. #if defined(RT_SERIAL_USING_DMA)
  85. static rt_ssize_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
  86. static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events);
  87. static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events);
  88. #endif
  89. /* Public functions ------------------------------------------------------------*/
  90. /* Private variables ------------------------------------------------------------*/
  91. static const struct rt_uart_ops nu_uart_ops =
  92. {
  93. .configure = nu_uart_configure,
  94. .control = nu_uart_control,
  95. .putc = nu_uart_send,
  96. .getc = nu_uart_receive,
  97. #if defined(RT_SERIAL_USING_DMA)
  98. .dma_transmit = nu_uart_dma_transmit
  99. #else
  100. .dma_transmit = RT_NULL
  101. #endif
  102. };
  103. static const struct serial_configure nu_uart_default_config =
  104. RT_SERIAL_CONFIG_DEFAULT;
  105. static struct nu_uart nu_uart_arr [] =
  106. {
  107. #if defined(BSP_USING_UART0)
  108. {
  109. .name = "uart0",
  110. .uart_base = UART0,
  111. .irqn = IRQ_UART0,
  112. .rstidx = UART0RST,
  113. .clkidx = UART0CKEN,
  114. #if defined(RT_SERIAL_USING_DMA)
  115. #if defined(BSP_USING_UART0_TX_DMA)
  116. .pdma_perp_tx = PDMA_UART0_TX,
  117. #else
  118. .pdma_perp_tx = NU_PDMA_UNUSED,
  119. #endif
  120. #if defined(BSP_USING_UART0_RX_DMA)
  121. .pdma_perp_rx = PDMA_UART0_RX,
  122. .rx_write_offset = 0,
  123. #else
  124. .pdma_perp_rx = NU_PDMA_UNUSED,
  125. #endif
  126. #endif
  127. },
  128. #endif
  129. #if defined(BSP_USING_UART1)
  130. {
  131. .name = "uart1",
  132. .uart_base = UART1,
  133. .irqn = IRQ_UART1,
  134. .rstidx = UART1RST,
  135. .clkidx = UART1CKEN,
  136. #if defined(RT_SERIAL_USING_DMA)
  137. #if defined(BSP_USING_UART1_TX_DMA)
  138. .pdma_perp_tx = PDMA_UART1_TX,
  139. #else
  140. .pdma_perp_tx = NU_PDMA_UNUSED,
  141. #endif
  142. #if defined(BSP_USING_UART1_RX_DMA)
  143. .pdma_perp_rx = PDMA_UART1_RX,
  144. .rx_write_offset = 0,
  145. #else
  146. .pdma_perp_rx = NU_PDMA_UNUSED,
  147. #endif
  148. #endif
  149. },
  150. #endif
  151. #if defined(BSP_USING_UART2)
  152. {
  153. .name = "uart2",
  154. .uart_base = UART2,
  155. .irqn = IRQ_UART2,
  156. .rstidx = UART2RST,
  157. .clkidx = UART2CKEN,
  158. #if defined(RT_SERIAL_USING_DMA)
  159. #if defined(BSP_USING_UART2_TX_DMA)
  160. .pdma_perp_tx = PDMA_UART2_TX,
  161. #else
  162. .pdma_perp_tx = NU_PDMA_UNUSED,
  163. #endif
  164. #if defined(BSP_USING_UART2_RX_DMA)
  165. .pdma_perp_rx = PDMA_UART2_RX,
  166. .rx_write_offset = 0,
  167. #else
  168. .pdma_perp_rx = NU_PDMA_UNUSED,
  169. #endif
  170. #endif
  171. },
  172. #endif
  173. #if defined(BSP_USING_UART3)
  174. {
  175. .name = "uart3",
  176. .uart_base = UART3,
  177. .irqn = IRQ_UART3,
  178. .rstidx = UART3RST,
  179. .clkidx = UART3CKEN,
  180. #if defined(RT_SERIAL_USING_DMA)
  181. #if defined(BSP_USING_UART3_TX_DMA)
  182. .pdma_perp_tx = PDMA_UART3_TX,
  183. #else
  184. .pdma_perp_tx = NU_PDMA_UNUSED,
  185. #endif
  186. #if defined(BSP_USING_UART3_RX_DMA)
  187. .pdma_perp_rx = PDMA_UART3_RX,
  188. .rx_write_offset = 0,
  189. #else
  190. .pdma_perp_rx = NU_PDMA_UNUSED,
  191. #endif
  192. #endif
  193. },
  194. #endif
  195. #if defined(BSP_USING_UART4)
  196. {
  197. .name = "uart4",
  198. .uart_base = UART4,
  199. .irqn = IRQ_UART4,
  200. .rstidx = UART4RST,
  201. .clkidx = UART4CKEN,
  202. #if defined(RT_SERIAL_USING_DMA)
  203. #if defined(BSP_USING_UART4_TX_DMA)
  204. .pdma_perp_tx = PDMA_UART4_TX,
  205. #else
  206. .pdma_perp_tx = NU_PDMA_UNUSED,
  207. #endif
  208. #if defined(BSP_USING_UART4_RX_DMA)
  209. .pdma_perp_rx = PDMA_UART4_RX,
  210. .rx_write_offset = 0,
  211. #else
  212. .pdma_perp_rx = NU_PDMA_UNUSED,
  213. #endif
  214. #endif
  215. },
  216. #endif
  217. #if defined(BSP_USING_UART5)
  218. {
  219. .name = "uart5",
  220. .uart_base = UART5,
  221. .irqn = IRQ_UART5,
  222. .rstidx = UART5RST,
  223. .clkidx = UART5CKEN,
  224. #if defined(RT_SERIAL_USING_DMA)
  225. #if defined(BSP_USING_UART5_TX_DMA)
  226. .pdma_perp_tx = PDMA_UART5_TX,
  227. #else
  228. .pdma_perp_tx = NU_PDMA_UNUSED,
  229. #endif
  230. #if defined(BSP_USING_UART5_RX_DMA)
  231. .pdma_perp_rx = PDMA_UART5_RX,
  232. .rx_write_offset = 0,
  233. #else
  234. .pdma_perp_rx = NU_PDMA_UNUSED,
  235. #endif
  236. #endif
  237. },
  238. #endif
  239. #if defined(BSP_USING_UART6)
  240. {
  241. .name = "uart6",
  242. .uart_base = UART6,
  243. .irqn = IRQ_UART6,
  244. .rstidx = UART6RST,
  245. .clkidx = UART6CKEN,
  246. #if defined(RT_SERIAL_USING_DMA)
  247. #if defined(BSP_USING_UART6_TX_DMA)
  248. .pdma_perp_tx = PDMA_UART6_TX,
  249. #else
  250. .pdma_perp_tx = NU_PDMA_UNUSED,
  251. #endif
  252. #if defined(BSP_USING_UART6_RX_DMA)
  253. .pdma_perp_rx = PDMA_UART6_RX,
  254. .rx_write_offset = 0,
  255. #else
  256. .pdma_perp_rx = NU_PDMA_UNUSED,
  257. #endif
  258. #endif
  259. },
  260. #endif
  261. #if defined(BSP_USING_UART7)
  262. {
  263. .name = "uart7",
  264. .uart_base = UART7,
  265. .irqn = IRQ_UART7,
  266. .rstidx = UART7RST,
  267. .clkidx = UART7CKEN,
  268. #if defined(RT_SERIAL_USING_DMA)
  269. #if defined(BSP_USING_UART7_TX_DMA)
  270. .pdma_perp_tx = PDMA_UART7_TX,
  271. #else
  272. .pdma_perp_tx = NU_PDMA_UNUSED,
  273. #endif
  274. #if defined(BSP_USING_UART7_RX_DMA)
  275. .pdma_perp_rx = PDMA_UART7_RX,
  276. .rx_write_offset = 0,
  277. #else
  278. .pdma_perp_rx = NU_PDMA_UNUSED,
  279. #endif
  280. #endif
  281. },
  282. #endif
  283. #if defined(BSP_USING_UART8)
  284. {
  285. .name = "uart8",
  286. .uart_base = UART8,
  287. .irqn = IRQ_UART8,
  288. .rstidx = UART8RST,
  289. .clkidx = UART8CKEN,
  290. #if defined(RT_SERIAL_USING_DMA)
  291. #if defined(BSP_USING_UART8_TX_DMA)
  292. .pdma_perp_tx = PDMA_UART8_TX,
  293. #else
  294. .pdma_perp_tx = NU_PDMA_UNUSED,
  295. #endif
  296. #if defined(BSP_USING_UART8_RX_DMA)
  297. .pdma_perp_rx = PDMA_UART8_RX,
  298. .rx_write_offset = 0,
  299. #else
  300. .pdma_perp_rx = NU_PDMA_UNUSED,
  301. #endif
  302. #endif
  303. },
  304. #endif
  305. #if defined(BSP_USING_UART9)
  306. {
  307. .name = "uart9",
  308. .uart_base = UART9,
  309. .irqn = IRQ_UART9,
  310. .rstidx = UART9RST,
  311. .clkidx = UART9CKEN,
  312. #if defined(RT_SERIAL_USING_DMA)
  313. #if defined(BSP_USING_UART9_TX_DMA)
  314. .pdma_perp_tx = PDMA_UART9_TX,
  315. #else
  316. .pdma_perp_tx = NU_PDMA_UNUSED,
  317. #endif
  318. #if defined(BSP_USING_UART9_RX_DMA)
  319. .pdma_perp_rx = PDMA_UART9_RX,
  320. .rx_write_offset = 0,
  321. #else
  322. .pdma_perp_rx = NU_PDMA_UNUSED,
  323. #endif
  324. #endif
  325. },
  326. #endif
  327. }; /* uart nu_uart */
  328. /**
  329. * All UART interrupt service routine
  330. */
  331. static void nu_uart_isr(int vector, void *param)
  332. {
  333. /* Get base address of uart register */
  334. nu_uart_t serial = (nu_uart_t)param;
  335. UART_T *uart_base = serial->uart_base;
  336. /* Get interrupt event */
  337. uint32_t u32IntSts = uart_base->INTSTS;
  338. uint32_t u32FIFOSts = uart_base->FIFOSTS;
  339. #if defined(RT_SERIAL_USING_DMA)
  340. if (u32IntSts & UART_INTSTS_HWRLSIF_Msk)
  341. {
  342. /* Drain RX FIFO to remove remain FEF frames in FIFO. */
  343. uart_base->FIFO |= UART_FIFO_RXRST_Msk;
  344. uart_base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk);
  345. return;
  346. }
  347. #endif
  348. /* Handle RX event */
  349. if (u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk))
  350. {
  351. rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
  352. }
  353. uart_base->INTSTS = u32IntSts;
  354. uart_base->FIFOSTS = u32FIFOSts;
  355. }
  356. /**
  357. * Set RS-485 AUD mode
  358. */
  359. void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel)
  360. {
  361. UART_T *uart_base;
  362. RT_ASSERT(serial);
  363. /* Get base address of uart register */
  364. uart_base = ((nu_uart_t)serial)->uart_base;
  365. /* Set RTS as RS-485 phy direction controlling ping. */
  366. UART_SelectRS485Mode(uart_base, UART_ALTCTL_RS485AUD_Msk, 0);
  367. if (bRTSActiveLowLevel)
  368. {
  369. /* Set direction pin as active-low. */
  370. uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
  371. }
  372. else
  373. {
  374. /* Set direction pin as active-high. */
  375. uart_base->MODEM &= ~UART_MODEM_RTSACTLV_Msk;
  376. }
  377. rt_kprintf("Set %s to RS-485 AUD function mode. ActiveLowLevel-%s\n", ((nu_uart_t)serial)->name, bRTSActiveLowLevel ? "YES" : "NO");
  378. }
  379. /**
  380. * Configure uart port
  381. */
  382. static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  383. {
  384. rt_err_t ret = RT_EOK;
  385. uint32_t uart_word_len = 0;
  386. uint32_t uart_stop_bit = 0;
  387. uint32_t uart_parity = 0;
  388. RT_ASSERT(serial);
  389. RT_ASSERT(cfg);
  390. /* Check baudrate */
  391. RT_ASSERT(cfg->baud_rate != 0);
  392. /* Get base address of uart register */
  393. UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
  394. /* Check word len */
  395. switch (cfg->data_bits)
  396. {
  397. case DATA_BITS_5:
  398. uart_word_len = UART_WORD_LEN_5;
  399. break;
  400. case DATA_BITS_6:
  401. uart_word_len = UART_WORD_LEN_6;
  402. break;
  403. case DATA_BITS_7:
  404. uart_word_len = UART_WORD_LEN_7;
  405. break;
  406. case DATA_BITS_8:
  407. uart_word_len = UART_WORD_LEN_8;
  408. break;
  409. default:
  410. rt_kprintf("Unsupported data length\n");
  411. ret = -RT_EINVAL;
  412. goto exit_nu_uart_configure;
  413. }
  414. /* Check stop bit */
  415. switch (cfg->stop_bits)
  416. {
  417. case STOP_BITS_1:
  418. uart_stop_bit = UART_STOP_BIT_1;
  419. break;
  420. case STOP_BITS_2:
  421. uart_stop_bit = UART_STOP_BIT_2;
  422. break;
  423. default:
  424. rt_kprintf("Unsupported stop bit\n");
  425. ret = -RT_EINVAL;
  426. goto exit_nu_uart_configure;
  427. }
  428. /* Check parity */
  429. switch (cfg->parity)
  430. {
  431. case PARITY_NONE:
  432. uart_parity = UART_PARITY_NONE;
  433. break;
  434. case PARITY_ODD:
  435. uart_parity = UART_PARITY_ODD;
  436. break;
  437. case PARITY_EVEN:
  438. uart_parity = UART_PARITY_EVEN;
  439. break;
  440. default:
  441. rt_kprintf("Unsupported parity\n");
  442. ret = -RT_EINVAL;
  443. goto exit_nu_uart_configure;
  444. }
  445. nu_sys_ip_reset(((nu_uart_t)serial)->rstidx);
  446. /* Open Uart and set UART Baudrate */
  447. UART_Open(uart_base, cfg->baud_rate);
  448. /* Set line configuration. */
  449. UART_SetLineConfig(uart_base, 0, uart_word_len, uart_parity, uart_stop_bit);
  450. /* Enable interrupt. */
  451. rt_hw_interrupt_umask(((nu_uart_t)serial)->irqn);
  452. exit_nu_uart_configure:
  453. if (ret != RT_EOK)
  454. UART_Close(uart_base);
  455. return -(ret);
  456. }
  457. #if defined(RT_SERIAL_USING_DMA)
  458. static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen)
  459. {
  460. rt_err_t result = RT_EOK;
  461. struct nu_pdma_chn_cb sChnCB;
  462. nu_uart_t psNuUart = (nu_uart_t)serial;
  463. /* Get base address of uart register */
  464. UART_T *uart_base = psNuUart->uart_base;
  465. /* Register ISR callback function */
  466. sChnCB.m_eCBType = eCBType_Event;
  467. sChnCB.m_pfnCBHandler = nu_pdma_uart_rx_cb;
  468. sChnCB.m_pvUserData = (void *)serial;
  469. nu_pdma_filtering_set(psNuUart->pdma_chanid_rx, NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
  470. result = nu_pdma_callback_register(psNuUart->pdma_chanid_rx, &sChnCB);
  471. if (result != RT_EOK)
  472. {
  473. goto exit_nu_pdma_uart_rx_config;
  474. }
  475. if (serial->config.bufsz == 0)
  476. {
  477. result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_rx,
  478. 8,
  479. (uint32_t)uart_base,
  480. (uint32_t)pu8Buf,
  481. i32TriggerLen,
  482. 1000); //Idle-timeout, 1ms
  483. if (result != RT_EOK)
  484. {
  485. goto exit_nu_pdma_uart_rx_config;
  486. }
  487. }
  488. else
  489. {
  490. /* For Serial RX FIFO - Single buffer recycle SG trigger */
  491. /* Link to next */
  492. nu_pdma_desc_t next = psNuUart->pdma_rx_desc;
  493. result = nu_pdma_desc_setup(psNuUart->pdma_chanid_rx,
  494. psNuUart->pdma_rx_desc,
  495. 8,
  496. (uint32_t)uart_base,
  497. (uint32_t)pu8Buf,
  498. i32TriggerLen,
  499. next,
  500. 0);
  501. if (result != RT_EOK)
  502. {
  503. goto exit_nu_pdma_uart_rx_config;
  504. }
  505. /* Assign head descriptor & go */
  506. result = nu_pdma_sg_transfer(psNuUart->pdma_chanid_rx, psNuUart->pdma_rx_desc, 1000);
  507. if (result != RT_EOK)
  508. {
  509. goto exit_nu_pdma_uart_rx_config;
  510. }
  511. }
  512. /* Enable Receive Line interrupt & Start DMA RX transfer. */
  513. UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
  514. exit_nu_pdma_uart_rx_config:
  515. return result;
  516. }
  517. static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
  518. {
  519. rt_size_t recv_len = 0;
  520. rt_size_t transferred_rxbyte = 0;
  521. struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
  522. nu_uart_t puart = (nu_uart_t)serial;
  523. RT_ASSERT(serial);
  524. /* Get base address of uart register */
  525. UART_T *uart_base = puart->uart_base;
  526. transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len);
  527. if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
  528. {
  529. if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
  530. {
  531. transferred_rxbyte = puart->rxdma_trigger_len;
  532. }
  533. else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UART_GET_RX_EMPTY(uart_base))
  534. {
  535. return;
  536. }
  537. recv_len = transferred_rxbyte - puart->rx_write_offset;
  538. if (recv_len > 0)
  539. {
  540. #if defined(BSP_USING_MMU)
  541. struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  542. mmu_invalidate_dcache((uint32_t)&rx_fifo->buffer[puart->rx_write_offset], recv_len);
  543. #endif
  544. puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
  545. }
  546. }
  547. if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
  548. {
  549. recv_len = puart->rxdma_trigger_len;
  550. }
  551. if (recv_len > 0)
  552. {
  553. rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  554. }
  555. }
  556. static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial)
  557. {
  558. struct nu_pdma_chn_cb sChnCB;
  559. RT_ASSERT(serial);
  560. /* Register ISR callback function */
  561. sChnCB.m_eCBType = eCBType_Event;
  562. sChnCB.m_pfnCBHandler = nu_pdma_uart_tx_cb;
  563. sChnCB.m_pvUserData = (void *)serial;
  564. nu_pdma_filtering_set(((nu_uart_t)serial)->pdma_chanid_tx, NU_PDMA_EVENT_TRANSFER_DONE);
  565. return nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx, &sChnCB);
  566. }
  567. static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
  568. {
  569. nu_uart_t puart = (nu_uart_t)pvOwner;
  570. RT_ASSERT(puart);
  571. UART_DISABLE_INT(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
  572. if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
  573. {
  574. rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_TX_DMADONE);
  575. }
  576. }
  577. /**
  578. * Uart DMA transfer
  579. */
  580. static rt_ssize_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  581. {
  582. rt_err_t result = RT_EOK;
  583. nu_uart_t psNuUart = (nu_uart_t)serial;
  584. RT_ASSERT(serial);
  585. RT_ASSERT(buf);
  586. /* Get base address of uart register */
  587. UART_T *uart_base = psNuUart->uart_base;
  588. if (direction == RT_SERIAL_DMA_TX)
  589. {
  590. result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
  591. 8,
  592. (uint32_t)buf,
  593. (uint32_t)uart_base,
  594. size,
  595. 0); // wait-forever
  596. // Start DMA TX transfer
  597. UART_ENABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
  598. }
  599. else if (direction == RT_SERIAL_DMA_RX)
  600. {
  601. UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
  602. // If config.bufsz = 0, serial will trigger once.
  603. psNuUart->rxdma_trigger_len = size;
  604. psNuUart->rx_write_offset = 0;
  605. result = nu_pdma_uart_rx_config(serial, buf, size);
  606. }
  607. else
  608. {
  609. result = -RT_ERROR;
  610. }
  611. return result;
  612. }
  613. static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
  614. {
  615. RT_ASSERT(pusrt);
  616. /* Allocate UART_TX nu_dma channel */
  617. if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
  618. {
  619. pusrt->pdma_chanid_tx = nu_pdma_channel_allocate(pusrt->pdma_perp_tx);
  620. if (pusrt->pdma_chanid_tx >= 0)
  621. {
  622. pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  623. }
  624. }
  625. /* Allocate UART_RX nu_dma channel */
  626. if (pusrt->pdma_perp_rx != NU_PDMA_UNUSED)
  627. {
  628. pusrt->pdma_chanid_rx = nu_pdma_channel_allocate(pusrt->pdma_perp_rx);
  629. if (pusrt->pdma_chanid_rx >= 0)
  630. {
  631. rt_err_t ret = RT_EOK;
  632. pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  633. ret = nu_pdma_sgtbls_allocate(&pusrt->pdma_rx_desc, 1);
  634. RT_ASSERT(ret == RT_EOK);
  635. }
  636. }
  637. return RT_EOK;
  638. }
  639. #endif
  640. /**
  641. * Uart interrupt control
  642. */
  643. static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  644. {
  645. nu_uart_t psNuUart = (nu_uart_t)serial;
  646. rt_err_t result = RT_EOK;
  647. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  648. RT_ASSERT(serial);
  649. /* Get base address of uart register */
  650. UART_T *uart_base = psNuUart->uart_base;
  651. switch (cmd)
  652. {
  653. case RT_DEVICE_CTRL_CLR_INT:
  654. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
  655. {
  656. UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
  657. }
  658. else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
  659. {
  660. /* Disable Receive Line interrupt & Stop DMA RX transfer. */
  661. #if defined(RT_SERIAL_USING_DMA)
  662. if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
  663. {
  664. nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
  665. }
  666. UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
  667. #endif
  668. }
  669. break;
  670. case RT_DEVICE_CTRL_SET_INT:
  671. if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
  672. {
  673. UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
  674. }
  675. break;
  676. #if defined(RT_SERIAL_USING_DMA)
  677. case RT_DEVICE_CTRL_CONFIG:
  678. if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
  679. {
  680. struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
  681. psNuUart->rxdma_trigger_len = serial->config.bufsz;
  682. psNuUart->rx_write_offset = 0;
  683. result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len); // Config & trigger
  684. }
  685. else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
  686. {
  687. result = nu_pdma_uart_tx_config(serial);
  688. }
  689. break;
  690. #endif
  691. case RT_DEVICE_CTRL_CLOSE:
  692. /* Disable interrupt. */
  693. rt_hw_interrupt_mask(psNuUart->irqn);
  694. #if defined(RT_SERIAL_USING_DMA)
  695. UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
  696. UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
  697. if (psNuUart->dma_flag != 0)
  698. {
  699. nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
  700. nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
  701. }
  702. #endif
  703. /* Close UART port */
  704. UART_Close(uart_base);
  705. break;
  706. default:
  707. result = -RT_EINVAL;
  708. break;
  709. }
  710. return result;
  711. }
  712. /**
  713. * Uart put char
  714. */
  715. static int nu_uart_send(struct rt_serial_device *serial, char c)
  716. {
  717. RT_ASSERT(serial);
  718. /* Get base address of uart register */
  719. UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
  720. /* Waiting if TX-FIFO is full. */
  721. while (UART_IS_TX_FULL(uart_base));
  722. /* Put char into TX-FIFO */
  723. UART_WRITE(uart_base, c);
  724. return 1;
  725. }
  726. /**
  727. * Uart get char
  728. */
  729. static int nu_uart_receive(struct rt_serial_device *serial)
  730. {
  731. RT_ASSERT(serial);
  732. /* Get base address of uart register */
  733. UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
  734. /* Return failure if RX-FIFO is empty. */
  735. if (UART_GET_RX_EMPTY(uart_base))
  736. {
  737. return -1;
  738. }
  739. /* Get char from RX-FIFO */
  740. return UART_READ(uart_base);
  741. }
  742. /**
  743. * Hardware UART Initialization
  744. */
  745. rt_err_t rt_hw_uart_init(void)
  746. {
  747. int i;
  748. rt_uint32_t flag;
  749. rt_err_t ret = RT_EOK;
  750. for (i = (UART_START + 1); i < UART_CNT; i++)
  751. {
  752. flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
  753. nu_uart_arr[i].dev.ops = &nu_uart_ops;
  754. nu_uart_arr[i].dev.config = nu_uart_default_config;
  755. #if defined(RT_SERIAL_USING_DMA)
  756. nu_uart_arr[i].dma_flag = 0;
  757. nu_hw_uart_dma_allocate(&nu_uart_arr[i]);
  758. flag |= nu_uart_arr[i].dma_flag;
  759. #endif
  760. rt_hw_interrupt_install(nu_uart_arr[i].irqn, nu_uart_isr, &nu_uart_arr[i], nu_uart_arr[i].name);
  761. nu_sys_ipclk_enable(nu_uart_arr[i].clkidx);
  762. ret = rt_hw_serial_register(&nu_uart_arr[i].dev, nu_uart_arr[i].name, flag, NULL);
  763. RT_ASSERT(ret == RT_EOK);
  764. }
  765. return ret;
  766. }
  767. #endif //#if defined(BSP_USING_UART)