drv_sci_spi.c 12 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-23 Mr.Tiger first version
  9. * 2021-11-04 Sherman ADD complete_event
  10. * 2022-12-7 Vandoul ADD sci spi
  11. */
  12. /**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
  13. #include "drv_sci_spi.h"
  14. #ifdef RT_USING_SPI
  15. //#define DRV_DEBUG
  16. #define DBG_TAG "drv.scispi"
  17. #ifdef DRV_DEBUG
  18. #define DBG_LVL DBG_LOG
  19. #else
  20. #define DBG_LVL DBG_INFO
  21. #endif /* DRV_DEBUG */
  22. #include <rtdbg.h>
  23. #ifdef R_SCI_B_SPI_H
  24. #define R_SCI_SPI_Write R_SCI_B_SPI_Write
  25. #define R_SCI_SPI_Read R_SCI_B_SPI_Read
  26. #define R_SCI_SPI_WriteRead R_SCI_B_SPI_WriteRead
  27. #define R_SCI_SPI_Open R_SCI_B_SPI_Open
  28. #define R_SCI_SPI_Close R_SCI_B_SPI_Close
  29. #endif
  30. #define RA_SCI_SPI0_EVENT 0x0001
  31. #define RA_SCI_SPI1_EVENT 0x0002
  32. #define RA_SCI_SPI2_EVENT 0x0004
  33. #define RA_SCI_SPI3_EVENT 0x0008
  34. #define RA_SCI_SPI4_EVENT 0x0010
  35. #define RA_SCI_SPI5_EVENT 0x0020
  36. #define RA_SCI_SPI6_EVENT 0x0040
  37. #define RA_SCI_SPI7_EVENT 0x0080
  38. #define RA_SCI_SPI8_EVENT 0x0100
  39. #define RA_SCI_SPI9_EVENT 0x0200
  40. static struct rt_event complete_event = {0};
  41. static struct ra_sci_spi_handle spi_handle[] =
  42. {
  43. #ifdef BSP_USING_SCI_SPI0
  44. {.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,},
  45. #endif
  46. #ifdef BSP_USING_SCI_SPI1
  47. {.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,},
  48. #endif
  49. #ifdef BSP_USING_SCI_SPI2
  50. {.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,},
  51. #endif
  52. #ifdef BSP_USING_SCI_SPI3
  53. {.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,},
  54. #endif
  55. #ifdef BSP_USING_SCI_SPI4
  56. {.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,},
  57. #endif
  58. #ifdef BSP_USING_SCI_SPI5
  59. {.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,},
  60. #endif
  61. #ifdef BSP_USING_SCI_SPI6
  62. {.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,},
  63. #endif
  64. #ifdef BSP_USING_SCI_SPI7
  65. {.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,},
  66. #endif
  67. #ifdef BSP_USING_SCI_SPI8
  68. {.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,},
  69. #endif
  70. #ifdef BSP_USING_SCI_SPI9
  71. {.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,},
  72. #endif
  73. };
  74. static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
  75. #define SCI_SPIx_CALLBACK(n) \
  76. void sci_spi##n##_callback(spi_callback_args_t *p_args) \
  77. { \
  78. rt_interrupt_enter(); \
  79. if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \
  80. { \
  81. rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \
  82. } \
  83. rt_interrupt_leave(); \
  84. }
  85. SCI_SPIx_CALLBACK(0);
  86. SCI_SPIx_CALLBACK(1);
  87. SCI_SPIx_CALLBACK(2);
  88. SCI_SPIx_CALLBACK(3);
  89. SCI_SPIx_CALLBACK(4);
  90. SCI_SPIx_CALLBACK(5);
  91. SCI_SPIx_CALLBACK(6);
  92. SCI_SPIx_CALLBACK(7);
  93. SCI_SPIx_CALLBACK(8);
  94. SCI_SPIx_CALLBACK(9);
  95. #define SCI_SPIx_EVENT_RECV(n) \
  96. rt_event_recv(event, \
  97. RA_SCI_SPI##n##_EVENT, \
  98. RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \
  99. rt_tick_from_millisecond(1000), \
  100. &recved);
  101. static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
  102. {
  103. rt_uint32_t recved = 0x00;
  104. rt_err_t ret = RT_EOK;
  105. switch (bus_name[4])
  106. {
  107. case '0':
  108. ret = SCI_SPIx_EVENT_RECV(0);
  109. break;
  110. case '1':
  111. ret = SCI_SPIx_EVENT_RECV(1);
  112. break;
  113. case '2':
  114. ret = SCI_SPIx_EVENT_RECV(2);
  115. break;
  116. case '3':
  117. ret = SCI_SPIx_EVENT_RECV(3);
  118. break;
  119. case '4':
  120. ret = SCI_SPIx_EVENT_RECV(4);
  121. break;
  122. case '5':
  123. ret = SCI_SPIx_EVENT_RECV(5);
  124. break;
  125. case '6':
  126. ret = SCI_SPIx_EVENT_RECV(6);
  127. break;
  128. case '7':
  129. ret = SCI_SPIx_EVENT_RECV(7);
  130. break;
  131. case '8':
  132. ret = SCI_SPIx_EVENT_RECV(8);
  133. break;
  134. case '9':
  135. ret = SCI_SPIx_EVENT_RECV(9);
  136. break;
  137. default:
  138. break;
  139. }
  140. if (ret != RT_EOK)
  141. {
  142. LOG_D("%s ra_wait_complete failed!", bus_name);
  143. return ret;
  144. }
  145. return -RT_EINVAL;
  146. }
  147. static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
  148. {
  149. spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
  150. if(data_width == 1)
  151. bit_width = SPI_BIT_WIDTH_8_BITS;
  152. else if(data_width == 2)
  153. bit_width = SPI_BIT_WIDTH_16_BITS;
  154. else if(data_width == 4)
  155. bit_width = SPI_BIT_WIDTH_32_BITS;
  156. return bit_width;
  157. }
  158. static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
  159. {
  160. RT_ASSERT(device != NULL);
  161. RT_ASSERT(send_buf != NULL);
  162. RT_ASSERT(len > 0);
  163. rt_err_t err = RT_EOK;
  164. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  165. spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
  166. /**< send msessage */
  167. err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
  168. if (RT_EOK != err)
  169. {
  170. LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  171. return -RT_ERROR;
  172. }
  173. /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
  174. ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
  175. return len;
  176. }
  177. static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
  178. {
  179. RT_ASSERT(device != NULL);
  180. RT_ASSERT(recv_buf != NULL);
  181. RT_ASSERT(len > 0);
  182. rt_err_t err = RT_EOK;
  183. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  184. spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
  185. /**< receive message */
  186. err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
  187. if (RT_EOK != err)
  188. {
  189. LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  190. return -RT_ERROR;
  191. }
  192. /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
  193. ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
  194. return len;
  195. }
  196. static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
  197. {
  198. RT_ASSERT(device != NULL);
  199. RT_ASSERT(message != NULL);
  200. RT_ASSERT(message->length > 0);
  201. rt_err_t err = RT_EOK;
  202. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  203. spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
  204. /**< write and receive message */
  205. err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
  206. if (RT_EOK != err)
  207. {
  208. LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  209. return -RT_ERROR;
  210. }
  211. /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
  212. ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
  213. return message->length;
  214. }
  215. /**< init spi TODO : MSB does not support modification */
  216. static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
  217. struct rt_spi_configuration *configuration)
  218. {
  219. RT_ASSERT(device != NULL);
  220. RT_ASSERT(configuration != NULL);
  221. rt_err_t err = RT_EOK;
  222. struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
  223. /**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
  224. rt_uint8_t data_width = configuration->data_width / 8;
  225. RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
  226. configuration->data_width = configuration->data_width / 8;
  227. spi_dev->rt_spi_cfg_t = configuration;
  228. #ifdef R_SCI_B_SPI_H
  229. sci_b_spi_extended_cfg_t spi_cfg = *(sci_b_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
  230. #else
  231. sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
  232. #endif
  233. /**< Configure Select Line */
  234. rt_pin_write(device->cs_pin, PIN_HIGH);
  235. /**< config bitrate */
  236. #ifdef R_SCI_B_SPI_H
  237. R_SCI_B_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div);
  238. #else
  239. R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false);
  240. #endif
  241. /**< init */
  242. err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
  243. /* handle error */
  244. if(err == FSP_ERR_IN_USE) {
  245. R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t);
  246. err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
  247. }
  248. if (RT_EOK != err)
  249. {
  250. LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
  251. return -RT_ERROR;
  252. }
  253. return RT_EOK;
  254. }
  255. static rt_ssize_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  256. {
  257. RT_ASSERT(device != RT_NULL);
  258. RT_ASSERT(device->bus != RT_NULL);
  259. RT_ASSERT(message != RT_NULL);
  260. rt_err_t err = RT_EOK;
  261. if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  262. {
  263. if (device->config.mode & RT_SPI_CS_HIGH)
  264. rt_pin_write(device->cs_pin, PIN_HIGH);
  265. else
  266. rt_pin_write(device->cs_pin, PIN_LOW);
  267. }
  268. if (message->length > 0)
  269. {
  270. if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
  271. {
  272. /**< receive message */
  273. err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
  274. }
  275. else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
  276. {
  277. /**< send message */
  278. err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
  279. }
  280. else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
  281. {
  282. /**< send and receive message */
  283. err = ra_write_read_message(device, message);
  284. }
  285. }
  286. if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
  287. {
  288. if (device->config.mode & RT_SPI_CS_HIGH)
  289. rt_pin_write(device->cs_pin, PIN_LOW);
  290. else
  291. rt_pin_write(device->cs_pin, PIN_HIGH);
  292. }
  293. return err;
  294. }
  295. static const struct rt_spi_ops ra_spi_ops =
  296. {
  297. .configure = ra_hw_spi_configure,
  298. .xfer = ra_spixfer,
  299. };
  300. int ra_hw_sci_spi_init(void)
  301. {
  302. for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
  303. {
  304. spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
  305. /**< register spi bus */
  306. rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
  307. if (RT_EOK != err)
  308. {
  309. LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err);
  310. return -RT_ERROR;
  311. }
  312. }
  313. if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO))
  314. {
  315. LOG_E("SPI transfer event init fail!");
  316. return -RT_ERROR;
  317. }
  318. return RT_EOK;
  319. }
  320. INIT_BOARD_EXPORT(ra_hw_sci_spi_init);
  321. /**
  322. * Attach the spi device to SPI bus, this function must be used after initialization.
  323. */
  324. rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  325. {
  326. RT_ASSERT(bus_name != RT_NULL);
  327. RT_ASSERT(device_name != RT_NULL);
  328. rt_err_t result;
  329. struct rt_spi_device *spi_device;
  330. /* attach the device to spi bus*/
  331. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  332. RT_ASSERT(spi_device != RT_NULL);
  333. result = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
  334. if (result != RT_EOK)
  335. {
  336. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  337. }
  338. LOG_D("%s attach to %s done", device_name, bus_name);
  339. return result;
  340. }
  341. #endif /* RT_USING_SPI */