drv_spi.c 7.6 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-06-27 AHTYDHD the first version
  9. */
  10. #include "drv_spi.h"
  11. #include <stdint.h>
  12. #include <stdbool.h>
  13. #include "inc/hw_memmap.h"
  14. #include "driverlib/ssi.h"
  15. #include "driverlib/gpio.h"
  16. #include "driverlib/sysctl.h"
  17. #ifdef RT_USING_SPI
  18. #if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
  19. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  20. #include "tm4c123_config.h"
  21. #include "spi_config.h"
  22. #include <string.h>
  23. //#define DRV_DEBUG
  24. #define LOG_TAG "drv.spi"
  25. #include <drv_log.h>
  26. enum
  27. {
  28. #ifdef BSP_USING_SPI0
  29. SPI0_INDEX,
  30. #endif
  31. #ifdef BSP_USING_SPI1
  32. SPI1_INDEX,
  33. #endif
  34. #ifdef BSP_USING_SPI2
  35. SPI2_INDEX,
  36. #endif
  37. #ifdef BSP_USING_SPI3
  38. SPI3_INDEX,
  39. #endif
  40. };
  41. static struct tm4c123_spi_config spi_config[] =
  42. {
  43. #ifdef BSP_USING_SPI0
  44. SPI0_BUS_CONFIG,
  45. #endif
  46. #ifdef BSP_USING_SPI1
  47. SPI1_BUS_CONFIG,
  48. #endif
  49. #ifdef BSP_USING_SPI2
  50. SPI2_BUS_CONFIG,
  51. #endif
  52. #ifdef BSP_USING_SPI3
  53. SPI3_BUS_CONFIG,
  54. #endif
  55. };
  56. static struct tm4c123_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
  57. static rt_err_t tm4c123_spi_configure(struct tm4c123_spi *spi_drv, struct rt_spi_configuration *cfg)
  58. {
  59. RT_ASSERT(spi_drv != RT_NULL);
  60. RT_ASSERT(cfg != RT_NULL);
  61. uint32_t ui32Protocol, ui32Mode;
  62. uint32_t ui32BitRate = (uint32_t)cfg->max_hz;
  63. uint32_t ui32DataWidth = (uint32_t)cfg->data_width;
  64. uint32_t pui32DataRx[1];
  65. rt_uint8_t ui8Protocol = 0;
  66. if (cfg->mode & RT_SPI_SLAVE)
  67. {
  68. ui32Mode = SSI_MODE_SLAVE;
  69. }
  70. else
  71. {
  72. ui32Mode = SSI_MODE_MASTER;
  73. }
  74. if (cfg->mode & RT_SPI_CPHA)
  75. {
  76. ui8Protocol += 1;
  77. }
  78. else
  79. {
  80. ui8Protocol += 0;
  81. }
  82. if (cfg->mode & RT_SPI_CPOL)
  83. {
  84. ui8Protocol += 2;
  85. }
  86. else
  87. {
  88. ui8Protocol += 0;
  89. }
  90. switch (ui8Protocol)
  91. {
  92. case 0:
  93. ui32Protocol = SSI_FRF_MOTO_MODE_0;
  94. break;
  95. case 1:
  96. ui32Protocol = SSI_FRF_MOTO_MODE_1;
  97. break;
  98. case 2:
  99. ui32Protocol = SSI_FRF_MOTO_MODE_2;
  100. break;
  101. case 3:
  102. ui32Protocol = SSI_FRF_MOTO_MODE_3;
  103. break;
  104. default:
  105. ui32Protocol = SSI_FRF_MOTO_MODE_0;
  106. break;
  107. }
  108. SSIConfigSetExpClk(spi_drv->config->base, SysCtlClockGet(), ui32Protocol,
  109. ui32Mode, ui32BitRate, ui32DataWidth);
  110. LOG_D("ssiclk freq: %d, SPI limiting freq: %d", SysCtlClockGet(), cfg->max_hz);
  111. SSIEnable(spi_drv->config->base);
  112. while (SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[0]))
  113. {
  114. }
  115. LOG_D("%s init done", spi_drv->config->bus_name);
  116. return RT_EOK;
  117. }
  118. static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  119. {
  120. rt_size_t message_length;
  121. rt_uint8_t *recv_buf;
  122. const rt_uint8_t *send_buf;
  123. uint32_t ReadData = 0;
  124. int i = 0;
  125. RT_ASSERT(device != RT_NULL);
  126. RT_ASSERT(device->bus != RT_NULL);
  127. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  128. RT_ASSERT(message != RT_NULL);
  129. struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus);
  130. struct tm4c123_hw_spi_cs *cs = device->parent.user_data;
  131. if (message->cs_take)
  132. {
  133. GPIOPinWrite(cs->portbase, cs->GPIO_Pin, 0);
  134. }
  135. LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
  136. LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
  137. spi_drv->config->bus_name,
  138. (uint32_t)message->send_buf,
  139. (uint32_t)message->recv_buf, message->length);
  140. message_length = message->length;
  141. recv_buf = message->recv_buf;
  142. send_buf = message->send_buf;
  143. if (message->send_buf && message->recv_buf)
  144. {
  145. for (i = 0; i < message_length; i++)
  146. {
  147. SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]);
  148. while (SSIBusy(spi_drv->config->base))
  149. {
  150. }
  151. SSIDataGet(spi_drv->config->base, &ReadData);
  152. recv_buf[i] = (unsigned char)ReadData;
  153. }
  154. }
  155. else if (message->send_buf)
  156. {
  157. for (i = 0; i < message_length; i++)
  158. {
  159. SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]);
  160. while (SSIBusy(spi_drv->config->base))
  161. {
  162. }
  163. SSIDataGet(spi_drv->config->base, &ReadData);
  164. }
  165. }
  166. else
  167. {
  168. for (i = 0; i < message_length; i++)
  169. {
  170. SSIDataPut(spi_drv->config->base, (uint32_t)0xff);
  171. while (SSIBusy(spi_drv->config->base))
  172. {
  173. }
  174. SSIDataGet(spi_drv->config->base, &ReadData);
  175. recv_buf[i] = (unsigned char)ReadData;
  176. }
  177. }
  178. LOG_D("%s transfer done", spi_drv->config->bus_name);
  179. if (message->cs_release)
  180. {
  181. GPIOPinWrite(cs->portbase, cs->GPIO_Pin, cs->GPIO_Pin);
  182. }
  183. return message->length;
  184. }
  185. static rt_err_t spi_configure(struct rt_spi_device *device,
  186. struct rt_spi_configuration *configuration)
  187. {
  188. RT_ASSERT(device != RT_NULL);
  189. RT_ASSERT(configuration != RT_NULL);
  190. struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus);
  191. spi_drv->cfg = configuration;
  192. return tm4c123_spi_configure(spi_drv, configuration);
  193. }
  194. static const struct rt_spi_ops tm4c123_spi_ops =
  195. {
  196. .configure = spi_configure,
  197. .xfer = spixfer,
  198. };
  199. static int rt_hw_spi_bus_init(void)
  200. {
  201. rt_err_t result;
  202. for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
  203. {
  204. spi_bus_obj[i].config = &spi_config[i];
  205. spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
  206. result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &tm4c123_spi_ops);
  207. RT_ASSERT(result == RT_EOK);
  208. LOG_D("%s bus init done", spi_config[i].bus_name);
  209. }
  210. return result;
  211. }
  212. /**
  213. * Attach the spi device to SPI bus, this function must be used after initialization.
  214. */
  215. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex, uint32_t cs_gpiobase, uint32_t cs_gpio_pin)
  216. {
  217. RT_ASSERT(bus_name != RT_NULL);
  218. RT_ASSERT(device_name != RT_NULL);
  219. rt_err_t result;
  220. struct rt_spi_device *spi_device;
  221. struct tm4c123_hw_spi_cs *cs_pin;
  222. /* initialize the cs pin && select the slave*/
  223. SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA + portindex);
  224. GPIOPinTypeGPIOOutput(cs_gpiobase, cs_gpio_pin);
  225. GPIOPinWrite(cs_gpiobase, cs_gpio_pin, cs_gpio_pin);
  226. /* attach the device to spi bus*/
  227. spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  228. RT_ASSERT(spi_device != RT_NULL);
  229. cs_pin = (struct tm4c123_hw_spi_cs *)rt_malloc(sizeof(struct tm4c123_hw_spi_cs));
  230. RT_ASSERT(cs_pin != RT_NULL);
  231. cs_pin->portbase = cs_gpiobase;
  232. cs_pin->GPIO_Pin = cs_gpio_pin;
  233. result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  234. if (result != RT_EOK)
  235. {
  236. LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
  237. }
  238. RT_ASSERT(result == RT_EOK);
  239. LOG_D("%s attach to %s done", device_name, bus_name);
  240. return result;
  241. }
  242. int rt_hw_spi_init(void)
  243. {
  244. spi_hw_config();
  245. return rt_hw_spi_bus_init();
  246. }
  247. INIT_BOARD_EXPORT(rt_hw_spi_init);
  248. #endif /* defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */
  249. #endif /*RT_USING_SPI*/
  250. /************************** end of file ******************/