yc_uart.c 9.4 KB

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  1. /*
  2. File Name : yc_uart.c
  3. Author : Yichip
  4. Version : V1.0
  5. Date : 2019/12/4
  6. Description : UART encapsulation.
  7. */
  8. #include "yc_uart.h"
  9. #define uart_DMA_buf_len 1024
  10. uint8_t uart0_DMA_buf[uart_DMA_buf_len] = {0};
  11. uint8_t uart1_DMA_buf[uart_DMA_buf_len] = {0};
  12. #define RX_ENABLE_BIT 0
  13. #define RX_ENABLE (1 << RX_ENABLE_BIT)
  14. #define UART_DMA_ENABLE_BIT 31
  15. #define UART_DMA_ENABLE (1 << UART_DMA_ENABLE_BIT)
  16. #define TX_INTR_ENABLE_BIT 31
  17. #define TX_INTR_ENABLE ((uint32_t)1 << TX_INTR_ENABLE_BIT)
  18. #define Set_RxITNum_Mask 0xff00
  19. #define Statu_RxNum_Mask (uint32_t)0xffff0000
  20. void UART_AutoFlowCtrlCmd(UART_TypeDef UARTx, FunctionalState NewState)
  21. {
  22. _ASSERT(IS_UART(UARTx));
  23. if (NewState == ENABLE)
  24. {
  25. switch (UARTx)
  26. {
  27. case UART0:
  28. UART0_CTRL |= FlowCtrl_Enable;
  29. break;
  30. case UART1:
  31. UART1_CTRL |= FlowCtrl_Enable;
  32. break;
  33. }
  34. }
  35. else
  36. {
  37. switch (UARTx)
  38. {
  39. case UART0:
  40. UART0_CTRL &= (~FlowCtrl_Enable);
  41. break;
  42. case UART1:
  43. UART1_CTRL &= (~FlowCtrl_Enable);
  44. break;
  45. }
  46. }
  47. return;
  48. }
  49. void UART_ClearIT(UART_TypeDef UARTx)
  50. {
  51. uint8_t ITType = UART_GetITIdentity(UARTx);
  52. UART_ITConfig(UARTx, ITType, DISABLE);
  53. }
  54. void UART_DeInit(UART_TypeDef UARTx)
  55. {
  56. _ASSERT(IS_UART(UARTx));
  57. switch (UARTx)
  58. {
  59. case UART0:
  60. UART0_CTRL = 0;
  61. break;
  62. case UART1:
  63. UART1_CTRL = 0;
  64. break;
  65. }
  66. }
  67. void UART_DMASendBuf(UART_TypeDef UARTx, uint8_t *buf, int len)
  68. {
  69. _ASSERT(IS_UART(UARTx));
  70. _ASSERT(NULL != buf);
  71. _ASSERT((len < 0xffff));
  72. if (UARTx == UART0)
  73. {
  74. DMA_SRC_ADDR(DMACH_UART0) = (int)buf;
  75. DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | len << 16;
  76. DMA_START(DMACH_UART0) = (1 << DMA_START_BIT);
  77. }
  78. else
  79. {
  80. DMA_SRC_ADDR(DMACH_UART1) = (int)buf;
  81. DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | len << 16;
  82. DMA_START(DMACH_UART1) = (1 << DMA_START_BIT);
  83. }
  84. }
  85. uint8_t UART_GetITIdentity(UART_TypeDef UARTx)
  86. {
  87. uint8_t IT_Mode = 0;
  88. switch (UARTx)
  89. {
  90. case UART0:
  91. {
  92. if (((UART0_CTRL & Set_RxITNum_Mask) > 0) && ((UART0_STATUS >> 16) > 0))
  93. {
  94. IT_Mode = UART_IT_RX;
  95. }
  96. else
  97. {
  98. if ((UART0_CTRL & (uint32_t)TX_INTR_ENABLE))
  99. {
  100. IT_Mode = UART_IT_TX;
  101. }
  102. else
  103. {
  104. IT_Mode = FALSE;
  105. }
  106. }
  107. }
  108. break;
  109. case UART1:
  110. {
  111. if (((UART1_CTRL & Set_RxITNum_Mask) > 0) && ((UART1_STATUS >> 16) > 0))
  112. {
  113. IT_Mode = UART_IT_RX;
  114. }
  115. else
  116. {
  117. if (UART1_CTRL & TX_INTR_ENABLE)
  118. {
  119. IT_Mode = UART_IT_TX;
  120. }
  121. else
  122. {
  123. IT_Mode = FALSE;
  124. }
  125. }
  126. }
  127. break;
  128. }
  129. return IT_Mode;
  130. }
  131. void UART_Init(UART_TypeDef UARTx, UART_InitTypeDef *UART_InitStruct)
  132. {
  133. #define RESET_BAUD (1 << 7)
  134. #define AUTO_BAUD (0 << 7)
  135. uint32_t reg_value = 0;
  136. uint32_t temp_baudrate = 0;
  137. _ASSERT(IS_UART(UARTx));
  138. _ASSERT(IS_MODE(UART_InitStruct->Mode));
  139. _ASSERT(IS_BAUDRATE(UART_InitStruct->BaudRate));
  140. _ASSERT(IS_PARITY(UART_InitStruct->Parity));
  141. _ASSERT(IS_FlowCtrl(UART_InitStruct->FlowCtrl));
  142. _ASSERT(IS_USART_STOPBITS(UART_InitStruct->StopBits));
  143. temp_baudrate = ((48000000 / UART_InitStruct->BaudRate) << 16);
  144. reg_value = RX_ENABLE |
  145. UART_InitStruct->Parity |
  146. UART_InitStruct->DataBits |
  147. UART_InitStruct->StopBits |
  148. UART_InitStruct->FlowCtrl |
  149. UART_InitStruct->Mode |
  150. RESET_BAUD |
  151. temp_baudrate;
  152. if (UARTx == UART0)
  153. {
  154. UART0_CTRL = 0;
  155. DMA_DEST_ADDR(DMACH_UART0) = (int)uart0_DMA_buf;
  156. DMA_LEN(DMACH_UART0) = uart_DMA_buf_len;
  157. DMA_CONFIG(DMACH_UART0) = 1;
  158. DMA_START(DMACH_UART0) |= (1 << (DMA_RESET_BIT));
  159. DMA_START(DMACH_UART0) &= ~(1 << (DMA_RESET_BIT));
  160. UART0_CTRL = 0;
  161. UART0_CTRL = reg_value;
  162. }
  163. else
  164. {
  165. UART1_CTRL = 0;
  166. DMA_DEST_ADDR(DMACH_UART1) = (int)uart1_DMA_buf;
  167. DMA_LEN(DMACH_UART1) = uart_DMA_buf_len;
  168. DMA_CONFIG(DMACH_UART1) = 1;
  169. DMA_START(DMACH_UART1) |= (1 << (DMA_RESET_BIT));
  170. DMA_START(DMACH_UART1) &= ~(1 << (DMA_RESET_BIT));
  171. UART1_CTRL = 0;
  172. UART1_CTRL = reg_value;
  173. }
  174. return;
  175. }
  176. Boolean UART_IsRXFIFOFull(UART_TypeDef UARTx)
  177. {
  178. #define BITRXFULL 1
  179. _ASSERT(IS_UART(UARTx));
  180. if (UART0 == UARTx)
  181. {
  182. return (Boolean)(UART0_STATUS & (1 << BITRXFULL));
  183. }
  184. else
  185. {
  186. return (Boolean)(UART1_STATUS & (1 << BITRXFULL));
  187. }
  188. }
  189. Boolean UART_IsRXFIFONotEmpty(UART_TypeDef UARTx)
  190. {
  191. #define BITRXEMPTY 0
  192. _ASSERT(IS_UART(UARTx));
  193. if (UART0 == UARTx)
  194. {
  195. return (Boolean)((UART0_STATUS >> 16) ? 1 : 0);
  196. }
  197. else
  198. {
  199. return (Boolean)((UART1_STATUS >> 16) ? 1 : 0);
  200. }
  201. }
  202. Boolean UART_IsUARTBusy(UART_TypeDef UARTx)
  203. {
  204. _ASSERT(IS_UART(UARTx));
  205. if (UART0 == UARTx)
  206. {
  207. return (Boolean)(!(DMA_STATUS(DMACH_UART0) & 1));
  208. }
  209. else
  210. {
  211. return (Boolean)(!(DMA_STATUS(DMACH_UART1) & 1));
  212. }
  213. }
  214. void UART_ITConfig(UART_TypeDef UARTx, uint32_t UART_IT, FunctionalState NewState)
  215. {
  216. _ASSERT(IS_UART(UARTx));
  217. _ASSERT(IS_UART_IT(UART_IT));
  218. switch (UARTx)
  219. {
  220. case UART0:
  221. {
  222. if (UART_IT == UART_IT_RX)
  223. {
  224. if (NewState)
  225. {
  226. UART0_CTRL |= ((ENABLE << 8));
  227. }
  228. else
  229. {
  230. UART0_CTRL &= ~Set_RxITNum_Mask;
  231. }
  232. }
  233. else if (UART_IT == UART_IT_TX)
  234. {
  235. UART0_CTRL &= (~TX_INTR_ENABLE);
  236. UART0_CTRL |= (NewState << TX_INTR_ENABLE_BIT);
  237. }
  238. }
  239. break;
  240. case UART1:
  241. {
  242. if (UART_IT == UART_IT_RX)
  243. {
  244. if (NewState)
  245. {
  246. UART1_CTRL |= ((ENABLE << 8));
  247. }
  248. else
  249. {
  250. UART1_CTRL &= ~Set_RxITNum_Mask;
  251. }
  252. }
  253. else if (UART_IT == UART_IT_TX)
  254. {
  255. UART1_CTRL &= (uint32_t)~TX_INTR_ENABLE;
  256. UART1_CTRL |= (NewState << TX_INTR_ENABLE_BIT);
  257. }
  258. }
  259. break;
  260. }
  261. }
  262. uint8_t UART_ReceiveData(UART_TypeDef UARTx)
  263. {
  264. _ASSERT(IS_UART(UARTx));
  265. if (UART0 == UARTx)
  266. {
  267. return UART0_RDATA;
  268. }
  269. else
  270. {
  271. return UART1_RDATA;
  272. }
  273. }
  274. int UART_RecvBuf(UART_TypeDef UARTx, uint8_t *buf, int len)
  275. {
  276. uint32_t length = 0;
  277. volatile int *pstatus = NULL;
  278. volatile unsigned char *pdata = NULL;
  279. _ASSERT(IS_UART(UARTx));
  280. _ASSERT(NULL != buf);
  281. if (UART0 == UARTx)
  282. {
  283. pstatus = &UART0_STATUS;
  284. pdata = &UART0_RDATA;
  285. }
  286. else
  287. {
  288. pstatus = &UART1_STATUS;
  289. pdata = &UART1_RDATA;
  290. }
  291. while ((*pstatus >> 16) > 0)
  292. {
  293. if (length < len)
  294. {
  295. buf[length++] = *pdata;
  296. }
  297. else
  298. {
  299. break;
  300. }
  301. }
  302. return length;
  303. }
  304. void UART_SendBuf(UART_TypeDef UARTx, uint8_t *buf, int len)
  305. {
  306. _ASSERT(IS_UART(UARTx));
  307. _ASSERT(NULL != buf);
  308. _ASSERT((len < 0xffff));
  309. if (UARTx == UART0)
  310. {
  311. DMA_SRC_ADDR(DMACH_UART0) = (int)buf;
  312. DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | len << 16;
  313. DMA_START(DMACH_UART0) = (1 << DMA_START_BIT);
  314. while ((!(DMA_STATUS(DMACH_UART0) & 1)));
  315. }
  316. else
  317. {
  318. DMA_SRC_ADDR(DMACH_UART1) = (int)buf;
  319. DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | len << 16;
  320. DMA_START(DMACH_UART1) = (1 << DMA_START_BIT);
  321. while ((!(DMA_STATUS(DMACH_UART1) & 1)));
  322. }
  323. }
  324. void UART_SendData(UART_TypeDef UARTx, uint8_t Data)
  325. {
  326. uint8_t buf[1] = {Data};
  327. if (UARTx == UART0)
  328. {
  329. DMA_SRC_ADDR(DMACH_UART0) = (int)buf;
  330. DMA_LEN(DMACH_UART0) = (DMA_LEN(DMACH_UART0) & 0xffff) | 1 << 16;
  331. DMA_START(DMACH_UART0) = (1 << DMA_START_BIT);
  332. while (!(DMA_STATUS(DMACH_UART0) & 1));
  333. }
  334. else
  335. {
  336. DMA_SRC_ADDR(DMACH_UART1) = (int)buf;
  337. DMA_LEN(DMACH_UART1) = (DMA_LEN(DMACH_UART1) & 0xffff) | 1 << 16;
  338. DMA_START(DMACH_UART1) = (1 << DMA_START_BIT);
  339. while (!(DMA_STATUS(DMACH_UART1) & 1));
  340. }
  341. }
  342. void UART_SetITTimeout(UART_TypeDef UARTx, uint16_t timeout)
  343. {
  344. if (UART0 == UARTx)
  345. {
  346. UART0_INTR = timeout;
  347. }
  348. else
  349. {
  350. UART1_INTR = timeout;
  351. }
  352. }
  353. void UART_SetRxITNum(UART_TypeDef UARTx, uint8_t Bcnt)
  354. {
  355. _ASSERT(IS_UART(UARTx));
  356. if (UART0 == UARTx)
  357. {
  358. UART0_CTRL = (UART0_CTRL & 0xffff00ff) | ((Bcnt & 0xff) << 8);
  359. }
  360. else
  361. {
  362. UART1_CTRL = (UART1_CTRL & 0xffff00ff) | ((Bcnt & 0xff) << 8);
  363. }
  364. }
  365. void UART_StructInit(UART_InitTypeDef *UART_InitStruct)
  366. {
  367. UART_InitStruct->BaudRate = 9600;
  368. UART_InitStruct->DataBits = Databits_8b;
  369. UART_InitStruct->FlowCtrl = FlowCtrl_None;
  370. UART_InitStruct->Mode = Mode_duplex;
  371. UART_InitStruct->StopBits = StopBits_1;
  372. UART_InitStruct->Parity = 0;
  373. }
  374. uint16_t UART_ReceiveDataLen(UART_TypeDef UARTx)
  375. {
  376. _ASSERT(IS_UART(UARTx));
  377. if (UART0 == UARTx)
  378. {
  379. return (uint16_t)(UART0_STATUS >> 16);
  380. }
  381. else
  382. {
  383. return (uint16_t)(UART1_STATUS >> 16);
  384. }
  385. }