psci.c 10 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-09-09 GuEe-GUI The first version
  9. * 2022-09-24 GuEe-GUI Add operations and fdt init support
  10. */
  11. #include <rtthread.h>
  12. #define DBG_TAG "osi.psci"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. /* support cpu mpidr and smccc from libcpu */
  16. #include <cpu.h>
  17. #include <smccc.h>
  18. #include <psci.h>
  19. #include <drivers/ofw.h>
  20. #include <drivers/platform.h>
  21. #include <drivers/core/dm.h>
  22. struct psci_ops
  23. {
  24. rt_uint32_t (*get_version)(void);
  25. rt_uint32_t (*cpu_on)(int cpuid, rt_ubase_t entry_point);
  26. rt_uint32_t (*cpu_off)(rt_uint32_t state);
  27. rt_uint32_t (*cpu_suspend)(rt_uint32_t power_state, rt_ubase_t entry_point);
  28. rt_uint32_t (*migrate)(int cpuid);
  29. rt_uint32_t (*get_affinity_info)(rt_ubase_t target_affinity, rt_ubase_t lowest_affinity_level);
  30. rt_uint32_t (*migrate_info_type)(void);
  31. };
  32. struct psci_0_1_func_ids
  33. {
  34. rt_uint32_t cpu_on;
  35. rt_uint32_t cpu_off;
  36. rt_uint32_t cpu_suspend;
  37. rt_uint32_t migrate;
  38. };
  39. typedef rt_err_t (*psci_init_ofw_handle)(struct rt_ofw_node *np);
  40. typedef rt_ubase_t (*psci_call_handle)(rt_uint32_t fn, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
  41. /* [40:63] and [24:31] must be zero, other is aff3 (64bit), aff2, aff1, aff0 */
  42. #ifdef ARCH_CPU_64BIT
  43. #define PSCI_FNC_ID(version_major, version_min, name) PSCI_##version_major##_##version_min##_FN64_##name
  44. #define MPIDR_MASK 0xff00ffffff
  45. #else
  46. #define PSCI_FNC_ID(version_major, version_min, name) PSCI_##version_major##_##version_min##_FN_##name
  47. #define MPIDR_MASK 0x00ffffff
  48. #endif
  49. static struct psci_ops _psci_ops = {};
  50. static struct psci_0_1_func_ids psci_0_1_func_ids = {};
  51. static psci_call_handle psci_call;
  52. /* PSCI SMCCC */
  53. static rt_ubase_t psci_smc_call(rt_uint32_t fn, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
  54. {
  55. struct arm_smccc_res_t res;
  56. arm_smccc_smc(fn, arg0, arg1, arg2, 0, 0, 0, 0, &res, RT_NULL);
  57. return res.a0;
  58. }
  59. static rt_ubase_t psci_hvc_call(rt_uint32_t fn, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
  60. {
  61. struct arm_smccc_res_t res;
  62. arm_smccc_hvc(fn, arg0, arg1, arg2, 0, 0, 0, 0, &res, RT_NULL);
  63. return res.a0;
  64. }
  65. /* PSCI VERSION */
  66. static rt_uint32_t psci_0_1_get_version(void)
  67. {
  68. return PSCI_VERSION(0, 1);
  69. }
  70. static rt_uint32_t psci_0_2_get_version(void)
  71. {
  72. return (rt_uint32_t)psci_call(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0);
  73. }
  74. /* PSCI FEATURES */
  75. static rt_uint32_t psci_get_features(rt_uint32_t psci_func_id)
  76. {
  77. return (rt_uint32_t)psci_call(PSCI_1_0_FN_PSCI_FEATURES, psci_func_id, 0, 0);
  78. }
  79. /* PSCI CPU_ON */
  80. static rt_uint32_t psci_cpu_on(rt_uint32_t func_id, int cpuid, rt_ubase_t entry_point)
  81. {
  82. rt_uint32_t ret = -PSCI_RET_INVALID_PARAMETERS;
  83. if (cpuid < RT_CPUS_NR)
  84. {
  85. rt_ubase_t mpid = rt_cpu_mpidr_table[cpuid] & MPIDR_MASK;
  86. ret = (rt_uint32_t)psci_call(func_id, mpid, entry_point, 0);
  87. }
  88. return ret;
  89. }
  90. static rt_uint32_t psci_0_1_cpu_on(int cpuid, rt_ubase_t entry_point)
  91. {
  92. return psci_cpu_on(psci_0_1_func_ids.cpu_on, cpuid, entry_point);
  93. }
  94. static rt_uint32_t psci_0_2_cpu_on(int cpuid, rt_ubase_t entry_point)
  95. {
  96. return psci_cpu_on(PSCI_FNC_ID(0, 2, CPU_ON), cpuid, entry_point);
  97. }
  98. /* PSCI CPU_OFF */
  99. static rt_uint32_t psci_cpu_off(rt_uint32_t func_id, rt_uint32_t state)
  100. {
  101. return (rt_uint32_t)psci_call(func_id, state, 0, 0);
  102. }
  103. static rt_uint32_t psci_0_1_cpu_off(rt_uint32_t state)
  104. {
  105. return psci_cpu_off(psci_0_1_func_ids.cpu_off, state);
  106. }
  107. static rt_uint32_t psci_0_2_cpu_off(rt_uint32_t state)
  108. {
  109. return psci_cpu_off(PSCI_0_2_FN_CPU_OFF, state);
  110. }
  111. /* PSCI CPU_SUSPEND */
  112. static rt_uint32_t psci_cpu_suspend(rt_uint32_t func_id, rt_uint32_t power_state, rt_ubase_t entry_point)
  113. {
  114. return (rt_uint32_t)psci_call(func_id, power_state, entry_point, 0);
  115. }
  116. static rt_uint32_t psci_0_1_cpu_suspend(rt_uint32_t power_state, rt_ubase_t entry_point)
  117. {
  118. return psci_cpu_suspend(psci_0_1_func_ids.cpu_suspend, power_state, entry_point);
  119. }
  120. static rt_uint32_t psci_0_2_cpu_suspend(rt_uint32_t power_state, rt_ubase_t entry_point)
  121. {
  122. return psci_cpu_suspend(PSCI_FNC_ID(0, 2, CPU_SUSPEND), power_state, entry_point);
  123. }
  124. /* PSCI CPU_MIGRATE */
  125. static rt_uint32_t psci_migrate(rt_uint32_t func_id, int cpuid)
  126. {
  127. rt_uint32_t ret = -PSCI_RET_INVALID_PARAMETERS;
  128. if (cpuid < RT_CPUS_NR)
  129. {
  130. rt_ubase_t mpid = rt_cpu_mpidr_table[cpuid] & MPIDR_MASK;
  131. ret = (rt_uint32_t)psci_call(func_id, mpid, 0, 0);
  132. }
  133. return ret;
  134. }
  135. static rt_uint32_t psci_0_1_migrate(int cpuid)
  136. {
  137. return psci_migrate(psci_0_1_func_ids.migrate, cpuid);
  138. }
  139. static rt_uint32_t psci_0_2_migrate(int cpuid)
  140. {
  141. return psci_migrate(PSCI_FNC_ID(0, 2, MIGRATE), cpuid);
  142. }
  143. /* PSCI AFFINITY_INFO */
  144. static rt_uint32_t psci_affinity_info(rt_ubase_t target_affinity, rt_ubase_t lowest_affinity_level)
  145. {
  146. return (rt_uint32_t)psci_call(PSCI_FNC_ID(0, 2, AFFINITY_INFO), target_affinity, lowest_affinity_level, 0);
  147. }
  148. /* PSCI MIGRATE_INFO_TYPE */
  149. static rt_uint32_t psci_migrate_info_type(void)
  150. {
  151. return (rt_uint32_t)psci_call(PSCI_0_2_FN_MIGRATE_INFO_TYPE, 0, 0, 0);
  152. }
  153. /* PSCI SYSTEM_OFF */
  154. void psci_system_off(void)
  155. {
  156. psci_call(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
  157. }
  158. /* PSCI SYSTEM_RESET */
  159. void psci_system_reboot(void)
  160. {
  161. if (psci_get_features(PSCI_FNC_ID(1, 1, SYSTEM_RESET2)) != PSCI_RET_NOT_SUPPORTED)
  162. {
  163. /*
  164. * reset_type[31] = 0 (architectural)
  165. * reset_type[30:0] = 0 (SYSTEM_WARM_RESET)
  166. * cookie = 0 (ignored by the implementation)
  167. */
  168. psci_call(PSCI_FNC_ID(1, 1, SYSTEM_RESET2), 0, 0, 0);
  169. }
  170. else
  171. {
  172. psci_call(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
  173. }
  174. }
  175. #define PSCI_CALL_FN_RET(fn, ...) \
  176. ({ \
  177. rt_uint32_t rc; \
  178. rc = PSCI_RET_NOT_SUPPORTED; \
  179. if (_psci_ops.fn) \
  180. rc = _psci_ops.fn(__VA_ARGS__); \
  181. rc; \
  182. })
  183. #define PSCI_CALL_FN(fn, ...) \
  184. ({ \
  185. if (_psci_ops.fn) \
  186. _psci_ops.fn(__VA_ARGS__); \
  187. })
  188. rt_uint32_t rt_psci_get_version(void)
  189. {
  190. return PSCI_CALL_FN_RET(get_version);
  191. }
  192. rt_uint32_t rt_psci_cpu_on(int cpuid, rt_ubase_t entry_point)
  193. {
  194. return PSCI_CALL_FN_RET(cpu_on, cpuid, entry_point);
  195. }
  196. rt_uint32_t rt_psci_cpu_off(rt_uint32_t state)
  197. {
  198. return PSCI_CALL_FN_RET(cpu_off, state);
  199. }
  200. rt_uint32_t rt_psci_cpu_suspend(rt_uint32_t power_state, rt_ubase_t entry_point)
  201. {
  202. return PSCI_CALL_FN_RET(cpu_suspend, power_state, entry_point);
  203. }
  204. rt_uint32_t rt_psci_migrate(int cpuid)
  205. {
  206. return PSCI_CALL_FN_RET(migrate, cpuid);
  207. }
  208. rt_uint32_t rt_psci_get_affinity_info(rt_ubase_t target_affinity, rt_ubase_t lowest_affinity_level)
  209. {
  210. return PSCI_CALL_FN_RET(get_affinity_info, target_affinity, lowest_affinity_level);
  211. }
  212. rt_uint32_t rt_psci_migrate_info_type(void)
  213. {
  214. return PSCI_CALL_FN_RET(migrate_info_type);
  215. }
  216. #undef PSCI_CALL_FN_RET
  217. #undef PSCI_CALL_FN
  218. /* PSCI INIT */
  219. static rt_err_t psci_0_1_init(struct rt_ofw_node *np)
  220. {
  221. rt_err_t err = RT_EOK;
  222. rt_uint32_t func_id;
  223. _psci_ops.get_version = psci_0_1_get_version;
  224. if (!rt_ofw_prop_read_u32(np, "cpu_on", &func_id))
  225. {
  226. psci_0_1_func_ids.cpu_on = func_id;
  227. _psci_ops.cpu_on = psci_0_1_cpu_on;
  228. }
  229. if (!rt_ofw_prop_read_u32(np, "cpu_off", &func_id))
  230. {
  231. psci_0_1_func_ids.cpu_off = func_id;
  232. _psci_ops.cpu_off = psci_0_1_cpu_off;
  233. }
  234. if (!rt_ofw_prop_read_u32(np, "cpu_suspend", &func_id))
  235. {
  236. psci_0_1_func_ids.cpu_suspend = func_id;
  237. _psci_ops.cpu_suspend = psci_0_1_cpu_suspend;
  238. }
  239. if (!rt_ofw_prop_read_u32(np, "migrate", &func_id))
  240. {
  241. psci_0_1_func_ids.migrate = func_id;
  242. _psci_ops.migrate = psci_0_1_migrate;
  243. }
  244. return err;
  245. }
  246. static rt_err_t psci_0_2_init(struct rt_ofw_node *np)
  247. {
  248. rt_err_t err = RT_EOK;
  249. rt_uint32_t version = psci_0_2_get_version();
  250. if (version >= PSCI_VERSION(0, 2))
  251. {
  252. _psci_ops.get_version = psci_0_2_get_version;
  253. _psci_ops.cpu_on = psci_0_2_cpu_on;
  254. _psci_ops.cpu_off = psci_0_2_cpu_off;
  255. _psci_ops.cpu_suspend = psci_0_2_cpu_suspend;
  256. _psci_ops.migrate = psci_0_2_migrate;
  257. _psci_ops.get_affinity_info = psci_affinity_info;
  258. _psci_ops.migrate_info_type = psci_migrate_info_type;
  259. }
  260. else
  261. {
  262. LOG_E("PSCI version detected");
  263. err = -RT_EINVAL;
  264. }
  265. return err;
  266. }
  267. static rt_err_t psci_1_0_init(struct rt_ofw_node *np)
  268. {
  269. rt_err_t err;
  270. err = psci_0_2_init(np);
  271. return err;
  272. }
  273. static rt_err_t psci_ofw_init(struct rt_platform_device *pdev)
  274. {
  275. rt_err_t err = RT_EOK;
  276. const char *method;
  277. const struct rt_ofw_node_id *id = pdev->id;
  278. struct rt_ofw_node *np = pdev->parent.ofw_node;
  279. if (!rt_ofw_prop_read_string(np, "method", &method))
  280. {
  281. if (!rt_strcmp(method, "smc"))
  282. {
  283. psci_call = psci_smc_call;
  284. }
  285. else if (!rt_strcmp(method, "hvc"))
  286. {
  287. psci_call = psci_hvc_call;
  288. }
  289. else
  290. {
  291. LOG_E("Invalid \"method\" property: %s", method);
  292. err = -RT_EINVAL;
  293. }
  294. if (!err)
  295. {
  296. psci_init_ofw_handle psci_init = (psci_init_ofw_handle)id->data;
  297. err = psci_init(np);
  298. if (!err)
  299. {
  300. rt_uint32_t version = rt_psci_get_version();
  301. rt_ofw_data(np) = &_psci_ops;
  302. RT_UNUSED(version);
  303. LOG_I("Using PSCI v%d.%d Function IDs", PSCI_VERSION_MAJOR(version), PSCI_VERSION_MINOR(version));
  304. }
  305. }
  306. }
  307. else
  308. {
  309. err = -RT_ENOSYS;
  310. }
  311. return err;
  312. }
  313. static rt_err_t psci_probe(struct rt_platform_device *pdev)
  314. {
  315. rt_err_t err;
  316. err = psci_ofw_init(pdev);
  317. return err;
  318. }
  319. static const struct rt_ofw_node_id psci_ofw_ids[] =
  320. {
  321. { .compatible = "arm,psci", .data = psci_0_1_init },
  322. { .compatible = "arm,psci-0.2", .data = psci_0_2_init },
  323. { .compatible = "arm,psci-1.0", .data = psci_1_0_init },
  324. { /* sentinel */ }
  325. };
  326. static struct rt_platform_driver psci_driver =
  327. {
  328. .name = "arm-psci",
  329. .ids = psci_ofw_ids,
  330. .probe = psci_probe,
  331. };
  332. static int psci_drv_register(void)
  333. {
  334. rt_platform_driver_register(&psci_driver);
  335. return 0;
  336. }
  337. INIT_FRAMEWORK_EXPORT(psci_drv_register);