drv_eth.h 3.8 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-25 zylx first version
  9. */
  10. #ifndef __DRV_ETH_H__
  11. #define __DRV_ETH_H__
  12. #include <rtthread.h>
  13. #include <rthw.h>
  14. #include <rtdevice.h>
  15. #include <board.h>
  16. /* The PHY basic control register */
  17. #define PHY_BASIC_CONTROL_REG 0x00U
  18. #define PHY_RESET_MASK (1<<15)
  19. #define PHY_AUTO_NEGOTIATION_MASK (1<<12)
  20. /* The PHY basic status register */
  21. #define PHY_BASIC_STATUS_REG 0x01U
  22. #define PHY_LINKED_STATUS_MASK (1<<2)
  23. #define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
  24. /* The PHY ID one register */
  25. #define PHY_ID1_REG 0x02U
  26. /* The PHY ID two register */
  27. #define PHY_ID2_REG 0x03U
  28. /* The PHY auto-negotiate advertise register */
  29. #define PHY_AUTONEG_ADVERTISE_REG 0x04U
  30. #ifdef PHY_USING_LAN8720A
  31. /* The PHY interrupt source flag register. */
  32. #define PHY_INTERRUPT_FLAG_REG 0x1DU
  33. /* The PHY interrupt mask register. */
  34. #define PHY_INTERRUPT_MASK_REG 0x1EU
  35. #define PHY_LINK_DOWN_MASK (1<<4)
  36. #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
  37. /* The PHY status register. */
  38. #define PHY_Status_REG 0x1FU
  39. #define PHY_10M_MASK (1<<2)
  40. #define PHY_100M_MASK (1<<3)
  41. #define PHY_FULL_DUPLEX_MASK (1<<4)
  42. #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
  43. #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
  44. #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
  45. #endif /* PHY_USING_LAN8720A */
  46. #ifdef PHY_USING_DM9161CEP
  47. #define PHY_Status_REG 0x11U
  48. #define PHY_10M_MASK ((1<<12) || (1<<13))
  49. #define PHY_100M_MASK ((1<<14) || (1<<15))
  50. #define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
  51. #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
  52. #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
  53. #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
  54. /* The PHY interrupt source flag register. */
  55. #define PHY_INTERRUPT_FLAG_REG 0x15U
  56. /* The PHY interrupt mask register. */
  57. #define PHY_INTERRUPT_MASK_REG 0x15U
  58. #define PHY_LINK_CHANGE_FLAG (1<<2)
  59. #define PHY_LINK_CHANGE_MASK (1<<9)
  60. #define PHY_INT_MASK 0
  61. #endif /* PHY_USING_DM9161CEP */
  62. #ifdef PHY_USING_DP83848C
  63. #define PHY_Status_REG 0x10U
  64. #define PHY_10M_MASK (1<<1)
  65. #define PHY_FULL_DUPLEX_MASK (1<<2)
  66. #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
  67. #define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
  68. #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
  69. /* The PHY interrupt source flag register. */
  70. #define PHY_INTERRUPT_FLAG_REG 0x12U
  71. #define PHY_LINK_CHANGE_FLAG (1<<13)
  72. /* The PHY interrupt control register. */
  73. #define PHY_INTERRUPT_CTRL_REG 0x11U
  74. #define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
  75. /* The PHY interrupt mask register. */
  76. #define PHY_INTERRUPT_MASK_REG 0x12U
  77. #define PHY_INT_MASK (1<<5)
  78. #endif /* PHY_USING_DP83848C */
  79. #ifdef PHY_USING_LAN8742A
  80. /* The PHY interrupt source flag register. */
  81. #define PHY_INTERRUPT_FLAG_REG 0x1DU
  82. /* The PHY interrupt mask register. */
  83. #define PHY_INTERRUPT_MASK_REG 0x1EU
  84. #define PHY_LINK_DOWN_MASK (1<<4)
  85. #define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
  86. /* The PHY status register. */
  87. #define PHY_Status_REG 0x1FU
  88. #define PHY_10M_MASK (1<<2)
  89. #define PHY_100M_MASK (1<<3)
  90. #define PHY_FULL_DUPLEX_MASK (1<<4)
  91. #define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
  92. #define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
  93. #define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
  94. #endif /* PHY_USING_LAN8742A */
  95. #endif /* __DRV_ETH_H__ */