usbhs_001.h 4.7 KB

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  1. /*
  2. * @brief High-Speed USB registers and control functions
  3. *
  4. * @note
  5. * Copyright(C) NXP Semiconductors, 2012
  6. * All rights reserved.
  7. *
  8. * @par
  9. * Software that is described herein is for illustrative purposes only
  10. * which provides customers with programming information regarding the
  11. * LPC products. This software is supplied "AS IS" without any warranties of
  12. * any kind, and NXP Semiconductors and its licensor disclaim any and
  13. * all warranties, express or implied, including all implied warranties of
  14. * merchantability, fitness for a particular purpose and non-infringement of
  15. * intellectual property rights. NXP Semiconductors assumes no responsibility
  16. * or liability for the use of the software, conveys no license or rights under any
  17. * patent, copyright, mask work right, or any other intellectual property rights in
  18. * or to any products. NXP Semiconductors reserves the right to make changes
  19. * in the software without notification. NXP Semiconductors also makes no
  20. * representation or warranty that such application will be suitable for the
  21. * specified use without further testing or modification.
  22. *
  23. * @par
  24. * Permission to use, copy, modify, and distribute this software and its
  25. * documentation is hereby granted, under NXP Semiconductors' and its
  26. * licensor's relevant copyrights in the software, without fee, provided that it
  27. * is used in conjunction with NXP Semiconductors microcontrollers. This
  28. * copyright, permission, and disclaimer notice must appear in all copies of
  29. * this code.
  30. */
  31. #ifndef __USBHS_001_H_
  32. #define __USBHS_001_H_
  33. #include "sys_config.h"
  34. #include "cmsis.h"
  35. #ifdef __cplusplus
  36. extern "C" {
  37. #endif
  38. /** @defgroup IP_USBHS_001 IP: USBHS Device, Host, & OTG register block and driver
  39. * @ingroup IP_Drivers
  40. * USB High-Speed Device, Host, & OTG
  41. * Note: On the LPC18xx and LPC43xx, only USB0 supports OTG
  42. * @{
  43. */
  44. /**
  45. * @brief USB High-Speed register block structure
  46. */
  47. typedef struct { /*!< USB Structure */
  48. __I uint32_t RESERVED0[64];
  49. __I uint32_t CAPLENGTH; /*!< Capability register length */
  50. __I uint32_t HCSPARAMS; /*!< Host controller structural parameters */
  51. __I uint32_t HCCPARAMS; /*!< Host controller capability parameters */
  52. __I uint32_t RESERVED1[5];
  53. __I uint32_t DCIVERSION; /*!< Device interface version number */
  54. __I uint32_t RESERVED2[7];
  55. union {
  56. __IO uint32_t USBCMD_H; /*!< USB command (host mode) */
  57. __IO uint32_t USBCMD_D; /*!< USB command (device mode) */
  58. };
  59. union {
  60. __IO uint32_t USBSTS_H; /*!< USB status (host mode) */
  61. __IO uint32_t USBSTS_D; /*!< USB status (device mode) */
  62. };
  63. union {
  64. __IO uint32_t USBINTR_H; /*!< USB interrupt enable (host mode) */
  65. __IO uint32_t USBINTR_D; /*!< USB interrupt enable (device mode) */
  66. };
  67. union {
  68. __IO uint32_t FRINDEX_H; /*!< USB frame index (host mode) */
  69. __I uint32_t FRINDEX_D; /*!< USB frame index (device mode) */
  70. };
  71. __I uint32_t RESERVED3;
  72. union {
  73. __IO uint32_t PERIODICLISTBASE; /*!< Frame list base address */
  74. __IO uint32_t DEVICEADDR; /*!< USB device address */
  75. };
  76. union {
  77. __IO uint32_t ASYNCLISTADDR; /*!< Address of endpoint list in memory (host mode) */
  78. __IO uint32_t ENDPOINTLISTADDR; /*!< Address of endpoint list in memory (device mode) */
  79. };
  80. __IO uint32_t TTCTRL; /*!< Asynchronous buffer status for embedded TT (host mode) */
  81. __IO uint32_t BURSTSIZE; /*!< Programmable burst size */
  82. __IO uint32_t TXFILLTUNING; /*!< Host transmit pre-buffer packet tuning (host mode) */
  83. __I uint32_t RESERVED4[2];
  84. __IO uint32_t ULPIVIEWPORT; /*!< ULPI viewport */
  85. __IO uint32_t BINTERVAL; /*!< Length of virtual frame */
  86. __IO uint32_t ENDPTNAK; /*!< Endpoint NAK (device mode) */
  87. __IO uint32_t ENDPTNAKEN; /*!< Endpoint NAK Enable (device mode) */
  88. __I uint32_t RESERVED5;
  89. union {
  90. __IO uint32_t PORTSC1_H; /*!< Port 1 status/control (host mode) */
  91. __IO uint32_t PORTSC1_D; /*!< Port 1 status/control (device mode) */
  92. };
  93. __I uint32_t RESERVED6[7];
  94. __IO uint32_t OTGSC; /*!< OTG status and control */
  95. union {
  96. __IO uint32_t USBMODE_H; /*!< USB mode (host mode) */
  97. __IO uint32_t USBMODE_D; /*!< USB mode (device mode) */
  98. };
  99. __IO uint32_t ENDPTSETUPSTAT; /*!< Endpoint setup status */
  100. __IO uint32_t ENDPTPRIME; /*!< Endpoint initialization */
  101. __IO uint32_t ENDPTFLUSH; /*!< Endpoint de-initialization */
  102. __I uint32_t ENDPTSTAT; /*!< Endpoint status */
  103. __IO uint32_t ENDPTCOMPLETE; /*!< Endpoint complete */
  104. __IO uint32_t ENDPTCTRL[6]; /*!< Endpoint control 0 */
  105. } IP_USBHS_001_Type;
  106. /**
  107. * @}
  108. */
  109. #ifdef __cplusplus
  110. }
  111. #endif
  112. #endif /* __USBHS_001_H_ */