drv_adc.c 6.7 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-05 zylx first version
  9. * 2018-12-12 greedyhao Porting for stm32f7xx
  10. * 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue
  11. */
  12. #include <board.h>
  13. #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
  14. #include "drv_config.h"
  15. //#define DRV_DEBUG
  16. #define LOG_TAG "drv.adc"
  17. #include <drv_log.h>
  18. static ADC_HandleTypeDef adc_config[] =
  19. {
  20. #ifdef BSP_USING_ADC1
  21. ADC1_CONFIG,
  22. #endif
  23. #ifdef BSP_USING_ADC2
  24. ADC2_CONFIG,
  25. #endif
  26. #ifdef BSP_USING_ADC3
  27. ADC3_CONFIG,
  28. #endif
  29. };
  30. struct stm32_adc
  31. {
  32. ADC_HandleTypeDef ADC_Handler;
  33. struct rt_adc_device stm32_adc_device;
  34. };
  35. static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
  36. static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
  37. {
  38. ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
  39. RT_ASSERT(device != RT_NULL);
  40. if (enabled)
  41. {
  42. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  43. ADC_Enable(stm32_adc_handler);
  44. #else
  45. __HAL_ADC_ENABLE(stm32_adc_handler);
  46. #endif
  47. }
  48. else
  49. {
  50. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  51. ADC_Disable(stm32_adc_handler);
  52. #else
  53. __HAL_ADC_DISABLE(stm32_adc_handler);
  54. #endif
  55. }
  56. return RT_EOK;
  57. }
  58. static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
  59. {
  60. rt_uint32_t stm32_channel = 0;
  61. switch (channel)
  62. {
  63. case 0:
  64. stm32_channel = ADC_CHANNEL_0;
  65. break;
  66. case 1:
  67. stm32_channel = ADC_CHANNEL_1;
  68. break;
  69. case 2:
  70. stm32_channel = ADC_CHANNEL_2;
  71. break;
  72. case 3:
  73. stm32_channel = ADC_CHANNEL_3;
  74. break;
  75. case 4:
  76. stm32_channel = ADC_CHANNEL_4;
  77. break;
  78. case 5:
  79. stm32_channel = ADC_CHANNEL_5;
  80. break;
  81. case 6:
  82. stm32_channel = ADC_CHANNEL_6;
  83. break;
  84. case 7:
  85. stm32_channel = ADC_CHANNEL_7;
  86. break;
  87. case 8:
  88. stm32_channel = ADC_CHANNEL_8;
  89. break;
  90. case 9:
  91. stm32_channel = ADC_CHANNEL_9;
  92. break;
  93. case 10:
  94. stm32_channel = ADC_CHANNEL_10;
  95. break;
  96. case 11:
  97. stm32_channel = ADC_CHANNEL_11;
  98. break;
  99. case 12:
  100. stm32_channel = ADC_CHANNEL_12;
  101. break;
  102. case 13:
  103. stm32_channel = ADC_CHANNEL_13;
  104. break;
  105. case 14:
  106. stm32_channel = ADC_CHANNEL_14;
  107. break;
  108. case 15:
  109. stm32_channel = ADC_CHANNEL_15;
  110. break;
  111. case 16:
  112. stm32_channel = ADC_CHANNEL_16;
  113. break;
  114. case 17:
  115. stm32_channel = ADC_CHANNEL_17;
  116. break;
  117. #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
  118. case 18:
  119. stm32_channel = ADC_CHANNEL_18;
  120. break;
  121. #endif
  122. }
  123. return stm32_channel;
  124. }
  125. static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
  126. {
  127. ADC_ChannelConfTypeDef ADC_ChanConf;
  128. ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
  129. RT_ASSERT(device != RT_NULL);
  130. RT_ASSERT(value != RT_NULL);
  131. rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
  132. #if defined(SOC_SERIES_STM32F1)
  133. if (channel <= 17)
  134. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
  135. || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  136. if (channel <= 18)
  137. #endif
  138. {
  139. /* set stm32 ADC channel */
  140. ADC_ChanConf.Channel = stm32_adc_get_channel(channel);
  141. }
  142. else
  143. {
  144. #if defined(SOC_SERIES_STM32F1)
  145. LOG_E("ADC channel must be between 0 and 17.");
  146. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
  147. || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
  148. LOG_E("ADC channel must be between 0 and 18.");
  149. #endif
  150. return -RT_ERROR;
  151. }
  152. ADC_ChanConf.Rank = 1;
  153. #if defined(SOC_SERIES_STM32F0)
  154. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
  155. #elif defined(SOC_SERIES_STM32F1)
  156. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
  157. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  158. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
  159. #elif defined(SOC_SERIES_STM32L4)
  160. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
  161. #endif
  162. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
  163. ADC_ChanConf.Offset = 0;
  164. #endif
  165. #ifdef SOC_SERIES_STM32L4
  166. ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
  167. ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
  168. #endif
  169. HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
  170. /* start ADC */
  171. HAL_ADC_Start(stm32_adc_handler);
  172. /* Wait for the ADC to convert */
  173. HAL_ADC_PollForConversion(stm32_adc_handler, 100);
  174. /* get ADC value */
  175. *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
  176. return RT_EOK;
  177. }
  178. static const struct rt_adc_ops stm_adc_ops =
  179. {
  180. .enabled = stm32_adc_enabled,
  181. .convert = stm32_get_adc_value,
  182. };
  183. static int stm32_adc_init(void)
  184. {
  185. int result = RT_EOK;
  186. /* save adc name */
  187. char name_buf[5] = {'a', 'd', 'c', '0', 0};
  188. int i = 0;
  189. for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
  190. {
  191. /* ADC init */
  192. name_buf[3] = '0';
  193. stm32_adc_obj[i].ADC_Handler = adc_config[i];
  194. #if defined(ADC1)
  195. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
  196. {
  197. name_buf[3] = '1';
  198. }
  199. #endif
  200. #if defined(ADC2)
  201. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
  202. {
  203. name_buf[3] = '2';
  204. }
  205. #endif
  206. #if defined(ADC3)
  207. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
  208. {
  209. name_buf[3] = '3';
  210. }
  211. #endif
  212. if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
  213. {
  214. LOG_E("%s init failed", name_buf);
  215. result = -RT_ERROR;
  216. }
  217. else
  218. {
  219. /* register ADC device */
  220. if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
  221. {
  222. LOG_D("%s init success", name_buf);
  223. }
  224. else
  225. {
  226. LOG_E("%s register failed", name_buf);
  227. result = -RT_ERROR;
  228. }
  229. }
  230. }
  231. return result;
  232. }
  233. INIT_BOARD_EXPORT(stm32_adc_init);
  234. #endif /* BSP_USING_ADC */