drv_smc911x.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020/12/31 Bernard Add license info
  9. */
  10. #include <board.h>
  11. #include <rtthread.h>
  12. #include <netif/ethernetif.h>
  13. #include <lwipopts.h>
  14. #include <automac.h>
  15. #define MAX_ADDR_LEN 6
  16. #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
  17. #include "drv_smc911x.h"
  18. #define DRIVERNAME "EMAC"
  19. struct eth_device_smc911x
  20. {
  21. /* inherit from Ethernet device */
  22. struct eth_device parent;
  23. /* interface address info. */
  24. rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
  25. uint32_t iobase;
  26. uint32_t irqno;
  27. };
  28. static struct eth_device_smc911x _emac;
  29. #if defined (CONFIG_SMC911X_32_BIT)
  30. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  31. {
  32. return *(volatile uint32_t *)(dev->iobase + offset);
  33. }
  34. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  35. {
  36. *(volatile uint32_t *)(dev->iobase + offset) = val;
  37. }
  38. #elif defined (CONFIG_SMC911X_16_BIT)
  39. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  40. {
  41. volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
  42. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  43. }
  44. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  45. {
  46. *(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
  47. *(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
  48. }
  49. #else
  50. #error "SMC911X: undefined bus width"
  51. #endif /* CONFIG_SMC911X_16_BIT */
  52. struct chip_id
  53. {
  54. uint16_t id;
  55. char *name;
  56. };
  57. static const struct chip_id chip_ids[] =
  58. {
  59. { LAN9118_ID_89218, "LAN89218" },
  60. { LAN9118_ID_9115, "LAN9115" },
  61. { LAN9118_ID_9116, "LAN9116" },
  62. { LAN9118_ID_9117, "LAN9117" },
  63. { LAN9118_ID_9118, "LAN9118" },
  64. { LAN9210_ID_9211, "LAN9211" },
  65. { LAN9218_ID_9215, "LAN9215" },
  66. { LAN9218_ID_9216, "LAN9216" },
  67. { LAN9218_ID_9217, "LAN9217" },
  68. { LAN9218_ID_9218, "LAN9218" },
  69. { LAN9220_ID_9220, "LAN9220" },
  70. { LAN9220_ID_9221, "LAN9221" },
  71. { 0, RT_NULL },
  72. };
  73. static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
  74. {
  75. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  76. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | LAN9118_MAC_CSR_CMD_R | reg);
  77. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  78. return smc911x_reg_read(dev, LAN9118_MAC_CSR_DATA);
  79. }
  80. static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
  81. {
  82. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  83. smc911x_reg_write(dev, LAN9118_MAC_CSR_DATA, data);
  84. smc911x_reg_write(dev, LAN9118_MAC_CSR_CMD, LAN9118_MAC_CSR_CMD_BUSY | reg);
  85. while (smc911x_reg_read(dev, LAN9118_MAC_CSR_CMD) & LAN9118_MAC_CSR_CMD_BUSY) ;
  86. }
  87. static int smc911x_detect_chip(struct eth_device_smc911x *dev)
  88. {
  89. unsigned long val, i;
  90. val = smc911x_reg_read(dev, LAN9118_BYTE_TEST);
  91. if (val == 0xffffffff)
  92. {
  93. /* Special case -- no chip present */
  94. return -1;
  95. }
  96. else if (val != 0x87654321)
  97. {
  98. rt_kprintf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
  99. return -1;
  100. }
  101. val = smc911x_reg_read(dev, LAN9118_ID_REV) >> 16;
  102. for (i = 0; chip_ids[i].id != 0; i++)
  103. {
  104. if (chip_ids[i].id == val) break;
  105. }
  106. if (!chip_ids[i].id)
  107. {
  108. rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  109. return -1;
  110. }
  111. return 0;
  112. }
  113. static void smc911x_reset(struct eth_device_smc911x *dev)
  114. {
  115. int timeout;
  116. /*
  117. * Take out of PM setting first
  118. * Device is already wake up if LAN9118_PMT_CTRL_READY bit is set
  119. */
  120. if ((smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY) == 0)
  121. {
  122. /* Write to the bytetest will take out of powerdown */
  123. smc911x_reg_write(dev, LAN9118_BYTE_TEST, 0x0);
  124. timeout = 10;
  125. while (timeout-- && !(smc911x_reg_read(dev, LAN9118_PMT_CTRL) & LAN9118_PMT_CTRL_READY))
  126. udelay(10);
  127. if (timeout < 0)
  128. {
  129. rt_kprintf(DRIVERNAME
  130. ": timeout waiting for PM restore\n");
  131. return;
  132. }
  133. }
  134. /* Disable interrupts */
  135. smc911x_reg_write(dev, LAN9118_INT_EN, 0);
  136. smc911x_reg_write(dev, LAN9118_HW_CFG, LAN9118_HW_CFG_SRST);
  137. timeout = 1000;
  138. while (timeout-- && smc911x_reg_read(dev, LAN9118_E2P_CMD) & LAN9118_E2P_CMD)
  139. udelay(10);
  140. if (timeout < 0)
  141. {
  142. rt_kprintf(DRIVERNAME ": reset timeout\n");
  143. return;
  144. }
  145. /* Reset the FIFO level and flow control settings */
  146. smc911x_set_mac_csr(dev, LAN9118_FLOW, LAN9118_FLOW_FCPT(0xffff) | LAN9118_FLOW_FCEN);
  147. smc911x_reg_write(dev, LAN9118_AFC_CFG, 0x0050287F);
  148. /* Set to LED outputs */
  149. smc911x_reg_write(dev, LAN9118_GPIO_CFG, 0x70070000);
  150. }
  151. static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
  152. {
  153. unsigned long addrh, addrl;
  154. uint8_t *m = dev->enetaddr;
  155. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  156. addrh = m[4] | (m[5] << 8);
  157. smc911x_set_mac_csr(dev, LAN9118_ADDRL, addrl);
  158. smc911x_set_mac_csr(dev, LAN9118_ADDRH, addrh);
  159. }
  160. static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
  161. uint8_t phy, uint8_t reg, uint16_t *val)
  162. {
  163. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  164. smc911x_set_mac_csr(dev, LAN9118_MII_ACC, phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY);
  165. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY) ;
  166. *val = smc911x_get_mac_csr(dev, LAN9118_MII_DATA);
  167. return 0;
  168. }
  169. static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
  170. uint8_t phy, uint8_t reg, uint16_t val)
  171. {
  172. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  173. ;
  174. smc911x_set_mac_csr(dev, LAN9118_MII_DATA, val);
  175. smc911x_set_mac_csr(dev, LAN9118_MII_ACC,
  176. phy << 11 | reg << 6 | LAN9118_MII_ACC_MIIBZY | LAN9118_MII_ACC_MIIWNR);
  177. while (smc911x_get_mac_csr(dev, LAN9118_MII_ACC) & LAN9118_MII_ACC_MIIBZY)
  178. ;
  179. return 0;
  180. }
  181. static int smc911x_phy_reset(struct eth_device_smc911x *dev)
  182. {
  183. uint32_t reg;
  184. reg = smc911x_reg_read(dev, LAN9118_PMT_CTRL);
  185. reg &= ~0xfffff030;
  186. reg |= LAN9118_PMT_CTRL_PHY_RST;
  187. smc911x_reg_write(dev, LAN9118_PMT_CTRL, reg);
  188. mdelay(100);
  189. return 0;
  190. }
  191. static void smc911x_phy_configure(struct eth_device_smc911x *dev)
  192. {
  193. int timeout;
  194. uint16_t status;
  195. smc911x_phy_reset(dev);
  196. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_RESET);
  197. mdelay(1);
  198. smc911x_eth_phy_write(dev, 1, LAN9118_MII_ADVERTISE, 0x01e1);
  199. smc911x_eth_phy_write(dev, 1, LAN9118_MII_BMCR, LAN9118_BMCR_ANENABLE | LAN9118_BMCR_ANRESTART);
  200. timeout = 5000;
  201. do
  202. {
  203. mdelay(1);
  204. if ((timeout--) == 0)
  205. goto err_out;
  206. if (smc911x_eth_phy_read(dev, 1, LAN9118_MII_BMSR, &status) != 0)
  207. goto err_out;
  208. }
  209. while (!(status & LAN9118_BMSR_LSTATUS));
  210. return;
  211. err_out:
  212. rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
  213. }
  214. static void smc911x_enable(struct eth_device_smc911x *dev)
  215. {
  216. /* Enable TX */
  217. smc911x_reg_write(dev, LAN9118_HW_CFG, 8 << 16 | LAN9118_HW_CFG_SF);
  218. smc911x_reg_write(dev, LAN9118_GPT_CFG, LAN9118_GPT_CFG_TIMER_EN | 10000);
  219. smc911x_reg_write(dev, LAN9118_TX_CFG, LAN9118_TX_CFG_TX_ON);
  220. /* no padding to start of packets */
  221. smc911x_reg_write(dev, LAN9118_RX_CFG, 0);
  222. smc911x_set_mac_csr(dev, LAN9118_MAC_CR, LAN9118_MAC_CR_TXEN | LAN9118_MAC_CR_RXEN |
  223. LAN9118_MAC_CR_HBDIS);
  224. }
  225. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  226. /* wrapper for smc911x_eth_phy_read */
  227. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  228. int reg)
  229. {
  230. uint16_t val = 0;
  231. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  232. if (dev)
  233. {
  234. int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
  235. if (retval < 0)
  236. return retval;
  237. return val;
  238. }
  239. return -ENODEV;
  240. }
  241. /* wrapper for smc911x_eth_phy_write */
  242. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  243. int reg, uint16_t val)
  244. {
  245. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  246. if (dev)
  247. return smc911x_eth_phy_write(dev, phy, reg, val);
  248. return -ENODEV;
  249. }
  250. #endif
  251. static void smc911x_isr(int vector, void *param)
  252. {
  253. uint32_t status;
  254. struct eth_device_smc911x *emac;
  255. emac = SMC911X_EMAC_DEVICE(param);
  256. status = smc911x_reg_read(emac, LAN9118_INT_STS);
  257. if (status & LAN9118_INT_STS_RSFL)
  258. {
  259. eth_device_ready(&emac->parent);
  260. }
  261. smc911x_reg_write(emac, LAN9118_INT_STS, status);
  262. return ;
  263. }
  264. static rt_err_t smc911x_emac_init(rt_device_t dev)
  265. {
  266. // uint32_t value;
  267. struct eth_device_smc911x *emac;
  268. emac = SMC911X_EMAC_DEVICE(dev);
  269. RT_ASSERT(emac != RT_NULL);
  270. smc911x_reset(emac);
  271. /* Configure the PHY, initialize the link state */
  272. smc911x_phy_configure(emac);
  273. smc911x_handle_mac_address(emac);
  274. /* Turn on Tx + Rx */
  275. smc911x_enable(emac);
  276. #if 1
  277. /* Interrupt on every received packet */
  278. smc911x_reg_write(emac, LAN9118_FIFO_INT, 0x01 << 8);
  279. smc911x_reg_write(emac, LAN9118_INT_EN, LAN9118_INT_EN_RDFL_EN | LAN9118_INT_RSFL);
  280. /* enable interrupt */
  281. smc911x_reg_write(emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_EN | LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  282. #else
  283. /* disable interrupt */
  284. smc911x_reg_write(emac, LAN9118_INT_EN, 0);
  285. value = smc911x_reg_read(emac, LAN9118_IRQ_CFG);
  286. value &= ~LAN9118_IRQ_CFG_IRQ_EN;
  287. smc911x_reg_write(emac, LAN9118_IRQ_CFG, value);
  288. #endif
  289. rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
  290. rt_hw_interrupt_umask(emac->irqno);
  291. return RT_EOK;
  292. }
  293. static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
  294. {
  295. struct eth_device_smc911x *emac;
  296. emac = SMC911X_EMAC_DEVICE(dev);
  297. RT_ASSERT(emac != RT_NULL);
  298. switch (cmd)
  299. {
  300. case NIOCTL_GADDR:
  301. /* get MAC address */
  302. if (args) rt_memcpy(args, emac->enetaddr, 6);
  303. else return -RT_ERROR;
  304. break;
  305. default :
  306. break;
  307. }
  308. return RT_EOK;
  309. }
  310. /* Ethernet device interface */
  311. /* transmit packet. */
  312. static uint8_t tx_buf[2048];
  313. rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf *p)
  314. {
  315. struct eth_device_smc911x *emac;
  316. uint32_t *data;
  317. uint32_t tmplen;
  318. uint32_t status;
  319. uint32_t length;
  320. emac = SMC911X_EMAC_DEVICE(dev);
  321. RT_ASSERT(emac != RT_NULL);
  322. /* copy pbuf to a whole ETH frame */
  323. pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
  324. /* send it out */
  325. data = (uint32_t *)tx_buf;
  326. length = p->tot_len;
  327. smc911x_reg_write(emac, LAN9118_TXDFIFOP, LAN9118_TXC_A_FS | LAN9118_TXC_A_LS | length);
  328. smc911x_reg_write(emac, LAN9118_TXDFIFOP, length);
  329. tmplen = (length + 3) / 4;
  330. while (tmplen--)
  331. {
  332. smc911x_reg_write(emac, LAN9118_TXDFIFOP, *data++);
  333. }
  334. /* wait for transmission */
  335. while (!(LAN9118_TX_FIFO_INF_TXSUSED(smc911x_reg_read(emac, LAN9118_TX_FIFO_INF))));
  336. /* get status. Ignore 'no carrier' error, it has no meaning for
  337. * full duplex operation
  338. */
  339. status = smc911x_reg_read(emac, LAN9118_TXSFIFOP) &
  340. (LAN9118_TXS_LOC | LAN9118_TXS_LCOL | LAN9118_TXS_ECOL |
  341. LAN9118_TXS_ED | LAN9118_TX_STS_UNDERRUN);
  342. if (!status) return 0;
  343. rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  344. status & LAN9118_TXS_LOC ? "LAN9118_TXS_LOC " : "",
  345. status & LAN9118_TXS_LCOL ? "LAN9118_TXS_LCOL " : "",
  346. status & LAN9118_TXS_ECOL ? "LAN9118_TXS_ECOL " : "",
  347. status & LAN9118_TXS_ED ? "LAN9118_TXS_ED " : "",
  348. status & LAN9118_TX_STS_UNDERRUN ? "LAN9118_TX_STS_UNDERRUN" : "");
  349. return -RT_EIO;
  350. }
  351. /* reception packet. */
  352. struct pbuf *smc911x_emac_rx(rt_device_t dev)
  353. {
  354. struct pbuf *p = RT_NULL;
  355. struct eth_device_smc911x *emac;
  356. emac = SMC911X_EMAC_DEVICE(dev);
  357. RT_ASSERT(emac != RT_NULL);
  358. /* take the emac buffer to the pbuf */
  359. if (LAN9118_RX_FIFO_INF_RXSUSED(smc911x_reg_read(emac, LAN9118_RX_FIFO_INF)))
  360. {
  361. uint32_t status;
  362. uint32_t pktlen, tmplen;
  363. status = smc911x_reg_read(emac, LAN9118_RXSFIFOP);
  364. /* get frame length */
  365. pktlen = (status & LAN9118_RX_STS_PKT_LEN) >> 16;
  366. smc911x_reg_write(emac, LAN9118_RX_CFG, 0);
  367. tmplen = (pktlen + 3) / 4;
  368. /* allocate pbuf */
  369. p = pbuf_alloc(PBUF_RAW, tmplen * 4, PBUF_RAM);
  370. if (p)
  371. {
  372. uint32_t *data = (uint32_t *)p->payload;
  373. while (tmplen--)
  374. {
  375. *data++ = smc911x_reg_read(emac, LAN9118_RXDFIFOP);
  376. }
  377. }
  378. if (status & LAN9118_RXS_ES)
  379. {
  380. rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
  381. }
  382. }
  383. return p;
  384. }
  385. #ifdef RT_USING_DEVICE_OPS
  386. const static struct rt_device_ops smc911x_emac_ops =
  387. {
  388. smc911x_emac_init,
  389. RT_NULL,
  390. RT_NULL,
  391. RT_NULL,
  392. RT_NULL,
  393. smc911x_emac_control
  394. };
  395. #endif
  396. int smc911x_emac_hw_init(void)
  397. {
  398. _emac.iobase = VEXPRESS_ETH_BASE;
  399. _emac.irqno = IRQ_VEXPRESS_A9_ETH;
  400. if (smc911x_detect_chip(&_emac))
  401. {
  402. rt_kprintf("no smc911x network interface found!\n");
  403. return -1;
  404. }
  405. /* set INT CFG */
  406. smc911x_reg_write(&_emac, LAN9118_IRQ_CFG, LAN9118_IRQ_CFG_IRQ_POL | LAN9118_IRQ_CFG_IRQ_TYPE);
  407. /* test MAC address */
  408. _emac.enetaddr[0] = AUTOMAC0;
  409. _emac.enetaddr[1] = AUTOMAC1;
  410. _emac.enetaddr[2] = AUTOMAC2;
  411. _emac.enetaddr[3] = AUTOMAC3;
  412. _emac.enetaddr[4] = AUTOMAC4;
  413. _emac.enetaddr[5] = AUTOMAC5;
  414. #ifdef RT_USING_DEVICE_OPS
  415. _emac.parent.parent.ops = &smc911x_emac_ops;
  416. #else
  417. _emac.parent.parent.init = smc911x_emac_init;
  418. _emac.parent.parent.open = RT_NULL;
  419. _emac.parent.parent.close = RT_NULL;
  420. _emac.parent.parent.read = RT_NULL;
  421. _emac.parent.parent.write = RT_NULL;
  422. _emac.parent.parent.control = smc911x_emac_control;
  423. #endif
  424. _emac.parent.parent.user_data = RT_NULL;
  425. _emac.parent.eth_rx = smc911x_emac_rx;
  426. _emac.parent.eth_tx = smc911x_emac_tx;
  427. /* register ETH device */
  428. eth_device_init(&(_emac.parent), "e0");
  429. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  430. {
  431. int retval;
  432. struct mii_dev *mdiodev = mdio_alloc();
  433. if (!mdiodev)
  434. return -ENOMEM;
  435. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  436. mdiodev->read = smc911x_miiphy_read;
  437. mdiodev->write = smc911x_miiphy_write;
  438. retval = mdio_register(mdiodev);
  439. if (retval < 0)
  440. return retval;
  441. }
  442. #endif
  443. eth_device_linkchange(&_emac.parent, RT_TRUE);
  444. return 0;
  445. }
  446. INIT_APP_EXPORT(smc911x_emac_hw_init);