gd32f4xx_can.h 44 KB

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  1. /*!
  2. \file gd32f4xx_can.h
  3. \brief definitions for the CAN
  4. */
  5. /*
  6. Copyright (C) 2016 GigaDevice
  7. 2016-08-15, V1.0.0, firmware for GD32F4xx
  8. */
  9. #ifndef GD32F4XX_CAN_H
  10. #define GD32F4XX_CAN_H
  11. #include "gd32f4xx.h"
  12. /* CAN definitions */
  13. #define CAN0 CAN_BASE /*!< CAN0 base address */
  14. #define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
  15. /* registers definitions */
  16. #define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */
  17. #define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */
  18. #define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/
  19. #define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */
  20. #define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */
  21. #define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */
  22. #define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */
  23. #define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */
  24. #define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */
  25. #define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */
  26. #define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */
  27. #define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */
  28. #define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */
  29. #define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */
  30. #define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */
  31. #define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */
  32. #define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */
  33. #define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */
  34. #define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */
  35. #define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */
  36. #define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */
  37. #define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */
  38. #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */
  39. #define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO0 mailbox data1 register */
  40. #define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */
  41. #define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */
  42. #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */
  43. #define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */
  44. #define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */
  45. #define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */
  46. #define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */
  47. #define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */
  48. #define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */
  49. #define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */
  50. #define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */
  51. #define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */
  52. #define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */
  53. #define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */
  54. #define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */
  55. #define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */
  56. #define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */
  57. #define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */
  58. #define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */
  59. #define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */
  60. #define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */
  61. #define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */
  62. #define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */
  63. #define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */
  64. #define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */
  65. #define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */
  66. #define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */
  67. #define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */
  68. #define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */
  69. #define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */
  70. #define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */
  71. #define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */
  72. #define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */
  73. #define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */
  74. #define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */
  75. #define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */
  76. #define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */
  77. #define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */
  78. #define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */
  79. #define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */
  80. #define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */
  81. #define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */
  82. #define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */
  83. #define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */
  84. #define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */
  85. #define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */
  86. #define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */
  87. #define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */
  88. #define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */
  89. #define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */
  90. #define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */
  91. #define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */
  92. #define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */
  93. #define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */
  94. #define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */
  95. #define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */
  96. #define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */
  97. #define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */
  98. #define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */
  99. #define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */
  100. #define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */
  101. #define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */
  102. #define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */
  103. #define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */
  104. #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */
  105. /* CAN transmit mailbox bank */
  106. #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
  107. #define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
  108. #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
  109. #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
  110. /* CAN filter bank */
  111. #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
  112. #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
  113. /* CAN receive fifo mailbox bank */
  114. #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
  115. #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
  116. #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
  117. #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
  118. /* bits definitions */
  119. /* CAN_CTL */
  120. #define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
  121. #define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
  122. #define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
  123. #define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
  124. #define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
  125. #define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
  126. #define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
  127. #define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
  128. #define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
  129. #define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
  130. /* CAN_STAT */
  131. #define CAN_STAT_IWS BIT(0) /*!< initial working state */
  132. #define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
  133. #define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
  134. #define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
  135. #define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
  136. #define CAN_STAT_TS BIT(8) /*!< transmitting state */
  137. #define CAN_STAT_RS BIT(9) /*!< receiving state */
  138. #define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
  139. #define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
  140. /* CAN_TSTAT */
  141. #define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
  142. #define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
  143. #define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
  144. #define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
  145. #define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
  146. #define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
  147. #define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
  148. #define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
  149. #define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
  150. #define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
  151. #define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
  152. #define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
  153. #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
  154. #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
  155. #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
  156. #define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
  157. #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
  158. #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
  159. #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
  160. #define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
  161. #define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
  162. #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
  163. /* CAN_RFIFO0 */
  164. #define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
  165. #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
  166. #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
  167. #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
  168. /* CAN_RFIFO1 */
  169. #define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
  170. #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
  171. #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
  172. #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
  173. /* CAN_INTEN */
  174. #define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
  175. #define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
  176. #define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
  177. #define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
  178. #define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
  179. #define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
  180. #define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
  181. #define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
  182. #define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
  183. #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
  184. #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
  185. #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
  186. #define CAN_INTEN_WUIE BIT(16) /*!< wakeup interrupt enable */
  187. #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
  188. /* CAN_ERR */
  189. #define CAN_ERR_WERR BIT(0) /*!< warning error */
  190. #define CAN_ERR_PERR BIT(1) /*!< passive error */
  191. #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
  192. #define CAN_ERR_ERRN BITS(4,6) /*!< error number */
  193. #define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
  194. #define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
  195. /* CAN_BT */
  196. #define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
  197. #define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
  198. #define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
  199. #define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
  200. #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
  201. #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
  202. /* CAN_TMIx */
  203. #define CAN_TMI_TEN BIT(0) /*!< transmit enable */
  204. #define CAN_TMI_FT BIT(1) /*!< frame type */
  205. #define CAN_TMI_FF BIT(2) /*!< frame format */
  206. #define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
  207. #define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
  208. /* CAN_TMPx */
  209. #define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
  210. #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
  211. #define CAN_TMP_TS BITS(16,31) /*!< time stamp */
  212. /* CAN_TMDATA0x */
  213. #define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
  214. #define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
  215. #define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
  216. #define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
  217. /* CAN_TMDATA1x */
  218. #define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
  219. #define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
  220. #define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
  221. #define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
  222. /* CAN_RFIFOMIx */
  223. #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
  224. #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
  225. #define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
  226. #define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
  227. /* CAN_RFIFOMPx */
  228. #define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
  229. #define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
  230. #define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
  231. /* CAN_RFIFOMDATA0x */
  232. #define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
  233. #define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
  234. #define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
  235. #define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
  236. /* CAN_RFIFOMDATA1x */
  237. #define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
  238. #define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
  239. #define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
  240. #define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
  241. /* CAN_FCTL */
  242. #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
  243. #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
  244. /* CAN_FMCFG */
  245. #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/
  246. /* CAN_FSCFG */
  247. #define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/
  248. /* CAN_FAFIFO */
  249. #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
  250. /* CAN_FW */
  251. #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
  252. /* consts definitions */
  253. /* define the CAN bit position and its register index offset */
  254. #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
  255. #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
  256. #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
  257. /* register offset */
  258. #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
  259. #define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
  260. #define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
  261. #define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
  262. #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
  263. /* CAN flags */
  264. typedef enum
  265. {
  266. /* flags in TSTAT register */
  267. CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
  268. CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
  269. CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
  270. CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
  271. CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
  272. CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
  273. /* flags in RFIFO0 register */
  274. CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
  275. CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
  276. /* flags in RFIFO1 register */
  277. CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
  278. CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
  279. /* flags in ERR register */
  280. CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
  281. CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
  282. CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
  283. }can_flag_enum;
  284. /* CAN interrupt flags */
  285. typedef enum
  286. {
  287. /* interrupt flags in STAT register */
  288. CAN_INT_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change interrupt flag of sleep working mode entering */
  289. CAN_INT_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change interrupt flag of wakeup from sleep working mode */
  290. CAN_INT_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error interrupt flag */
  291. }can_interrupt_flag_enum;
  292. /* CAN initiliaze parameters struct */
  293. typedef struct
  294. {
  295. uint8_t working_mode; /*!< CAN working mode */
  296. uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
  297. uint8_t time_segment_1; /*!< time segment 1 */
  298. uint8_t time_segment_2; /*!< time segment 2 */
  299. ControlStatus time_triggered; /*!< time triggered communication mode */
  300. ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
  301. ControlStatus auto_wake_up; /*!< automatic wake-up mode */
  302. ControlStatus auto_retrans; /*!< automatic retransmission mode */
  303. ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
  304. ControlStatus trans_fifo_order; /*!< transmit FIFO order */
  305. uint16_t prescaler; /*!< baudrate prescaler */
  306. }can_parameter_struct;
  307. /* CAN transmit message struct */
  308. typedef struct
  309. {
  310. uint32_t tx_sfid; /*!< standard format frame identifier */
  311. uint32_t tx_efid; /*!< extended format frame identifier */
  312. uint8_t tx_ff; /*!< format of frame, standard or extended format */
  313. uint8_t tx_ft; /*!< type of frame, data or remote */
  314. uint8_t tx_dlen; /*!< data length */
  315. uint8_t tx_data[8]; /*!< transmit data */
  316. }can_trasnmit_message_struct;
  317. /* CAN receive message struct */
  318. typedef struct
  319. {
  320. uint32_t rx_sfid; /*!< standard format frame identifier */
  321. uint32_t rx_efid; /*!< extended format frame identifier */
  322. uint8_t rx_ff; /*!< format of frame, standard or extended format */
  323. uint8_t rx_ft; /*!< type of frame, data or remote */
  324. uint8_t rx_dlen; /*!< data length */
  325. uint8_t rx_data[8]; /*!< receive data */
  326. uint8_t rx_fi; /*!< filtering index */
  327. } can_receive_message_struct;
  328. /* CAN filter parameters struct */
  329. typedef struct
  330. {
  331. uint16_t filter_list_high; /*!< filter list number high bits*/
  332. uint16_t filter_list_low; /*!< filter list number low bits */
  333. uint16_t filter_mask_high; /*!< filter mask number high bits */
  334. uint16_t filter_mask_low; /*!< filter mask number low bits */
  335. uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
  336. uint16_t filter_number; /*!< filter number */
  337. uint16_t filter_mode; /*!< filter mode, list or mask */
  338. uint16_t filter_bits; /*!< filter scale */
  339. ControlStatus filter_enable; /*!< filter work or not */
  340. }can_filter_parameter_struct;
  341. /* CAN errors */
  342. typedef enum
  343. {
  344. CAN_ERROR_NONE = 0, /*!< no error */
  345. CAN_ERROR_FILL, /*!< fill error */
  346. CAN_ERROR_FORMATE, /*!< format error */
  347. CAN_ERROR_ACK, /*!< ACK error */
  348. CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
  349. CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
  350. CAN_ERROR_CRC, /*!< CRC error */
  351. CAN_ERROR_SOFTWARECFG /*!< software configure */
  352. }can_error_enum;
  353. /* transmit states */
  354. typedef enum
  355. {
  356. CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */
  357. CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */
  358. CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */
  359. CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */
  360. }can_transmit_state_enum;
  361. /* CAN baudrate prescaler*/
  362. #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
  363. /* CAN bit segment 1*/
  364. #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
  365. /* CAN bit segment 2*/
  366. #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
  367. /* CAN resynchronization jump width*/
  368. #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
  369. /* CAN communication mode*/
  370. #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
  371. /* CAN FDATA high 16 bits */
  372. #define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
  373. /* CAN FDATA low 16 bits */
  374. #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
  375. /* CAN1 filter start bank_number*/
  376. #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
  377. /* CAN transmit mailbox extended identifier*/
  378. #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
  379. /* CAN transmit mailbox standard identifier*/
  380. #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
  381. /* transmit data byte 0 */
  382. #define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
  383. /* transmit data byte 1 */
  384. #define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
  385. /* transmit data byte 2 */
  386. #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
  387. /* transmit data byte 3 */
  388. #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
  389. /* transmit data byte 4 */
  390. #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
  391. /* transmit data byte 5 */
  392. #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
  393. /* transmit data byte 6 */
  394. #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
  395. /* transmit data byte 7 */
  396. #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
  397. /* receive mailbox extended identifier*/
  398. #define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31)
  399. /* receive mailbox standrad identifier*/
  400. #define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31)
  401. /* receive data length */
  402. #define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3)
  403. #define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15)
  404. /* receive data byte 0 */
  405. #define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7)
  406. /* receive data byte 1 */
  407. #define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15)
  408. /* receive data byte 2 */
  409. #define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23)
  410. /* receive data byte 3 */
  411. #define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31)
  412. /* receive data byte 4 */
  413. #define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7)
  414. /* receive data byte 5 */
  415. #define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15)
  416. /* receive data byte 6 */
  417. #define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23)
  418. /* receive data byte 7 */
  419. #define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31)
  420. /* CAN errors */
  421. #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
  422. #define CAN_ERRN_0 ERR_ERRN(0) /* no error */
  423. #define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */
  424. #define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */
  425. #define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */
  426. #define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */
  427. #define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */
  428. #define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */
  429. #define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */
  430. #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
  431. /* CAN communication mode */
  432. #define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
  433. #define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
  434. #define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
  435. #define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
  436. /* CAN resynchronisation jump width */
  437. #define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
  438. #define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
  439. #define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
  440. #define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
  441. /* CAN time segment 1 */
  442. #define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
  443. #define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
  444. #define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
  445. #define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
  446. #define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
  447. #define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
  448. #define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
  449. #define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
  450. #define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
  451. #define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
  452. #define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
  453. #define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
  454. #define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
  455. #define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
  456. #define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
  457. #define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
  458. /* CAN time segment 2 */
  459. #define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
  460. #define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
  461. #define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
  462. #define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
  463. #define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
  464. #define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
  465. #define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
  466. #define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
  467. /* CAN mailbox number */
  468. #define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
  469. #define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
  470. #define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
  471. #define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
  472. /* CAN frame format */
  473. #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
  474. #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
  475. /* CAN receive fifo */
  476. #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
  477. #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
  478. /* frame number of receive fifo */
  479. #define CAN_RFIFO_RFL0_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFO0 */
  480. #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
  481. #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
  482. /* CAN working mode */
  483. #define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
  484. #define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
  485. #define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
  486. /* filter bits */
  487. #define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
  488. #define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
  489. /* filter mode */
  490. #define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
  491. #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
  492. /* filter 16 bits mask */
  493. #define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU)
  494. /* frame type */
  495. #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
  496. #define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
  497. /* CAN timeout */
  498. #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
  499. /* function declarations */
  500. /* initialization functions */
  501. /* CAN deinit */
  502. void can_deinit(uint32_t can_periph);
  503. /* CAN init */
  504. ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init);
  505. /* transmit functions */
  506. /* CAN transmit message */
  507. uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message);
  508. /* CAN transmit state */
  509. can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
  510. /* CAN stop transmission */
  511. void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
  512. /* CAN transmit error number */
  513. uint8_t can_transmit_error_number(uint32_t can_periph);
  514. /* filter functions */
  515. /* CAN filter init */
  516. void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init);
  517. /* set can1 fliter start bank number */
  518. void can1_filter_start_bank(uint8_t start_bank);
  519. /* enable functions */
  520. /* CAN debug freeze enable */
  521. void can_debug_freeze_enable(uint32_t can_periph);
  522. /* CAN debug freeze disable */
  523. void can_debug_freeze_disable(uint32_t can_periph);
  524. /* CAN time triggle mode enable */
  525. void can_time_trigger_mode_enable(uint32_t can_periph);
  526. /* CAN time triggle mode disable */
  527. void can_time_trigger_mode_disable(uint32_t can_periph);
  528. /* CAN interrupt enable */
  529. void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
  530. /* CAN interrupt disable */
  531. void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
  532. /* receive functions */
  533. /* CAN receive message */
  534. void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message);
  535. /* CAN release fifo */
  536. void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
  537. /* CAN receive message length */
  538. uint8_t can_receive_message_length(uint32_t can_periph, uint8_t fifo_number);
  539. /* CAN receive error number */
  540. uint8_t can_receive_error_number(uint32_t can_periph);
  541. /* mode functions */
  542. /* CAN working mode */
  543. ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
  544. /* CAN wakeup from sleep mode */
  545. ErrStatus can_wakeup(uint32_t can_periph);
  546. /* flag functions */
  547. /* CAN get error */
  548. can_error_enum can_error_get(uint32_t can_periph);
  549. /* CAN get flag state */
  550. FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
  551. /* CAN clear flag state */
  552. void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
  553. /* CAN get interrupt flag state */
  554. FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
  555. /* CAN clear interrupt flag state */
  556. void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
  557. #endif /* GD32F4XX_CAN_H */