spi_flash_w25qxx.c 12 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2011-12-16 aozima the first version
  9. * 2012-05-06 aozima can page write.
  10. * 2012-08-23 aozima add flash lock.
  11. * 2012-08-24 aozima fixed write status register BUG.
  12. */
  13. #include <stdint.h>
  14. #include <rtdevice.h>
  15. #include "spi_flash.h"
  16. #include "spi_flash_w25qxx.h"
  17. #define FLASH_DEBUG
  18. #ifdef FLASH_DEBUG
  19. #define FLASH_TRACE rt_kprintf
  20. #else
  21. #define FLASH_TRACE(...)
  22. #endif /* #ifdef FLASH_DEBUG */
  23. #define PAGE_SIZE 4096
  24. /* JEDEC Manufacturer锟斤拷s ID */
  25. #define MF_ID (0xEF)
  26. /* JEDEC Device ID: Memory type and Capacity */
  27. #define MTC_W25Q80_BV (0x4014) /* W25Q80BV */
  28. #define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */
  29. #define MTC_W25Q16_DW (0x6015) /* W25Q16DW */
  30. #define MTC_W25Q32_BV (0x4016) /* W25Q32BV */
  31. #define MTC_W25Q32_DW (0x6016) /* W25Q32DW */
  32. #define MTC_W25Q64_BV_CV (0x4017) /* W25Q64BV W25Q64CV */
  33. #define MTC_W25Q64_DW (0x4017) /* W25Q64DW */
  34. #define MTC_W25Q128_BV (0x4018) /* W25Q128BV */
  35. #define MTC_W25Q256_FV (TBD) /* W25Q256FV */
  36. /* command list */
  37. #define CMD_WRSR (0x01) /* Write Status Register */
  38. #define CMD_PP (0x02) /* Page Program */
  39. #define CMD_READ (0x03) /* Read Data */
  40. #define CMD_WRDI (0x04) /* Write Disable */
  41. #define CMD_RDSR1 (0x05) /* Read Status Register-1 */
  42. #define CMD_WREN (0x06) /* Write Enable */
  43. #define CMD_FAST_READ (0x0B) /* Fast Read */
  44. #define CMD_ERASE_4K (0x20) /* Sector Erase:4K */
  45. #define CMD_RDSR2 (0x35) /* Read Status Register-2 */
  46. #define CMD_ERASE_32K (0x52) /* 32KB Block Erase */
  47. #define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */
  48. #define CMD_ERASE_full (0xC7) /* Chip Erase */
  49. #define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */
  50. #define DUMMY (0xFF)
  51. static struct spi_flash_device spi_flash_device;
  52. static void flash_lock(struct spi_flash_device * flash_device)
  53. {
  54. rt_mutex_take(&flash_device->lock, RT_WAITING_FOREVER);
  55. }
  56. static void flash_unlock(struct spi_flash_device * flash_device)
  57. {
  58. rt_mutex_release(&flash_device->lock);
  59. }
  60. static uint8_t w25qxx_read_status(void)
  61. {
  62. return rt_spi_sendrecv8(spi_flash_device.rt_spi_device, CMD_RDSR1);
  63. }
  64. static void w25qxx_wait_busy(void)
  65. {
  66. while( w25qxx_read_status() & (0x01));
  67. }
  68. /** \brief read [size] byte from [offset] to [buffer]
  69. *
  70. * \param offset uint32_t unit : byte
  71. * \param buffer uint8_t*
  72. * \param size uint32_t unit : byte
  73. * \return uint32_t byte for read
  74. *
  75. */
  76. static uint32_t w25qxx_read(uint32_t offset, uint8_t * buffer, uint32_t size)
  77. {
  78. uint8_t send_buffer[4];
  79. send_buffer[0] = CMD_WRDI;
  80. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  81. send_buffer[0] = CMD_READ;
  82. send_buffer[1] = (uint8_t)(offset>>16);
  83. send_buffer[2] = (uint8_t)(offset>>8);
  84. send_buffer[3] = (uint8_t)(offset);
  85. rt_spi_send_then_recv(spi_flash_device.rt_spi_device,
  86. send_buffer, 4,
  87. buffer, size);
  88. return size;
  89. }
  90. /** \brief write N page on [page]
  91. *
  92. * \param page_addr uint32_t unit : byte (4096 * N,1 page = 4096byte)
  93. * \param buffer const uint8_t*
  94. * \return uint32_t
  95. *
  96. */
  97. uint32_t w25qxx_page_write(uint32_t page_addr, const uint8_t* buffer)
  98. {
  99. uint32_t index;
  100. uint8_t send_buffer[4];
  101. RT_ASSERT((page_addr&0xFF) == 0); /* page addr must align to 256byte. */
  102. send_buffer[0] = CMD_WREN;
  103. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  104. send_buffer[0] = CMD_ERASE_4K;
  105. send_buffer[1] = (page_addr >> 16);
  106. send_buffer[2] = (page_addr >> 8);
  107. send_buffer[3] = (page_addr);
  108. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 4);
  109. w25qxx_wait_busy(); // wait erase done.
  110. for(index=0; index < (PAGE_SIZE / 256); index++)
  111. {
  112. send_buffer[0] = CMD_WREN;
  113. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  114. send_buffer[0] = CMD_PP;
  115. send_buffer[1] = (uint8_t)(page_addr >> 16);
  116. send_buffer[2] = (uint8_t)(page_addr >> 8);
  117. send_buffer[3] = (uint8_t)(page_addr);
  118. rt_spi_send_then_send(spi_flash_device.rt_spi_device,
  119. send_buffer,
  120. 4,
  121. buffer,
  122. 256);
  123. buffer += 256;
  124. page_addr += 256;
  125. w25qxx_wait_busy();
  126. }
  127. send_buffer[0] = CMD_WRDI;
  128. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  129. return PAGE_SIZE;
  130. }
  131. /* RT-Thread device interface */
  132. static rt_err_t w25qxx_flash_init(rt_device_t dev)
  133. {
  134. return RT_EOK;
  135. }
  136. static rt_err_t w25qxx_flash_open(rt_device_t dev, rt_uint16_t oflag)
  137. {
  138. uint8_t send_buffer[3];
  139. flash_lock((struct spi_flash_device *)dev);
  140. send_buffer[0] = CMD_WREN;
  141. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 1);
  142. send_buffer[0] = CMD_WRSR;
  143. send_buffer[1] = 0;
  144. send_buffer[2] = 0;
  145. rt_spi_send(spi_flash_device.rt_spi_device, send_buffer, 3);
  146. w25qxx_wait_busy();
  147. flash_unlock((struct spi_flash_device *)dev);
  148. return RT_EOK;
  149. }
  150. static rt_err_t w25qxx_flash_close(rt_device_t dev)
  151. {
  152. return RT_EOK;
  153. }
  154. static rt_err_t w25qxx_flash_control(rt_device_t dev, int cmd, void *args)
  155. {
  156. RT_ASSERT(dev != RT_NULL);
  157. if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
  158. {
  159. struct rt_device_blk_geometry *geometry;
  160. geometry = (struct rt_device_blk_geometry *)args;
  161. if (geometry == RT_NULL) return -RT_ERROR;
  162. geometry->bytes_per_sector = spi_flash_device.geometry.bytes_per_sector;
  163. geometry->sector_count = spi_flash_device.geometry.sector_count;
  164. geometry->block_size = spi_flash_device.geometry.block_size;
  165. }
  166. return RT_EOK;
  167. }
  168. static rt_size_t w25qxx_flash_read(rt_device_t dev,
  169. rt_off_t pos,
  170. void* buffer,
  171. rt_size_t size)
  172. {
  173. flash_lock((struct spi_flash_device *)dev);
  174. w25qxx_read(pos*spi_flash_device.geometry.bytes_per_sector,
  175. buffer,
  176. size*spi_flash_device.geometry.bytes_per_sector);
  177. flash_unlock((struct spi_flash_device *)dev);
  178. return size;
  179. }
  180. static rt_size_t w25qxx_flash_write(rt_device_t dev,
  181. rt_off_t pos,
  182. const void* buffer,
  183. rt_size_t size)
  184. {
  185. rt_size_t i = 0;
  186. rt_size_t block = size;
  187. const uint8_t * ptr = buffer;
  188. flash_lock((struct spi_flash_device *)dev);
  189. while(block--)
  190. {
  191. w25qxx_page_write((pos + i)*spi_flash_device.geometry.bytes_per_sector,
  192. ptr);
  193. ptr += PAGE_SIZE;
  194. i++;
  195. }
  196. flash_unlock((struct spi_flash_device *)dev);
  197. return size;
  198. }
  199. #ifdef RT_USING_DEVICE_OPS
  200. const static struct rt_device_ops w25qxx_device_ops =
  201. {
  202. w25qxx_flash_init,
  203. w25qxx_flash_open,
  204. w25qxx_flash_close,
  205. w25qxx_flash_read,
  206. w25qxx_flash_write,
  207. w25qxx_flash_control
  208. };
  209. #endif
  210. rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_name)
  211. {
  212. struct rt_spi_device * rt_spi_device;
  213. /* initialize mutex */
  214. if (rt_mutex_init(&spi_flash_device.lock, spi_device_name, RT_IPC_FLAG_FIFO) != RT_EOK)
  215. {
  216. rt_kprintf("init sd lock mutex failed\n");
  217. return -RT_ENOSYS;
  218. }
  219. rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
  220. if(rt_spi_device == RT_NULL)
  221. {
  222. FLASH_TRACE("spi device %s not found!\r\n", spi_device_name);
  223. return -RT_ENOSYS;
  224. }
  225. spi_flash_device.rt_spi_device = rt_spi_device;
  226. /* config spi */
  227. {
  228. struct rt_spi_configuration cfg;
  229. cfg.data_width = 8;
  230. cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */
  231. cfg.max_hz = 50 * 1000 * 1000; /* 50M */
  232. rt_spi_configure(spi_flash_device.rt_spi_device, &cfg);
  233. }
  234. /* init flash */
  235. {
  236. rt_uint8_t cmd;
  237. rt_uint8_t id_recv[3];
  238. uint16_t memory_type_capacity;
  239. flash_lock(&spi_flash_device);
  240. cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
  241. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  242. cmd = CMD_WRDI;
  243. rt_spi_send(spi_flash_device.rt_spi_device, &cmd, 1);
  244. /* read flash id */
  245. cmd = CMD_JEDEC_ID;
  246. rt_spi_send_then_recv(spi_flash_device.rt_spi_device, &cmd, 1, id_recv, 3);
  247. flash_unlock(&spi_flash_device);
  248. if(id_recv[0] != MF_ID)
  249. {
  250. FLASH_TRACE("Manufacturers ID error!\r\n");
  251. FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]);
  252. return -RT_ENOSYS;
  253. }
  254. spi_flash_device.geometry.bytes_per_sector = 4096;
  255. spi_flash_device.geometry.block_size = 4096; /* block erase: 4k */
  256. /* get memory type and capacity */
  257. memory_type_capacity = id_recv[1];
  258. memory_type_capacity = (memory_type_capacity << 8) | id_recv[2];
  259. if(memory_type_capacity == MTC_W25Q128_BV)
  260. {
  261. FLASH_TRACE("W25Q128BV detection\r\n");
  262. spi_flash_device.geometry.sector_count = 4096;
  263. }
  264. else if(memory_type_capacity == MTC_W25Q64_BV_CV)
  265. {
  266. FLASH_TRACE("W25Q64BV or W25Q64CV detection\r\n");
  267. spi_flash_device.geometry.sector_count = 2048;
  268. }
  269. else if(memory_type_capacity == MTC_W25Q64_DW)
  270. {
  271. FLASH_TRACE("W25Q64DW detection\r\n");
  272. spi_flash_device.geometry.sector_count = 2048;
  273. }
  274. else if(memory_type_capacity == MTC_W25Q32_BV)
  275. {
  276. FLASH_TRACE("W25Q32BV detection\r\n");
  277. spi_flash_device.geometry.sector_count = 1024;
  278. }
  279. else if(memory_type_capacity == MTC_W25Q32_DW)
  280. {
  281. FLASH_TRACE("W25Q32DW detection\r\n");
  282. spi_flash_device.geometry.sector_count = 1024;
  283. }
  284. else if(memory_type_capacity == MTC_W25Q16_BV_CL_CV)
  285. {
  286. FLASH_TRACE("W25Q16BV or W25Q16CL or W25Q16CV detection\r\n");
  287. spi_flash_device.geometry.sector_count = 512;
  288. }
  289. else if(memory_type_capacity == MTC_W25Q16_DW)
  290. {
  291. FLASH_TRACE("W25Q16DW detection\r\n");
  292. spi_flash_device.geometry.sector_count = 512;
  293. }
  294. else if(memory_type_capacity == MTC_W25Q80_BV)
  295. {
  296. FLASH_TRACE("W25Q80BV detection\r\n");
  297. spi_flash_device.geometry.sector_count = 256;
  298. }
  299. else
  300. {
  301. FLASH_TRACE("Memory Capacity error!\r\n");
  302. return -RT_ENOSYS;
  303. }
  304. }
  305. /* register device */
  306. spi_flash_device.flash_device.type = RT_Device_Class_Block;
  307. #ifdef RT_USING_DEVICE_OPS
  308. spi_flash_device.flash_device.ops = &w25qxx_device_ops;
  309. #else
  310. spi_flash_device.flash_device.init = w25qxx_flash_init;
  311. spi_flash_device.flash_device.open = w25qxx_flash_open;
  312. spi_flash_device.flash_device.close = w25qxx_flash_close;
  313. spi_flash_device.flash_device.read = w25qxx_flash_read;
  314. spi_flash_device.flash_device.write = w25qxx_flash_write;
  315. spi_flash_device.flash_device.control = w25qxx_flash_control;
  316. #endif
  317. /* no private */
  318. spi_flash_device.flash_device.user_data = RT_NULL;
  319. rt_device_register(&spi_flash_device.flash_device, flash_device_name,
  320. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
  321. return RT_EOK;
  322. }