usb_hc_ehci.c 41 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usb_hc_ehci.h"
  7. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  8. #include "usb_hc_ohci.h"
  9. #endif
  10. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  11. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  12. #define EHCI_TUNE_RL_TT 0
  13. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  14. #define EHCI_TUNE_MULT_TT 1
  15. struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS];
  16. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw ehci_qh_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QH_NUM];
  17. /* The head of the asynchronous queue */
  18. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_async_qh_head[CONFIG_USBHOST_MAX_BUS];
  19. /* The head of the periodic queue */
  20. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_periodic_qh_head[CONFIG_USBHOST_MAX_BUS];
  21. /* The frame list */
  22. USB_NOCACHE_RAM_SECTION uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)] __attribute__((aligned(4096)));
  23. static struct ehci_qh_hw *ehci_qh_alloc(struct usbh_bus *bus)
  24. {
  25. struct ehci_qh_hw *qh;
  26. struct ehci_qtd_hw *qtd;
  27. size_t flags;
  28. flags = usb_osal_enter_critical_section();
  29. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  30. if (!g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i]) {
  31. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = true;
  32. usb_osal_leave_critical_section(flags);
  33. qh = &ehci_qh_pool[bus->hcd.hcd_id][i];
  34. memset(&qh->hw, 0, sizeof(struct ehci_qh));
  35. qh->hw.hlp = QTD_LIST_END;
  36. qh->hw.overlay.next_qtd = QTD_LIST_END;
  37. qh->hw.overlay.alt_next_qtd = QTD_LIST_END;
  38. qh->urb = NULL;
  39. for (uint32_t j = 0; j < CONFIG_USB_EHCI_QTD_NUM; j++) {
  40. qtd = &qh->qtd_pool[j];
  41. qtd->hw.next_qtd = QTD_LIST_END;
  42. qtd->hw.alt_next_qtd = QTD_LIST_END;
  43. qtd->hw.token = QTD_TOKEN_STATUS_HALTED;
  44. qtd->urb = NULL;
  45. }
  46. return qh;
  47. }
  48. }
  49. usb_osal_leave_critical_section(flags);
  50. return NULL;
  51. }
  52. static void ehci_qh_free(struct usbh_bus *bus, struct ehci_qh_hw *qh)
  53. {
  54. size_t flags;
  55. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  56. if (&ehci_qh_pool[bus->hcd.hcd_id][i] == qh) {
  57. flags = usb_osal_enter_critical_section();
  58. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = false;
  59. usb_osal_leave_critical_section(flags);
  60. qh->urb = NULL;
  61. return;
  62. }
  63. }
  64. }
  65. static inline void ehci_qh_add_head(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  66. {
  67. n->hw.hlp = head->hw.hlp;
  68. head->hw.hlp = QH_HLP_QH(n);
  69. }
  70. static inline void ehci_qh_remove(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  71. {
  72. struct ehci_qh_hw *tmp = head;
  73. while (EHCI_ADDR2QH(tmp->hw.hlp) && EHCI_ADDR2QH(tmp->hw.hlp) != n) {
  74. tmp = EHCI_ADDR2QH(tmp->hw.hlp);
  75. }
  76. if (tmp) {
  77. tmp->hw.hlp = n->hw.hlp;
  78. }
  79. }
  80. static int ehci_caculate_smask(int binterval)
  81. {
  82. int order, interval;
  83. interval = 1;
  84. while (binterval > 1) {
  85. interval *= 2;
  86. binterval--;
  87. }
  88. if (interval < 2) /* interval 1 */
  89. return 0xFF;
  90. if (interval < 4) /* interval 2 */
  91. return 0x55;
  92. if (interval < 8) /* interval 4 */
  93. return 0x22;
  94. for (order = 0; (interval > 1); order++) {
  95. interval >>= 1;
  96. }
  97. return (0x1 << (order % 8));
  98. }
  99. static void ehci_qh_fill(struct ehci_qh_hw *qh,
  100. uint8_t dev_addr,
  101. uint8_t ep_addr,
  102. uint8_t ep_type,
  103. uint16_t ep_mps,
  104. uint8_t ep_mult,
  105. uint8_t ep_interval,
  106. uint8_t speed,
  107. uint8_t hubaddr,
  108. uint8_t hubport)
  109. {
  110. uint32_t epchar = 0;
  111. uint32_t epcap = 0;
  112. /* QH endpoint characteristics:
  113. *
  114. * FIELD DESCRIPTION
  115. * -------- -------------------------------
  116. * DEVADDR Device address
  117. * I Inactivate on Next Transaction
  118. * ENDPT Endpoint number
  119. * EPS Endpoint speed
  120. * DTC Data toggle control
  121. * MAXPKT Max packet size
  122. * C Control endpoint
  123. * RL NAK count reloaded
  124. */
  125. /* QH endpoint capabilities
  126. *
  127. * FIELD DESCRIPTION
  128. * -------- -------------------------------
  129. * SSMASK Interrupt Schedule Mask
  130. * SCMASK Split Completion Mask
  131. * HUBADDR Hub Address
  132. * PORT Port number
  133. * MULT High band width multiplier
  134. */
  135. epchar |= ((ep_addr & 0xf) << QH_EPCHAR_ENDPT_SHIFT);
  136. epchar |= (dev_addr << QH_EPCHAR_DEVADDR_SHIFT);
  137. epchar |= (ep_mps << QH_EPCHAR_MAXPKT_SHIFT);
  138. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  139. epchar |= QH_EPCHAR_DTC; /* toggle from qtd */
  140. }
  141. switch (speed) {
  142. case USB_SPEED_LOW:
  143. epchar |= QH_EPCHAR_EPS_LOW;
  144. __attribute__((fallthrough));
  145. case USB_SPEED_FULL:
  146. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  147. epchar |= QH_EPCHAR_C; /* for TT */
  148. }
  149. if (ep_type != USB_ENDPOINT_TYPE_INTERRUPT) {
  150. epchar |= (EHCI_TUNE_RL_TT << QH_EPCHAR_RL_SHIFT);
  151. }
  152. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_TT);
  153. epcap |= QH_EPCAPS_HUBADDR(hubaddr);
  154. epcap |= QH_EPCAPS_PORT(hubport);
  155. if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) {
  156. epcap |= QH_EPCAPS_SSMASK(2);
  157. epcap |= QH_EPCAPS_SCMASK(0x78);
  158. }
  159. break;
  160. case USB_SPEED_HIGH:
  161. epchar |= QH_EPCHAR_EPS_HIGH;
  162. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  163. epchar |= (EHCI_TUNE_RL_HS << QH_EPCHAR_RL_SHIFT);
  164. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  165. } else if (ep_type == USB_ENDPOINT_TYPE_BULK) {
  166. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  167. } else {
  168. /* only for interrupt ep */
  169. epcap |= QH_EPCAPS_MULT(ep_mult);
  170. epcap |= ehci_caculate_smask(ep_interval);
  171. }
  172. break;
  173. default:
  174. break;
  175. }
  176. qh->hw.epchar = epchar;
  177. qh->hw.epcap = epcap;
  178. }
  179. static void ehci_qtd_bpl_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen)
  180. {
  181. uint32_t rest;
  182. qtd->hw.bpl[0] = bufaddr;
  183. rest = 0x1000 - (bufaddr & 0xfff);
  184. if (buflen < rest) {
  185. rest = buflen;
  186. } else {
  187. bufaddr += 0x1000;
  188. bufaddr &= ~0x0fff;
  189. for (int i = 1; rest < buflen && i < 5; i++) {
  190. qtd->hw.bpl[i] = bufaddr;
  191. bufaddr += 0x1000;
  192. if ((rest + 0x1000) < buflen) {
  193. rest += 0x1000;
  194. } else {
  195. rest = buflen;
  196. }
  197. }
  198. }
  199. }
  200. static void ehci_qtd_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen, uint32_t token)
  201. {
  202. /* qTD token
  203. *
  204. * FIELD DESCRIPTION
  205. * -------- -------------------------------
  206. * STATUS Status
  207. * PID PID Code
  208. * CERR Error Counter
  209. * CPAGE Current Page
  210. * IOC Interrupt on complete
  211. * NBYTES Total Bytes to Transfer
  212. * TOGGLE Data Toggle
  213. */
  214. qtd->hw.token = token;
  215. ehci_qtd_bpl_fill(qtd, bufaddr, buflen);
  216. qtd->length = buflen;
  217. }
  218. static struct ehci_qh_hw *ehci_control_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen)
  219. {
  220. struct ehci_qh_hw *qh = NULL;
  221. struct ehci_qtd_hw *qtd_setup = NULL;
  222. struct ehci_qtd_hw *qtd_data = NULL;
  223. struct ehci_qtd_hw *qtd_status = NULL;
  224. uint32_t token;
  225. size_t flags;
  226. qh = ehci_qh_alloc(bus);
  227. if (qh == NULL) {
  228. return NULL;
  229. }
  230. qtd_setup = &qh->qtd_pool[0];
  231. qtd_data = &qh->qtd_pool[1];
  232. qtd_status = &qh->qtd_pool[2];
  233. ehci_qh_fill(qh,
  234. urb->hport->dev_addr,
  235. urb->ep->bEndpointAddress,
  236. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  237. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  238. 0,
  239. 0,
  240. urb->hport->speed,
  241. urb->hport->parent->hub_addr,
  242. urb->hport->port);
  243. /* fill setup qtd */
  244. token = QTD_TOKEN_STATUS_ACTIVE |
  245. QTD_TOKEN_PID_SETUP |
  246. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  247. ((uint32_t)8 << QTD_TOKEN_NBYTES_SHIFT);
  248. ehci_qtd_fill(qtd_setup, (uintptr_t)setup, 8, token);
  249. qtd_setup->urb = urb;
  250. /* fill data qtd */
  251. if (setup->wLength > 0) {
  252. if ((setup->bmRequestType & 0x80) == 0x80) {
  253. token = QTD_TOKEN_PID_IN;
  254. } else {
  255. token = QTD_TOKEN_PID_OUT;
  256. }
  257. token |= QTD_TOKEN_STATUS_ACTIVE |
  258. QTD_TOKEN_PID_OUT |
  259. QTD_TOKEN_TOGGLE |
  260. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  261. ((uint32_t)buflen << QTD_TOKEN_NBYTES_SHIFT);
  262. ehci_qtd_fill(qtd_data, (uintptr_t)buffer, buflen, token);
  263. qtd_data->urb = urb;
  264. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_data);
  265. qtd_data->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  266. } else {
  267. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  268. }
  269. /* fill status qtd */
  270. if ((setup->bmRequestType & 0x80) == 0x80) {
  271. token = QTD_TOKEN_PID_OUT;
  272. } else {
  273. token = QTD_TOKEN_PID_IN;
  274. }
  275. token |= QTD_TOKEN_STATUS_ACTIVE |
  276. QTD_TOKEN_TOGGLE |
  277. QTD_TOKEN_IOC |
  278. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  279. ((uint32_t)0 << QTD_TOKEN_NBYTES_SHIFT);
  280. ehci_qtd_fill(qtd_status, 0, 0, token);
  281. qtd_status->urb = urb;
  282. qtd_status->hw.next_qtd = QTD_LIST_END;
  283. /* update qh first qtd */
  284. qh->hw.curr_qtd = EHCI_PTR2ADDR(qtd_setup);
  285. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(qtd_setup);
  286. /* record qh first qtd */
  287. qh->first_qtd = EHCI_PTR2ADDR(qtd_setup);
  288. flags = usb_osal_enter_critical_section();
  289. qh->urb = urb;
  290. urb->hcpriv = qh;
  291. /* add qh into async list */
  292. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  293. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  294. usb_osal_leave_critical_section(flags);
  295. return qh;
  296. }
  297. static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  298. {
  299. struct ehci_qh_hw *qh = NULL;
  300. struct ehci_qtd_hw *qtd = NULL;
  301. struct ehci_qtd_hw *first_qtd = NULL;
  302. struct ehci_qtd_hw *prev_qtd = NULL;
  303. uint32_t qtd_num = 0;
  304. uint32_t xfer_len = 0;
  305. uint32_t token;
  306. size_t flags;
  307. qh = ehci_qh_alloc(bus);
  308. if (qh == NULL) {
  309. return NULL;
  310. }
  311. ehci_qh_fill(qh,
  312. urb->hport->dev_addr,
  313. urb->ep->bEndpointAddress,
  314. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  315. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  316. 0,
  317. 0,
  318. urb->hport->speed,
  319. urb->hport->parent->hub_addr,
  320. urb->hport->port);
  321. while (1) {
  322. qtd = &qh->qtd_pool[qtd_num];
  323. if (buflen > 0x4000) {
  324. xfer_len = 0x4000;
  325. buflen -= 0x4000;
  326. } else {
  327. xfer_len = buflen;
  328. buflen = 0;
  329. }
  330. if (urb->ep->bEndpointAddress & 0x80) {
  331. token = QTD_TOKEN_PID_IN;
  332. } else {
  333. token = QTD_TOKEN_PID_OUT;
  334. }
  335. token |= QTD_TOKEN_STATUS_ACTIVE |
  336. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  337. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  338. if (buflen == 0) {
  339. token |= QTD_TOKEN_IOC;
  340. }
  341. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  342. qtd->urb = urb;
  343. qtd->hw.next_qtd = QTD_LIST_END;
  344. buffer += xfer_len;
  345. if (prev_qtd) {
  346. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  347. } else {
  348. first_qtd = qtd;
  349. }
  350. prev_qtd = qtd;
  351. if (buflen == 0) {
  352. break;
  353. }
  354. qtd_num++;
  355. if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) {
  356. return NULL;
  357. }
  358. }
  359. /* update qh first qtd */
  360. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  361. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  362. /* update data toggle */
  363. if (urb->data_toggle) {
  364. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  365. } else {
  366. qh->hw.overlay.token = 0;
  367. }
  368. /* record qh first qtd */
  369. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  370. flags = usb_osal_enter_critical_section();
  371. qh->urb = urb;
  372. urb->hcpriv = qh;
  373. /* add qh into async list */
  374. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  375. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  376. usb_osal_leave_critical_section(flags);
  377. return qh;
  378. }
  379. static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  380. {
  381. struct ehci_qh_hw *qh = NULL;
  382. struct ehci_qtd_hw *qtd = NULL;
  383. struct ehci_qtd_hw *first_qtd = NULL;
  384. struct ehci_qtd_hw *prev_qtd = NULL;
  385. uint32_t qtd_num = 0;
  386. uint32_t xfer_len = 0;
  387. uint32_t token;
  388. size_t flags;
  389. qh = ehci_qh_alloc(bus);
  390. if (qh == NULL) {
  391. return NULL;
  392. }
  393. ehci_qh_fill(qh,
  394. urb->hport->dev_addr,
  395. urb->ep->bEndpointAddress,
  396. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  397. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  398. USB_GET_MULT(urb->ep->wMaxPacketSize) + 1,
  399. urb->ep->bInterval,
  400. urb->hport->speed,
  401. urb->hport->parent->hub_addr,
  402. urb->hport->port);
  403. while (1) {
  404. qtd = &qh->qtd_pool[qtd_num];
  405. if (buflen > 0x4000) {
  406. xfer_len = 0x4000;
  407. buflen -= 0x4000;
  408. } else {
  409. xfer_len = buflen;
  410. buflen = 0;
  411. }
  412. if (urb->ep->bEndpointAddress & 0x80) {
  413. token = QTD_TOKEN_PID_IN;
  414. } else {
  415. token = QTD_TOKEN_PID_OUT;
  416. }
  417. token |= QTD_TOKEN_STATUS_ACTIVE |
  418. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  419. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  420. if (buflen == 0) {
  421. token |= QTD_TOKEN_IOC;
  422. }
  423. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  424. qtd->urb = urb;
  425. qtd->hw.next_qtd = QTD_LIST_END;
  426. buffer += xfer_len;
  427. if (prev_qtd) {
  428. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  429. } else {
  430. first_qtd = qtd;
  431. }
  432. prev_qtd = qtd;
  433. if (buflen == 0) {
  434. break;
  435. }
  436. qtd_num++;
  437. if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) {
  438. return NULL;
  439. }
  440. }
  441. /* update qh first qtd */
  442. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  443. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  444. /* update data toggle */
  445. if (urb->data_toggle) {
  446. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  447. } else {
  448. qh->hw.overlay.token = 0;
  449. }
  450. /* record qh first qtd */
  451. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  452. flags = usb_osal_enter_critical_section();
  453. qh->urb = urb;
  454. urb->hcpriv = qh;
  455. /* add qh into periodic list */
  456. ehci_qh_add_head(&g_periodic_qh_head[bus->hcd.hcd_id], qh);
  457. EHCI_HCOR->usbcmd |= EHCI_USBCMD_PSEN;
  458. usb_osal_leave_critical_section(flags);
  459. return qh;
  460. }
  461. static void ehci_urb_waitup(struct usbh_bus *bus, struct usbh_urb *urb)
  462. {
  463. struct ehci_qh_hw *qh;
  464. qh = (struct ehci_qh_hw *)urb->hcpriv;
  465. qh->urb = NULL;
  466. urb->hcpriv = NULL;
  467. qh->remove_in_iaad = 0;
  468. if (urb->timeout) {
  469. usb_osal_sem_give(qh->waitsem);
  470. } else {
  471. ehci_qh_free(bus, qh);
  472. }
  473. if (urb->complete) {
  474. if (urb->errorcode < 0) {
  475. urb->complete(urb->arg, urb->errorcode);
  476. } else {
  477. urb->complete(urb->arg, urb->actual_length);
  478. }
  479. }
  480. }
  481. static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  482. {
  483. struct ehci_qtd_hw *qtd;
  484. (void)bus;
  485. ehci_qh_remove(qhead, qh);
  486. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  487. while (qtd) {
  488. qtd->urb->actual_length += (qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT));
  489. qh->first_qtd = qtd->hw.next_qtd;
  490. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  491. }
  492. }
  493. static void ehci_check_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  494. {
  495. struct usbh_urb *urb;
  496. struct ehci_qtd_hw *qtd;
  497. uint32_t token;
  498. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  499. if (qtd == NULL) {
  500. return;
  501. }
  502. while (qtd) {
  503. token = qtd->hw.token;
  504. if (token & QTD_TOKEN_STATUS_ERRORS) {
  505. break;
  506. } else if (token & QTD_TOKEN_STATUS_ACTIVE) {
  507. return;
  508. }
  509. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  510. }
  511. urb = qh->urb;
  512. if ((token & QTD_TOKEN_STATUS_ERRORS) == 0) {
  513. if (token & QTD_TOKEN_TOGGLE) {
  514. urb->data_toggle = true;
  515. } else {
  516. urb->data_toggle = false;
  517. }
  518. urb->errorcode = 0;
  519. } else {
  520. if (token & QTD_TOKEN_STATUS_BABBLE) {
  521. urb->errorcode = -USB_ERR_BABBLE;
  522. urb->data_toggle = 0;
  523. } else if (token & QTD_TOKEN_STATUS_HALTED) {
  524. urb->errorcode = -USB_ERR_STALL;
  525. urb->data_toggle = 0;
  526. } else if (token & (QTD_TOKEN_STATUS_DBERR | QTD_TOKEN_STATUS_XACTERR)) {
  527. urb->errorcode = -USB_ERR_IO;
  528. }
  529. }
  530. ehci_qh_scan_qtds(bus, qhead, qh);
  531. if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  532. ehci_urb_waitup(bus, urb);
  533. } else {
  534. qh->remove_in_iaad = 1;
  535. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  536. }
  537. }
  538. static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  539. {
  540. struct ehci_qtd_hw *qtd;
  541. (void)bus;
  542. ehci_qh_remove(qhead, qh);
  543. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  544. while (qtd) {
  545. qh->first_qtd = qtd->hw.next_qtd;
  546. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  547. }
  548. }
  549. static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port)
  550. {
  551. volatile uint32_t timeout = 0;
  552. uint32_t regval;
  553. #if defined(CONFIG_USB_EHCI_HPMICRO) && CONFIG_USB_EHCI_HPMICRO
  554. if ((*(volatile uint32_t *)(bus->hcd.reg_base + 0x224) & 0xc0) == (2 << 6)) { /* Hardcode for hpm */
  555. EHCI_HCOR->portsc[port - 1] |= (1 << 29);
  556. } else {
  557. EHCI_HCOR->portsc[port - 1] &= ~(1 << 29);
  558. }
  559. #endif
  560. regval = EHCI_HCOR->portsc[port - 1];
  561. regval &= ~EHCI_PORTSC_PE;
  562. regval |= EHCI_PORTSC_RESET;
  563. EHCI_HCOR->portsc[port - 1] = regval;
  564. usb_osal_msleep(55);
  565. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESET;
  566. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESET) != 0) {
  567. usb_osal_msleep(1);
  568. timeout++;
  569. if (timeout > 100) {
  570. return -USB_ERR_TIMEOUT;
  571. }
  572. }
  573. return 0;
  574. }
  575. __WEAK void usb_hc_low_level_init(struct usbh_bus *bus)
  576. {
  577. (void)bus;
  578. }
  579. __WEAK void usb_hc_low_level2_init(struct usbh_bus *bus)
  580. {
  581. (void)bus;
  582. }
  583. __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus)
  584. {
  585. (void)bus;
  586. }
  587. int usb_hc_init(struct usbh_bus *bus)
  588. {
  589. struct ehci_qh_hw *qh;
  590. volatile uint32_t timeout = 0;
  591. uint32_t regval;
  592. memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd));
  593. memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM);
  594. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  595. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  596. if ((uint32_t)&qh->hw % 32) {
  597. USB_LOG_ERR("struct ehci_qh_hw is not align 32\r\n");
  598. return -USB_ERR_INVAL;
  599. }
  600. for (uint8_t i = 0; i < CONFIG_USB_EHCI_QTD_NUM; i++) {
  601. if ((uint32_t)&qh->qtd_pool[i] % 32) {
  602. USB_LOG_ERR("struct ehci_qtd_hw is not align 32\r\n");
  603. return -USB_ERR_INVAL;
  604. }
  605. }
  606. }
  607. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  608. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  609. qh->waitsem = usb_osal_sem_create(0);
  610. }
  611. memset(&g_async_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  612. g_async_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_QH(&g_async_qh_head[bus->hcd.hcd_id]);
  613. g_async_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCHAR_H;
  614. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  615. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  616. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  617. g_async_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  618. memset(g_framelist[bus->hcd.hcd_id], 0, sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE);
  619. memset(&g_periodic_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  620. g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_END;
  621. g_periodic_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCAPS_SSMASK(1);
  622. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  623. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  624. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  625. g_periodic_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  626. for (uint32_t i = 0; i < CONFIG_USB_EHCI_FRAME_LIST_SIZE; i++) {
  627. g_framelist[bus->hcd.hcd_id][i] = QH_HLP_QH(&g_periodic_qh_head[bus->hcd.hcd_id]);
  628. }
  629. usb_hc_low_level_init(bus);
  630. USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion);
  631. USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams);
  632. USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams);
  633. g_ehci_hcd[bus->hcd.hcd_id].ppc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC) ? true : false;
  634. g_ehci_hcd[bus->hcd.hcd_id].n_ports = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;
  635. g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT;
  636. g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT;
  637. g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true;
  638. g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength;
  639. USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n",
  640. g_ehci_hcd[bus->hcd.hcd_id].ppc,
  641. g_ehci_hcd[bus->hcd.hcd_id].n_ports,
  642. g_ehci_hcd[bus->hcd.hcd_id].n_cc,
  643. g_ehci_hcd[bus->hcd.hcd_id].n_pcc);
  644. EHCI_HCOR->usbcmd &= ~EHCI_USBCMD_RUN;
  645. usb_osal_msleep(2);
  646. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  647. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) {
  648. usb_osal_msleep(1);
  649. timeout++;
  650. if (timeout > 100) {
  651. return -USB_ERR_TIMEOUT;
  652. }
  653. }
  654. usb_hc_low_level2_init(bus);
  655. EHCI_HCOR->usbintr = 0;
  656. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  657. /* Set the Current Asynchronous List Address. */
  658. EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]);
  659. /* Set the Periodic Frame List Base Address. */
  660. EHCI_HCOR->periodiclistbase = EHCI_PTR2ADDR(g_framelist[bus->hcd.hcd_id]);
  661. regval = 0;
  662. #if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024
  663. regval |= EHCI_USBCMD_FLSIZE_1024;
  664. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 512
  665. regval |= EHCI_USBCMD_FLSIZE_512;
  666. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 256
  667. regval |= EHCI_USBCMD_FLSIZE_256;
  668. #else
  669. #error Unsupported frame size list size
  670. #endif
  671. regval |= EHCI_USBCMD_ITHRE_1MF;
  672. regval |= EHCI_USBCMD_ASEN;
  673. regval |= EHCI_USBCMD_PSEN;
  674. regval |= EHCI_USBCMD_RUN;
  675. EHCI_HCOR->usbcmd = regval;
  676. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  677. EHCI_HCOR->configflag = EHCI_CONFIGFLAG;
  678. #endif
  679. /* Wait for the EHCI to run (no longer report halted) */
  680. timeout = 0;
  681. while (EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) {
  682. usb_osal_msleep(1);
  683. timeout++;
  684. if (timeout > 100) {
  685. return -USB_ERR_TIMEOUT;
  686. }
  687. }
  688. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  689. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  690. regval = EHCI_HCOR->portsc[port];
  691. regval |= EHCI_PORTSC_PP;
  692. regval &= ~(EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC);
  693. EHCI_HCOR->portsc[port] = regval;
  694. }
  695. }
  696. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  697. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  698. USB_LOG_INFO("EHCI uses tt for ls/fs device, so cannot enable this macro\r\n");
  699. return -USB_ERR_INVAL;
  700. #endif
  701. }
  702. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  703. USB_LOG_INFO("EHCI uses tt for ls/fs device\r\n");
  704. } else {
  705. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  706. USB_LOG_INFO("EHCI uses companion controller for ls/fs device\r\n");
  707. ohci_init(bus);
  708. #else
  709. USB_LOG_WRN("Do not enable companion controller, you should use a hub to support ls/fs device\r\n");
  710. #endif
  711. }
  712. /* Enable EHCI interrupts. */
  713. EHCI_HCOR->usbintr = EHCI_USBIE_INT | EHCI_USBIE_ERR | EHCI_USBIE_PCD | EHCI_USBIE_FATAL | EHCI_USBIE_IAA;
  714. return 0;
  715. }
  716. int usb_hc_deinit(struct usbh_bus *bus)
  717. {
  718. struct ehci_qh_hw *qh;
  719. volatile uint32_t timeout = 0;
  720. uint32_t regval;
  721. EHCI_HCOR->usbintr = 0;
  722. regval = EHCI_HCOR->usbcmd;
  723. regval &= ~EHCI_USBCMD_ASEN;
  724. regval &= ~EHCI_USBCMD_PSEN;
  725. regval &= ~EHCI_USBCMD_RUN;
  726. EHCI_HCOR->usbcmd = regval;
  727. while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS)) || ((EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) == 0)) {
  728. usb_osal_msleep(1);
  729. timeout++;
  730. if (timeout > 100) {
  731. return -USB_ERR_TIMEOUT;
  732. }
  733. }
  734. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  735. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  736. regval = EHCI_HCOR->portsc[port];
  737. regval &= ~EHCI_PORTSC_PP;
  738. EHCI_HCOR->portsc[port] = regval;
  739. }
  740. }
  741. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  742. EHCI_HCOR->configflag = 0;
  743. #endif
  744. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  745. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  746. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  747. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  748. usb_osal_sem_delete(qh->waitsem);
  749. }
  750. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  751. ohci_deinit(bus);
  752. #endif
  753. usb_hc_low_level_deinit(bus);
  754. return 0;
  755. }
  756. uint16_t usbh_get_frame_number(struct usbh_bus *bus)
  757. {
  758. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  759. if (EHCI_HCOR->portsc[0] & EHCI_PORTSC_OWNER) {
  760. return ohci_get_frame_number(bus);
  761. }
  762. #endif
  763. return (((EHCI_HCOR->frindex & EHCI_FRINDEX_MASK) >> 3) & 0x3ff);
  764. }
  765. int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf)
  766. {
  767. uint8_t nports;
  768. uint8_t port;
  769. uint32_t temp, status;
  770. nports = g_ehci_hcd[bus->hcd.hcd_id].n_ports;
  771. port = setup->wIndex;
  772. temp = EHCI_HCOR->portsc[port - 1];
  773. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  774. if (temp & EHCI_PORTSC_OWNER) {
  775. return ohci_roothub_control(bus, setup, buf);
  776. }
  777. if ((temp & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) {
  778. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  779. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  780. }
  781. return ohci_roothub_control(bus, setup, buf);
  782. }
  783. #endif
  784. if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) {
  785. switch (setup->bRequest) {
  786. case HUB_REQUEST_CLEAR_FEATURE:
  787. switch (setup->wValue) {
  788. case HUB_FEATURE_HUB_C_LOCALPOWER:
  789. break;
  790. case HUB_FEATURE_HUB_C_OVERCURRENT:
  791. break;
  792. default:
  793. return -USB_ERR_NOTSUPP;
  794. }
  795. break;
  796. case HUB_REQUEST_SET_FEATURE:
  797. switch (setup->wValue) {
  798. case HUB_FEATURE_HUB_C_LOCALPOWER:
  799. break;
  800. case HUB_FEATURE_HUB_C_OVERCURRENT:
  801. break;
  802. default:
  803. return -USB_ERR_NOTSUPP;
  804. }
  805. break;
  806. case HUB_REQUEST_GET_DESCRIPTOR:
  807. break;
  808. case HUB_REQUEST_GET_STATUS:
  809. memset(buf, 0, 4);
  810. break;
  811. default:
  812. break;
  813. }
  814. } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) {
  815. switch (setup->bRequest) {
  816. case HUB_REQUEST_CLEAR_FEATURE:
  817. if (!port || port > nports) {
  818. return -USB_ERR_INVAL;
  819. }
  820. switch (setup->wValue) {
  821. case HUB_PORT_FEATURE_ENABLE:
  822. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PE;
  823. break;
  824. case HUB_PORT_FEATURE_SUSPEND:
  825. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_RESUME;
  826. usb_osal_msleep(20);
  827. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESUME;
  828. while (EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESUME) {
  829. }
  830. temp = EHCI_HCOR->usbcmd;
  831. temp |= EHCI_USBCMD_ASEN;
  832. temp |= EHCI_USBCMD_PSEN;
  833. temp |= EHCI_USBCMD_RUN;
  834. EHCI_HCOR->usbcmd = temp;
  835. while ((EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) == 0) {
  836. }
  837. case HUB_PORT_FEATURE_C_SUSPEND:
  838. break;
  839. case HUB_PORT_FEATURE_POWER:
  840. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PP;
  841. break;
  842. case HUB_PORT_FEATURE_C_CONNECTION:
  843. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_CSC;
  844. break;
  845. case HUB_PORT_FEATURE_C_ENABLE:
  846. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PEC;
  847. break;
  848. case HUB_PORT_FEATURE_C_OVER_CURREN:
  849. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OCC;
  850. break;
  851. case HUB_PORT_FEATURE_C_RESET:
  852. break;
  853. default:
  854. return -USB_ERR_NOTSUPP;
  855. }
  856. break;
  857. case HUB_REQUEST_SET_FEATURE:
  858. if (!port || port > nports) {
  859. return -USB_ERR_INVAL;
  860. }
  861. switch (setup->wValue) {
  862. case HUB_PORT_FEATURE_SUSPEND:
  863. temp = EHCI_HCOR->usbcmd;
  864. temp &= ~EHCI_USBCMD_ASEN;
  865. temp &= ~EHCI_USBCMD_PSEN;
  866. temp &= ~EHCI_USBCMD_RUN;
  867. EHCI_HCOR->usbcmd = temp;
  868. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) {
  869. }
  870. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_SUSPEND;
  871. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_SUSPEND) == 0) {
  872. }
  873. break;
  874. case HUB_PORT_FEATURE_POWER:
  875. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PP;
  876. break;
  877. case HUB_PORT_FEATURE_RESET:
  878. usbh_reset_port(bus, port);
  879. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  880. if (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_PE)) {
  881. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  882. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  883. }
  884. return ohci_roothub_control(bus, setup, buf);
  885. }
  886. #endif
  887. break;
  888. default:
  889. return -USB_ERR_NOTSUPP;
  890. }
  891. break;
  892. case HUB_REQUEST_GET_STATUS:
  893. if (!port || port > nports) {
  894. return -USB_ERR_INVAL;
  895. }
  896. temp = EHCI_HCOR->portsc[port - 1];
  897. status = 0;
  898. if (temp & EHCI_PORTSC_CSC) {
  899. status |= (1 << HUB_PORT_FEATURE_C_CONNECTION);
  900. }
  901. if (temp & EHCI_PORTSC_PEC) {
  902. status |= (1 << HUB_PORT_FEATURE_C_ENABLE);
  903. }
  904. if (temp & EHCI_PORTSC_OCC) {
  905. status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN);
  906. }
  907. if (temp & EHCI_PORTSC_CCS) {
  908. status |= (1 << HUB_PORT_FEATURE_CONNECTION);
  909. }
  910. if (temp & EHCI_PORTSC_PE) {
  911. status |= (1 << HUB_PORT_FEATURE_ENABLE);
  912. if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) {
  913. status |= (1 << HUB_PORT_FEATURE_LOWSPEED);
  914. } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) {
  915. status |= (1 << HUB_PORT_FEATURE_HIGHSPEED);
  916. }
  917. }
  918. if (temp & EHCI_PORTSC_SUSPEND) {
  919. status |= (1 << HUB_PORT_FEATURE_SUSPEND);
  920. }
  921. if (temp & EHCI_PORTSC_OCA) {
  922. status |= (1 << HUB_PORT_FEATURE_OVERCURRENT);
  923. }
  924. if (temp & EHCI_PORTSC_RESET) {
  925. status |= (1 << HUB_PORT_FEATURE_RESET);
  926. }
  927. if (temp & EHCI_PORTSC_PP || !(EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC)) {
  928. status |= (1 << HUB_PORT_FEATURE_POWER);
  929. }
  930. memcpy(buf, &status, 4);
  931. break;
  932. default:
  933. break;
  934. }
  935. }
  936. return 0;
  937. }
  938. int usbh_submit_urb(struct usbh_urb *urb)
  939. {
  940. struct ehci_qh_hw *qh = NULL;
  941. size_t flags;
  942. int ret = 0;
  943. struct usbh_hub *hub;
  944. struct usbh_hubport *hport;
  945. struct usbh_bus *bus;
  946. if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) {
  947. return -USB_ERR_INVAL;
  948. }
  949. bus = urb->hport->bus;
  950. /* find active hubport in roothub */
  951. hport = urb->hport;
  952. hub = urb->hport->parent;
  953. while (!hub->is_roothub) {
  954. hport = hub->parent;
  955. hub = hub->parent->parent;
  956. }
  957. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  958. if (EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_OWNER) {
  959. return ohci_submit_urb(urb);
  960. }
  961. #endif
  962. if (!urb->hport->connected || !(EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_CCS)) {
  963. return -USB_ERR_NOTCONN;
  964. }
  965. if (urb->errorcode == -USB_ERR_BUSY) {
  966. return -USB_ERR_BUSY;
  967. }
  968. flags = usb_osal_enter_critical_section();
  969. urb->hcpriv = NULL;
  970. urb->errorcode = -USB_ERR_BUSY;
  971. urb->actual_length = 0;
  972. usb_osal_leave_critical_section(flags);
  973. switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
  974. case USB_ENDPOINT_TYPE_CONTROL:
  975. qh = ehci_control_urb_init(bus, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length);
  976. if (qh == NULL) {
  977. return -USB_ERR_NOMEM;
  978. }
  979. break;
  980. case USB_ENDPOINT_TYPE_BULK:
  981. qh = ehci_bulk_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  982. if (qh == NULL) {
  983. return -USB_ERR_NOMEM;
  984. }
  985. break;
  986. case USB_ENDPOINT_TYPE_INTERRUPT:
  987. qh = ehci_intr_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  988. if (qh == NULL) {
  989. return -USB_ERR_NOMEM;
  990. }
  991. break;
  992. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  993. #ifdef CONFIG_USB_EHCI_ISO
  994. ret = ehci_iso_urb_init(bus, urb);
  995. #endif
  996. break;
  997. default:
  998. break;
  999. }
  1000. if (urb->timeout > 0) {
  1001. /* wait until timeout or sem give */
  1002. ret = usb_osal_sem_take(qh->waitsem, urb->timeout);
  1003. if (ret < 0) {
  1004. goto errout_timeout;
  1005. }
  1006. urb->timeout = 0;
  1007. ret = urb->errorcode;
  1008. /* we can free qh when waitsem is done */
  1009. ehci_qh_free(bus, qh);
  1010. }
  1011. return ret;
  1012. errout_timeout:
  1013. urb->timeout = 0;
  1014. usbh_kill_urb(urb);
  1015. return ret;
  1016. }
  1017. int usbh_kill_urb(struct usbh_urb *urb)
  1018. {
  1019. struct ehci_qh_hw *qh;
  1020. struct usbh_bus *bus;
  1021. size_t flags;
  1022. bool remove_in_iaad = false;
  1023. if (!urb || !urb->hport || !urb->hcpriv || !urb->hport->bus) {
  1024. return -USB_ERR_INVAL;
  1025. }
  1026. bus = urb->hport->bus;
  1027. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  1028. if (EHCI_HCOR->portsc[urb->hport->port - 1] & EHCI_PORTSC_OWNER) {
  1029. return ohci_kill_urb(urb);
  1030. }
  1031. #endif
  1032. flags = usb_osal_enter_critical_section();
  1033. EHCI_HCOR->usbcmd &= ~(EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1034. if ((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) || (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_BULK)) {
  1035. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1036. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1037. if (qh->urb == urb) {
  1038. remove_in_iaad = true;
  1039. ehci_kill_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1040. }
  1041. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1042. }
  1043. } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  1044. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1045. while (qh) {
  1046. if (qh->urb == urb) {
  1047. ehci_kill_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1048. }
  1049. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1050. }
  1051. } else {
  1052. #ifdef CONFIG_USB_EHCI_ISO
  1053. ehci_kill_iso_urb(bus, urb);
  1054. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1055. usb_osal_leave_critical_section(flags);
  1056. return 0;
  1057. #endif
  1058. }
  1059. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1060. qh = (struct ehci_qh_hw *)urb->hcpriv;
  1061. urb->hcpriv = NULL;
  1062. urb->errorcode = -USB_ERR_SHUTDOWN;
  1063. qh->urb = NULL;
  1064. if (urb->timeout) {
  1065. usb_osal_sem_give(qh->waitsem);
  1066. } else {
  1067. ehci_qh_free(bus, qh);
  1068. }
  1069. if (remove_in_iaad) {
  1070. volatile uint32_t timeout = 0;
  1071. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  1072. while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) {
  1073. usb_osal_msleep(1);
  1074. timeout++;
  1075. if (timeout > 100) {
  1076. usb_osal_leave_critical_section(flags);
  1077. return -USB_ERR_TIMEOUT;
  1078. }
  1079. }
  1080. EHCI_HCOR->usbsts = EHCI_USBSTS_IAA;
  1081. }
  1082. usb_osal_leave_critical_section(flags);
  1083. return 0;
  1084. }
  1085. static void ehci_scan_async_list(struct usbh_bus *bus)
  1086. {
  1087. struct ehci_qh_hw *qh;
  1088. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1089. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1090. if (qh->urb) {
  1091. ehci_check_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1092. }
  1093. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1094. }
  1095. }
  1096. static void ehci_scan_periodic_list(struct usbh_bus *bus)
  1097. {
  1098. struct ehci_qh_hw *qh;
  1099. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1100. while (qh) {
  1101. if (qh->urb) {
  1102. ehci_check_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1103. }
  1104. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1105. }
  1106. }
  1107. void USBH_IRQHandler(uint8_t busid)
  1108. {
  1109. uint32_t usbsts;
  1110. struct usbh_bus *bus;
  1111. bus = &g_usbhost_bus[busid];
  1112. usbsts = EHCI_HCOR->usbsts & EHCI_HCOR->usbintr;
  1113. EHCI_HCOR->usbsts = usbsts;
  1114. if (usbsts & EHCI_USBSTS_INT) {
  1115. ehci_scan_async_list(bus);
  1116. ehci_scan_periodic_list(bus);
  1117. #ifdef CONFIG_USB_EHCI_ISO
  1118. ehci_scan_isochronous_list(bus);
  1119. #endif
  1120. }
  1121. if (usbsts & EHCI_USBSTS_ERR) {
  1122. ehci_scan_async_list(bus);
  1123. ehci_scan_periodic_list(bus);
  1124. #ifdef CONFIG_USB_EHCI_ISO
  1125. ehci_scan_isochronous_list(bus);
  1126. #endif
  1127. }
  1128. if (usbsts & EHCI_USBSTS_PCD) {
  1129. for (int port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  1130. uint32_t portsc = EHCI_HCOR->portsc[port];
  1131. if (portsc & EHCI_PORTSC_CSC) {
  1132. if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) {
  1133. } else {
  1134. #if defined(CONFIG_USB_EHCI_NXP)
  1135. /* kUSB_ControllerEhci0 and kUSB_ControllerEhci1*/
  1136. extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable);
  1137. USB_EhcihostPhyDisconnectDetectCmd(2 + busid, 0);
  1138. #endif
  1139. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1140. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] = false;
  1141. }
  1142. for (uint8_t index = 0; index < CONFIG_USB_EHCI_ISO_NUM; index++) {
  1143. g_ehci_hcd[bus->hcd.hcd_id].ehci_iso_used[index] = false;
  1144. }
  1145. }
  1146. bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1));
  1147. usbh_hub_thread_wakeup(&bus->hcd.roothub);
  1148. }
  1149. }
  1150. }
  1151. if (usbsts & EHCI_USBSTS_IAA) {
  1152. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1153. struct ehci_qh_hw *qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  1154. if (g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] && qh->remove_in_iaad) {
  1155. ehci_urb_waitup(bus, qh->urb);
  1156. }
  1157. }
  1158. }
  1159. if (usbsts & EHCI_USBSTS_FATAL) {
  1160. }
  1161. }