drv_rtc.c 3.5 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-01-25 iysheng first version
  9. */
  10. #include <board.h>
  11. #include <sys/time.h>
  12. #define DBG_TAG "drv.rtc"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. #ifdef RT_USING_RTC
  16. typedef struct {
  17. struct rt_device rtc_dev;
  18. } gd32_rtc_device;
  19. static gd32_rtc_device g_gd32_rtc_dev;
  20. static time_t get_rtc_timestamp(void)
  21. {
  22. time_t rtc_counter;
  23. rtc_counter = (time_t)rtc_counter_get();
  24. return rtc_counter;
  25. }
  26. static rt_err_t set_rtc_timestamp(time_t time_stamp)
  27. {
  28. uint32_t rtc_counter;
  29. rtc_counter = (uint32_t)time_stamp;
  30. /* wait until LWOFF bit in RTC_CTL to 1 */
  31. rtc_lwoff_wait();
  32. /* enter configure mode */
  33. rtc_configuration_mode_enter();
  34. /* write data to rtc register */
  35. rtc_counter_set(rtc_counter);
  36. /* exit configure mode */
  37. rtc_configuration_mode_exit();
  38. /* wait until LWOFF bit in RTC_CTL to 1 */
  39. rtc_lwoff_wait();
  40. return RT_EOK;
  41. }
  42. static rt_err_t rt_gd32_rtc_control(rt_device_t dev, int cmd, void *args)
  43. {
  44. rt_err_t result = RT_EOK;
  45. RT_ASSERT(dev != RT_NULL);
  46. switch (cmd)
  47. {
  48. case RT_DEVICE_CTRL_RTC_GET_TIME:
  49. *(rt_uint32_t *)args = get_rtc_timestamp();
  50. break;
  51. case RT_DEVICE_CTRL_RTC_SET_TIME:
  52. if (set_rtc_timestamp(*(rt_uint32_t *)args))
  53. {
  54. result = -RT_ERROR;
  55. }
  56. break;
  57. }
  58. return result;
  59. }
  60. #ifdef RT_USING_DEVICE_OPS
  61. const static struct rt_device_ops g_gd32_rtc_ops =
  62. {
  63. RT_NULL,
  64. RT_NULL,
  65. RT_NULL,
  66. RT_NULL,
  67. RT_NULL,
  68. rt_gd32_rtc_control
  69. };
  70. #endif
  71. static int rt_hw_rtc_init(void)
  72. {
  73. rt_err_t ret;
  74. time_t rtc_counter;
  75. rcu_periph_clock_enable(RCU_PMU);
  76. pmu_backup_write_enable();
  77. rcu_periph_clock_enable(RCU_BKPI);
  78. rtc_counter = get_rtc_timestamp();
  79. /* once the rtc clock source has been selected, if can't be changed
  80. * anymore unless the Backup domain is reset */
  81. rcu_bkp_reset_enable();
  82. rcu_bkp_reset_disable();
  83. rcu_periph_clock_enable(RCU_RTC);
  84. #if defined(BSP_RTC_USING_LSE)
  85. rcu_osci_on(RCU_LXTAL);
  86. if (SUCCESS == rcu_osci_stab_wait(RCU_LXTAL))
  87. {
  88. /* set lxtal as rtc clock source */
  89. rcu_rtc_clock_config(RCU_RTCSRC_LXTAL);
  90. }
  91. #elif defined(BSP_RTC_USING_LSI)
  92. rcu_osci_on(RCU_IRC40K);
  93. if (SUCCESS == rcu_osci_stab_wait(RCU_IRC40K))
  94. {
  95. /* set IRC40K as rtc clock source */
  96. rcu_rtc_clock_config(RCU_RTCSRC_IRC40K);
  97. }
  98. #endif
  99. set_rtc_timestamp(rtc_counter);
  100. #ifdef RT_USING_DEVICE_OPS
  101. g_gd32_rtc_dev.rtc_dev.ops = &g_gd32_rtc_ops;
  102. #else
  103. g_gd32_rtc_dev.rtc_dev.init = RT_NULL;
  104. g_gd32_rtc_dev.rtc_dev.open = RT_NULL;
  105. g_gd32_rtc_dev.rtc_dev.close = RT_NULL;
  106. g_gd32_rtc_dev.rtc_dev.read = RT_NULL;
  107. g_gd32_rtc_dev.rtc_dev.write = RT_NULL;
  108. g_gd32_rtc_dev.rtc_dev.control = rt_gd32_rtc_control;
  109. #endif
  110. g_gd32_rtc_dev.rtc_dev.type = RT_Device_Class_RTC;
  111. g_gd32_rtc_dev.rtc_dev.rx_indicate = RT_NULL;
  112. g_gd32_rtc_dev.rtc_dev.tx_complete = RT_NULL;
  113. g_gd32_rtc_dev.rtc_dev.user_data = RT_NULL;
  114. ret = rt_device_register(&g_gd32_rtc_dev.rtc_dev, "rtc", \
  115. RT_DEVICE_FLAG_RDWR);
  116. if (ret != RT_EOK)
  117. {
  118. LOG_E("failed register internal rtc device, err=%d", ret);
  119. }
  120. return ret;
  121. }
  122. INIT_DEVICE_EXPORT(rt_hw_rtc_init);
  123. #endif