drv_usart.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246
  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-07-23 tyustli first version
  9. */
  10. #include <drv_usart.h>
  11. #ifdef RT_USING_SERIAL
  12. #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
  13. && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
  14. #error "Please define at least one BSP_USING_UARTx"
  15. /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
  16. #endif
  17. struct gd32_usart {
  18. char *name;
  19. rt_uint32_t usart_base;
  20. rt_uint32_t usart_clk;
  21. rt_uint32_t gpio_clk;
  22. rt_uint32_t gpio_port;
  23. rt_uint32_t tx_pin;
  24. rt_uint32_t rx_pin;
  25. IRQn_Type irqn;
  26. struct rt_serial_device serial;
  27. };
  28. enum {
  29. #ifdef BSP_USING_UART0
  30. GDUSART0_INDEX,
  31. #endif
  32. };
  33. static struct gd32_usart usart_config[] = {
  34. #ifdef BSP_USING_UART0
  35. { "uart0",
  36. USART0,
  37. RCU_USART0,
  38. RCU_GPIOA,
  39. GPIOA,
  40. GPIO_PIN_9,
  41. GPIO_PIN_10,
  42. USART0_IRQn, },
  43. #endif
  44. };
  45. static rt_err_t gd32_configure(struct rt_serial_device *serial,
  46. struct serial_configure *cfg) {
  47. struct gd32_usart *usart;
  48. RT_ASSERT(serial != RT_NULL);
  49. RT_ASSERT(cfg != RT_NULL);
  50. usart = (struct gd32_usart *) serial->parent.user_data;
  51. RT_ASSERT(usart != RT_NULL);
  52. /* enable GPIO clock */
  53. rcu_periph_clock_enable(usart->gpio_clk);
  54. /* enable USART clock */
  55. rcu_periph_clock_enable(usart->usart_clk);
  56. /* connect port to USARTx_Tx */
  57. gpio_init(usart->gpio_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
  58. usart->tx_pin);
  59. /* connect port to USARTx_Rx */
  60. gpio_init(usart->gpio_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ,
  61. usart->rx_pin);
  62. usart_deinit(usart->usart_base);
  63. usart_baudrate_set(usart->usart_base, cfg->baud_rate);
  64. switch (cfg->data_bits) {
  65. case DATA_BITS_8:
  66. usart_word_length_set(usart->usart_base, USART_WL_8BIT);
  67. break;
  68. case DATA_BITS_9:
  69. usart_word_length_set(usart->usart_base, USART_WL_9BIT);
  70. break;
  71. default:
  72. usart_word_length_set(usart->usart_base, USART_WL_8BIT);
  73. break;
  74. }
  75. switch (cfg->stop_bits) {
  76. case STOP_BITS_1:
  77. usart_stop_bit_set(usart->usart_base, USART_STB_1BIT);
  78. break;
  79. case STOP_BITS_2:
  80. usart_stop_bit_set(usart->usart_base, USART_STB_2BIT);
  81. break;
  82. default:
  83. usart_stop_bit_set(usart->usart_base, USART_STB_1BIT);
  84. break;
  85. }
  86. switch (cfg->parity) {
  87. case PARITY_NONE:
  88. usart_parity_config(usart->usart_base, USART_PM_NONE);
  89. break;
  90. case PARITY_ODD:
  91. usart_parity_config(usart->usart_base, USART_PM_ODD);
  92. break;
  93. case PARITY_EVEN:
  94. usart_parity_config(usart->usart_base, USART_PM_EVEN);
  95. break;
  96. default:
  97. usart_parity_config(usart->usart_base, USART_PM_NONE);
  98. break;
  99. }
  100. usart_hardware_flow_rts_config(usart->usart_base, USART_RTS_DISABLE);
  101. usart_hardware_flow_cts_config(usart->usart_base, USART_RTS_DISABLE);
  102. usart_receive_config(usart->usart_base, USART_RECEIVE_ENABLE);
  103. usart_transmit_config(usart->usart_base, USART_TRANSMIT_ENABLE);
  104. usart_enable(usart->usart_base);
  105. return RT_EOK;
  106. }
  107. static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd,
  108. void *arg) {
  109. struct gd32_usart *usart;
  110. RT_ASSERT(serial != RT_NULL);
  111. usart = (struct gd32_usart *) serial->parent.user_data;
  112. RT_ASSERT(usart != RT_NULL);
  113. switch (cmd) {
  114. case RT_DEVICE_CTRL_CLR_INT:
  115. eclic_irq_disable(usart->usart_base);
  116. usart_interrupt_disable(usart->usart_base, USART_INT_RBNE);
  117. break;
  118. case RT_DEVICE_CTRL_SET_INT:
  119. eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1);
  120. eclic_irq_enable(usart->irqn, 1, 0);
  121. /* enable USART0 receive interrupt */
  122. usart_interrupt_enable(usart->usart_base, USART_INT_RBNE);
  123. break;
  124. }
  125. return RT_EOK;
  126. }
  127. static int gd32_putc(struct rt_serial_device *serial, char ch) {
  128. struct gd32_usart *usart;
  129. RT_ASSERT(serial != RT_NULL);
  130. usart = (struct gd32_usart *) serial->parent.user_data;
  131. RT_ASSERT(usart != RT_NULL);
  132. usart_data_transmit(usart->usart_base, (uint8_t) ch);
  133. while (usart_flag_get(usart->usart_base, USART_FLAG_TBE) == RESET)
  134. ;
  135. return 1;
  136. }
  137. static int gd32_getc(struct rt_serial_device *serial) {
  138. int ch;
  139. struct gd32_usart *usart;
  140. RT_ASSERT(serial != RT_NULL);
  141. usart = (struct gd32_usart *) serial->parent.user_data;
  142. RT_ASSERT(usart != RT_NULL);
  143. ch = -1;
  144. if (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE)) {
  145. ch = usart_data_receive(usart->usart_base) & 0xff;
  146. }
  147. return ch;
  148. }
  149. static const struct rt_uart_ops gd32_usart_ops = { gd32_configure, gd32_control,
  150. gd32_putc, gd32_getc,
  151. RT_NULL };
  152. static void usart_isr(struct rt_serial_device *serial) {
  153. struct gd32_usart *usart;
  154. RT_ASSERT(serial != RT_NULL);
  155. usart = (struct gd32_usart *) serial->parent.user_data;
  156. RT_ASSERT(usart != RT_NULL);
  157. if ((usart_interrupt_flag_get(usart->usart_base, USART_INT_FLAG_RBNE)
  158. != RESET)
  159. && (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE))) {
  160. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  161. usart_interrupt_flag_clear(usart->usart_base, USART_INT_FLAG_RBNE);
  162. usart_flag_clear(usart->usart_base, USART_FLAG_RBNE);
  163. } else {
  164. if (usart_flag_get(usart->usart_base, USART_FLAG_CTSF) != RESET) {
  165. usart_flag_clear(usart->usart_base, USART_FLAG_CTSF);
  166. }
  167. if (usart_flag_get(usart->usart_base, USART_FLAG_LBDF) != RESET) {
  168. usart_flag_clear(usart->usart_base, USART_FLAG_LBDF);
  169. }
  170. if (usart_flag_get(usart->usart_base, USART_FLAG_TC) != RESET) {
  171. usart_flag_clear(usart->usart_base, USART_FLAG_TC);
  172. }
  173. }
  174. }
  175. #ifdef BSP_USING_UART0
  176. void USART0_IRQHandler(void) {
  177. rt_interrupt_enter();
  178. usart_isr(&usart_config[GDUSART0_INDEX].serial);
  179. rt_interrupt_leave();
  180. }
  181. #endif
  182. int rt_hw_usart_init(void) {
  183. rt_size_t obj_num;
  184. int index;
  185. obj_num = sizeof(usart_config) / sizeof(struct gd32_usart);
  186. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  187. rt_err_t result = 0;
  188. for (index = 0; index < obj_num; index++) {
  189. usart_config[index].serial.ops = &gd32_usart_ops;
  190. usart_config[index].serial.config = config;
  191. /* register UART device */
  192. result = rt_hw_serial_register(&usart_config[index].serial,
  193. usart_config[index].name,
  194. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
  195. | RT_DEVICE_FLAG_INT_TX, &usart_config[index]);
  196. RT_ASSERT(result == RT_EOK);
  197. }
  198. return result;
  199. }
  200. #endif /* RT_USING_SERIAL */
  201. /******************** end of file *******************/