trap.c 8.1 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2013-07-20 Bernard first version
  9. */
  10. #include <rtthread.h>
  11. #include <rthw.h>
  12. #include <board.h>
  13. #include <armv8.h>
  14. #include "interrupt.h"
  15. #include "mm_aspace.h"
  16. #include <backtrace.h>
  17. void rt_unwind(struct rt_hw_exp_stack *regs, int pc_adj)
  18. {
  19. }
  20. #ifdef RT_USING_FINSH
  21. extern long list_thread(void);
  22. #endif
  23. #ifdef RT_USING_LWP
  24. #include <lwp.h>
  25. #include <lwp_arch.h>
  26. #ifdef LWP_USING_CORE_DUMP
  27. #include <lwp_core_dump.h>
  28. #endif
  29. void sys_exit(int value);
  30. void check_user_fault(struct rt_hw_exp_stack *regs, uint32_t pc_adj, char *info)
  31. {
  32. uint32_t mode = regs->cpsr;
  33. if ((mode & 0x1f) == 0x00)
  34. {
  35. rt_kprintf("%s! pc = 0x%08x\n", info, regs->pc - pc_adj);
  36. #ifdef LWP_USING_CORE_DUMP
  37. lwp_core_dump(regs, pc_adj);
  38. #endif
  39. backtrace((unsigned long)regs->pc, (unsigned long)regs->x30, (unsigned long)regs->x29);
  40. sys_exit(-1);
  41. }
  42. }
  43. int _get_type(unsigned long esr)
  44. {
  45. int ret;
  46. int fsc = esr & 0x3f;
  47. switch (fsc)
  48. {
  49. case 0x4:
  50. case 0x5:
  51. case 0x6:
  52. case 0x7:
  53. ret = MM_FAULT_TYPE_PAGE_FAULT;
  54. break;
  55. case 0x9:
  56. case 0xa:
  57. case 0xb:
  58. ret = MM_FAULT_TYPE_ACCESS_FAULT;
  59. break;
  60. default:
  61. ret = MM_FAULT_TYPE_GENERIC;
  62. }
  63. return ret;
  64. }
  65. int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
  66. {
  67. unsigned char ec;
  68. void *dfar;
  69. int ret = 0;
  70. ec = (unsigned char)((esr >> 26) & 0x3fU);
  71. enum rt_mm_fault_op fault_op;
  72. enum rt_mm_fault_type fault_type;
  73. struct rt_lwp *lwp;
  74. switch (ec)
  75. {
  76. case 0x20:
  77. fault_op = MM_FAULT_OP_EXECUTE;
  78. fault_type = _get_type(esr);
  79. break;
  80. case 0x21:
  81. case 0x24:
  82. case 0x25:
  83. fault_op = MM_FAULT_OP_WRITE;
  84. fault_type = _get_type(esr);
  85. break;
  86. default:
  87. fault_op = 0;
  88. break;
  89. }
  90. if (fault_op)
  91. {
  92. asm volatile("mrs %0, far_el1":"=r"(dfar));
  93. struct rt_aspace_fault_msg msg = {
  94. .fault_op = fault_op,
  95. .fault_type = fault_type,
  96. .fault_vaddr = dfar,
  97. };
  98. lwp = lwp_self();
  99. RT_ASSERT(lwp);
  100. if (rt_aspace_fault_try_fix(lwp->aspace, &msg))
  101. {
  102. ret = 1;
  103. }
  104. }
  105. return ret;
  106. }
  107. #endif
  108. /**
  109. * this function will show registers of CPU
  110. *
  111. * @param regs the registers point
  112. */
  113. void rt_hw_show_register(struct rt_hw_exp_stack *regs)
  114. {
  115. rt_kprintf("Execption:\n");
  116. rt_kprintf("X00:0x%16.16p X01:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)regs->x1, (void *)regs->x2, (void *)regs->x3);
  117. rt_kprintf("X04:0x%16.16p X05:0x%16.16p X06:0x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7);
  118. rt_kprintf("X08:0x%16.16p X09:0x%16.16p X10:0x%16.16p X11:0x%16.16p\n", (void *)regs->x8, (void *)regs->x9, (void *)regs->x10, (void *)regs->x11);
  119. rt_kprintf("X12:0x%16.16p X13:0x%16.16p X14:0x%16.16p X15:0x%16.16p\n", (void *)regs->x12, (void *)regs->x13, (void *)regs->x14, (void *)regs->x15);
  120. rt_kprintf("X16:0x%16.16p X17:0x%16.16p X18:0x%16.16p X19:0x%16.16p\n", (void *)regs->x16, (void *)regs->x17, (void *)regs->x18, (void *)regs->x19);
  121. rt_kprintf("X20:0x%16.16p X21:0x%16.16p X22:0x%16.16p X23:0x%16.16p\n", (void *)regs->x20, (void *)regs->x21, (void *)regs->x22, (void *)regs->x23);
  122. rt_kprintf("X24:0x%16.16p X25:0x%16.16p X26:0x%16.16p X27:0x%16.16p\n", (void *)regs->x24, (void *)regs->x25, (void *)regs->x26, (void *)regs->x27);
  123. rt_kprintf("X28:0x%16.16p X29:0x%16.16p X30:0x%16.16p\n", (void *)regs->x28, (void *)regs->x29, (void *)regs->x30);
  124. rt_kprintf("SP_EL0:0x%16.16p\n", (void *)regs->sp_el0);
  125. rt_kprintf("SPSR :0x%16.16p\n", (void *)regs->cpsr);
  126. rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc);
  127. }
  128. void rt_hw_trap_irq(void)
  129. {
  130. #ifdef SOC_BCM283x
  131. extern rt_uint8_t core_timer_flag;
  132. void *param;
  133. uint32_t irq;
  134. rt_isr_handler_t isr_func;
  135. extern struct rt_irq_desc isr_table[];
  136. uint32_t value = 0;
  137. value = IRQ_PEND_BASIC & 0x3ff;
  138. if(core_timer_flag != 0)
  139. {
  140. uint32_t cpu_id = rt_hw_cpu_id();
  141. uint32_t int_source = CORE_IRQSOURCE(cpu_id);
  142. if (int_source & 0x0f)
  143. {
  144. if (int_source & 0x08)
  145. {
  146. isr_func = isr_table[IRQ_ARM_TIMER].handler;
  147. #ifdef RT_USING_INTERRUPT_INFO
  148. isr_table[IRQ_ARM_TIMER].counter++;
  149. #endif
  150. if (isr_func)
  151. {
  152. param = isr_table[IRQ_ARM_TIMER].param;
  153. isr_func(IRQ_ARM_TIMER, param);
  154. }
  155. }
  156. }
  157. }
  158. /* local interrupt*/
  159. if (value)
  160. {
  161. if (value & (1 << 8))
  162. {
  163. value = IRQ_PEND1;
  164. irq = __rt_ffs(value) - 1;
  165. }
  166. else if (value & (1 << 9))
  167. {
  168. value = IRQ_PEND2;
  169. irq = __rt_ffs(value) + 31;
  170. }
  171. else
  172. {
  173. value &= 0x0f;
  174. irq = __rt_ffs(value) + 63;
  175. }
  176. /* get interrupt service routine */
  177. isr_func = isr_table[irq].handler;
  178. #ifdef RT_USING_INTERRUPT_INFO
  179. isr_table[irq].counter++;
  180. #endif
  181. if (isr_func)
  182. {
  183. /* Interrupt for myself. */
  184. param = isr_table[irq].param;
  185. /* turn to interrupt service routine */
  186. isr_func(irq, param);
  187. }
  188. }
  189. #else
  190. void *param;
  191. int ir, ir_self;
  192. rt_isr_handler_t isr_func;
  193. extern struct rt_irq_desc isr_table[];
  194. ir = rt_hw_interrupt_get_irq();
  195. if (ir == 1023)
  196. {
  197. /* Spurious interrupt */
  198. return;
  199. }
  200. /* bit 10~12 is cpuid, bit 0~9 is interrupt id */
  201. ir_self = ir & 0x3ffUL;
  202. /* get interrupt service routine */
  203. isr_func = isr_table[ir_self].handler;
  204. #ifdef RT_USING_INTERRUPT_INFO
  205. isr_table[ir_self].counter++;
  206. #endif
  207. if (isr_func)
  208. {
  209. /* Interrupt for myself. */
  210. param = isr_table[ir_self].param;
  211. /* turn to interrupt service routine */
  212. isr_func(ir_self, param);
  213. }
  214. /* end of interrupt */
  215. rt_hw_interrupt_ack(ir);
  216. #endif
  217. }
  218. void rt_hw_trap_fiq(void)
  219. {
  220. void *param;
  221. int ir, ir_self;
  222. rt_isr_handler_t isr_func;
  223. extern struct rt_irq_desc isr_table[];
  224. ir = rt_hw_interrupt_get_irq();
  225. /* bit 10~12 is cpuid, bit 0~9 is interrup id */
  226. ir_self = ir & 0x3ffUL;
  227. /* get interrupt service routine */
  228. isr_func = isr_table[ir_self].handler;
  229. param = isr_table[ir_self].param;
  230. /* turn to interrupt service routine */
  231. isr_func(ir_self, param);
  232. /* end of interrupt */
  233. rt_hw_interrupt_ack(ir);
  234. }
  235. void process_exception(unsigned long esr, unsigned long epc);
  236. void SVC_Handler(struct rt_hw_exp_stack *regs);
  237. void rt_hw_trap_exception(struct rt_hw_exp_stack *regs)
  238. {
  239. unsigned long esr;
  240. unsigned char ec;
  241. asm volatile("mrs %0, esr_el1":"=r"(esr));
  242. ec = (unsigned char)((esr >> 26) & 0x3fU);
  243. #ifdef RT_USING_LWP
  244. if (dbg_check_event(regs, esr))
  245. {
  246. return;
  247. }
  248. else
  249. #endif
  250. if (ec == 0x15) /* is 64bit syscall ? */
  251. {
  252. SVC_Handler(regs);
  253. /* never return here */
  254. }
  255. #ifdef RT_USING_LWP
  256. if (check_user_stack(esr, regs))
  257. {
  258. return;
  259. }
  260. #endif
  261. process_exception(esr, regs->pc);
  262. rt_hw_show_register(regs);
  263. rt_kprintf("current: %s\n", rt_thread_self()->parent.name);
  264. #ifdef RT_USING_LWP
  265. check_user_fault(regs, 0, "user fault");
  266. #endif
  267. #ifdef RT_USING_FINSH
  268. list_thread();
  269. #endif
  270. #ifdef RT_USING_LWP
  271. {
  272. rt_thread_t th;
  273. th = rt_thread_self();
  274. if (th && th->lwp)
  275. {
  276. rt_backtrace_user_thread(th);
  277. }
  278. }
  279. #endif
  280. backtrace((unsigned long)regs->pc, (unsigned long)regs->x30, (unsigned long)regs->x29);
  281. rt_hw_cpu_shutdown();
  282. }
  283. void rt_hw_trap_serror(struct rt_hw_exp_stack *regs)
  284. {
  285. rt_kprintf("SError\n");
  286. rt_hw_show_register(regs);
  287. rt_kprintf("current: %s\n", rt_thread_self()->parent.name);
  288. #ifdef RT_USING_FINSH
  289. list_thread();
  290. #endif
  291. rt_hw_cpu_shutdown();
  292. }