clock.c 59 KB

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  1. /*
  2. * This file is part of FH8620 BSP for RT-Thread distribution.
  3. *
  4. * Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
  5. * All rights reserved
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20. *
  21. * Visit http://www.fullhan.com to get contact with Fullhan.
  22. *
  23. * Change Logs:
  24. * Date Author Notes
  25. */
  26. #include "clock.h"
  27. #include <rtdevice.h>
  28. #include "fh_arch.h"
  29. #include "libraries/inc/fh_timer.h"
  30. #include "fh_pmu.h"
  31. //#include "chip_reg.h"
  32. //NEED_CAUTION.
  33. #define TIMER_CLOCK 1000000
  34. #define FH_CLK_DEBUG
  35. #define FH_CLK_DIV_DEFAULT
  36. //#define FH_CLK_GATE_DEFAULT
  37. //#define FH_DBG_CLK
  38. #define FH_CLK_DIV_DEFAULT_VALUE 0x55aaaa55
  39. #define FH_CLK_GATE_DEFAULT_VALUE 0xaa5555aa
  40. #define CONFIG_PAE_PTS_CLOCK (1000000)
  41. #define TICKS_PER_USEC (CONFIG_PAE_PTS_CLOCK / 1000000)
  42. #define REG_PAE_PTS_REG (0xec100000 + 0x0040)
  43. #define fh_clk_err(p,fmt,args...)\
  44. rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args)
  45. #ifdef FH_CLK_DEBUG
  46. #define fh_clk_debug(p,fmt,args...)\
  47. rt_kprintf("%s:\t\t"fmt,p->name, ##args)
  48. #define fh_clk_debug_no_handle(fmt,args...)\
  49. rt_kprintf(fmt, ##args)
  50. #else
  51. //#define fh_clk_err(p,fmt,args...)
  52. #define fh_clk_debug(p,fmt,args...)
  53. #define fh_clk_debug_no_handle(fmt,args...)
  54. #endif
  55. struct fh_clk_tree;
  56. static struct fh_clk_tree fh_clk_tree;
  57. #define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
  58. #define __raw_readl(a) (*(volatile unsigned int *)(a))
  59. #define FH_TIMER_WRITEL(offset,value) __raw_writel(value,(fh_clk_tree.c_base_addr + offset))
  60. #define FH_TIMER_READL(offset) __raw_readl((fh_clk_tree.c_base_addr + offset))
  61. enum clk_gate_enum{
  62. #define CLK_GATE (1)
  63. #define CLK_UNGATE (0)
  64. ISP_ACLK_GATE = (1<<0),
  65. HCLK_GATE = (1<<1),
  66. CPU_FCLK0_GATE = (1<<3),
  67. VCU_CLK_GATE = (1<<4),
  68. VOU_CLK_GATE = (1<<5),
  69. MCLK_GATE = (1<<6),
  70. SPI0_CLK_GATE = (1<<7),
  71. SPI1_CLK_GATE = (1<<8),
  72. SDC0_CLK_GATE = (1<<9),
  73. SDC1_CLK_GATE = (1<<10),
  74. AC_MCLK_GATE = (1<<11), /////
  75. I2C0_CLK_GATE = (1<<12),
  76. UART0_CLK_GATE = (1<<13),
  77. UART1_CLK_GATE = (1<<14),
  78. //can't change
  79. WDT_CLK_GATE = (1<<15),
  80. PWM_CLK_GATE = (1<<16),
  81. TMR0_CLK_GATE = (1<<17),
  82. TMR1_CLK_GATE = (1<<18),
  83. PTS_CLK_GATE = (1<<19),
  84. MIPI_DPHY_CLK20M_GATE = (1<<20),
  85. MIPI_P32_CLK_GATE = (1<<21),
  86. PIX_CLK_GATE = (1<<22), ////
  87. CIS_CLK_OUT_GATE = (1<<23),
  88. I2S_SCLK_GATE = (1<<24), //////
  89. ETH_REF_CLK_GATE = (1<<25),
  90. SADC_CLK_GATE = (1<<26),
  91. I2C1_CLK_GATE = (1<<27),
  92. ETH_RX_CLK_GATE = (1<<28), /////
  93. ETH_TX_CLK_GATE = (1<<29), /////
  94. ETH_RMII_CLK_GATE = (1<<30),////
  95. };
  96. //struct fh_clk;
  97. typedef void (*clk_update)(struct fh_clk* p_clk);
  98. //update func...
  99. void clk_in_update(struct fh_clk* p_clk);
  100. void pll1_clk_update(struct fh_clk* p_clk);
  101. void pll0_clk_update(struct fh_clk* p_clk);
  102. void cis_pclk_update(struct fh_clk* p_clk);
  103. void ddr_clk_update(struct fh_clk* p_clk);
  104. void ddr_clk_update(struct fh_clk* p_clk);
  105. void fclk_update(struct fh_clk* p_clk);
  106. void aclk_update(struct fh_clk* p_clk);
  107. void hclk_update(struct fh_clk* p_clk);
  108. void pclk_update(struct fh_clk* p_clk);
  109. void isp_aclk_update(struct fh_clk* p_clk);
  110. void vcu_clk_update(struct fh_clk* p_clk);
  111. void vou_clk_update(struct fh_clk* p_clk);
  112. void mipi_p32_clk_update(struct fh_clk* p_clk);
  113. void cis_clk_out_update(struct fh_clk* p_clk);
  114. void pts_update(struct fh_clk* p_clk);
  115. void mipi_pix_clk_update(struct fh_clk* p_clk);
  116. void spi0_clk_update(struct fh_clk* p_clk);
  117. void spi1_clk_update(struct fh_clk* p_clk);
  118. void mipi_dphy_clk20m_update(struct fh_clk* p_clk);
  119. void i2c0_clk_update(struct fh_clk* p_clk);
  120. void i2c1_clk_update(struct fh_clk* p_clk);
  121. void uart0_clk_update(struct fh_clk* p_clk);
  122. void uart1_clk_update(struct fh_clk* p_clk);
  123. void pwm_clk_update(struct fh_clk* p_clk);
  124. void time0_clk_update(struct fh_clk* p_clk);
  125. void time1_clk_update(struct fh_clk* p_clk);
  126. void sadc_clk_update(struct fh_clk* p_clk);
  127. void sdc0_clk2x_update(struct fh_clk* p_clk);
  128. void sdc0_clk_update(struct fh_clk* p_clk);
  129. void sdc0_clk_out_update(struct fh_clk* p_clk);
  130. void sdc0_clk_sample_update(struct fh_clk* p_clk);
  131. void sdc0_clk_drv_update(struct fh_clk* p_clk);
  132. void sdc1_clk2x_update(struct fh_clk* p_clk);
  133. void sdc1_clk_update(struct fh_clk* p_clk);
  134. void sdc1_clk_out_update(struct fh_clk* p_clkt);
  135. void sdc1_clk_sample_update(struct fh_clk* p_clk);
  136. void sdc1_clk_drv_update(struct fh_clk* p_clk);
  137. void eth_ref_clk_update(struct fh_clk* p_clk);
  138. void wdt_clk_update(struct fh_clk* p_clk);
  139. rt_int32_t check_pix_clk_source(rt_uint32_t offset,rt_uint32_t mask,rt_uint32_t *value);
  140. void pix_update(struct fh_clk* p_clk);
  141. struct fh_clk_div{
  142. //some has prediv....
  143. //this two could have or......
  144. #define PRE_DIV_CAL_ALREADY (0x80000000)
  145. #define PRE_DIV_ENABLE (0x01)
  146. #define DIV_ENABLE (0x10)
  147. rt_uint32_t div_flag;
  148. rt_uint32_t pdiv_value;
  149. //rt_uint32_t hw_div_value;
  150. rt_uint32_t sw_div_value;
  151. rt_uint32_t sw_div_multi;
  152. //rt_uint32_t clk_in_hz;
  153. rt_uint32_t reg_offset;
  154. rt_uint32_t reg_mask;
  155. //rt_uint32_t rate;
  156. };
  157. struct fh_clk_mux{
  158. //#define MUX_LEVEL_1 (1)
  159. //#define MUX_LEVEL_2 (2)
  160. //#define MAX_MUX_LEVEL MUX_LEVEL_2
  161. // rt_uint32_t lev;
  162. #define HAS_MUX (0)
  163. #define HAS_NO_MUX (1)
  164. rt_uint32_t mux_flag;
  165. rt_uint32_t hw_mux_value;
  166. rt_uint32_t sw_mux_value;
  167. rt_uint32_t reg_offset;
  168. rt_uint32_t reg_mask;
  169. };
  170. struct fh_clk_gate{
  171. #define HAS_GATE (0)
  172. #define HAS_NO_GATE (1)
  173. rt_uint32_t gate_flag;
  174. #define CLK_UNGATE (0)
  175. #define CLK_GATE (1)
  176. //rt_uint32_t hw_status;
  177. rt_uint32_t sw_status;
  178. //rt_uint32_t value;
  179. rt_uint32_t reg_offset;
  180. rt_uint32_t reg_mask;
  181. };
  182. /***************
  183. *
  184. * level 1
  185. *
  186. ***************/
  187. struct fh_clk_level_1{
  188. rt_uint32_t clk_in_out;
  189. };
  190. /***************
  191. *
  192. * level 2
  193. *
  194. ***************/
  195. struct fh_clk_level_2{
  196. rt_uint32_t clk_in_out;
  197. };
  198. /***************
  199. *
  200. * level 3
  201. *
  202. ***************/
  203. struct fh_clk_level_3_ddr{
  204. //rt_uint32_t mux_level;
  205. struct fh_clk_mux mux[2];
  206. struct fh_clk_gate gate;
  207. struct fh_clk_div div;
  208. };
  209. struct fh_clk_level_3_sdc{
  210. #define DIFF_REFERENCE (0x80000000)
  211. rt_uint32_t phase_diff;
  212. rt_uint32_t reg_offset;
  213. rt_uint32_t reg_mask;
  214. };
  215. struct fh_clk_level_3_gmac{
  216. };
  217. struct fh_clk_level_3_normal{
  218. struct fh_clk_mux mux;
  219. struct fh_clk_gate gate;
  220. struct fh_clk_div div;
  221. };
  222. struct fh_clk_level_3 {
  223. #define LEVEL_PERI_NORMAL (0x301)
  224. #define LEVEL_PERI_DDR (0x302)
  225. #define LEVEL_PERI_SDC (0x303)
  226. #define LEVEL_PERI_GMAC (0x304)
  227. rt_uint32_t peri_flag;
  228. union
  229. {
  230. struct fh_clk_level_3_ddr ddr;
  231. struct fh_clk_level_3_sdc sdc;
  232. struct fh_clk_level_3_gmac gmac;
  233. struct fh_clk_level_3_normal normal;
  234. }obj;
  235. };
  236. struct fh_clk {
  237. char *name;
  238. #define LEVEL_CRYSTAL (0x100)
  239. #define LEVEL_PLL (0x200)
  240. #define LEVEL_PERIPHERAL (0x300)
  241. rt_uint32_t level;
  242. #define ROOT_NODE (RT_NULL)
  243. struct fh_clk *parent;
  244. union
  245. {
  246. struct fh_clk_level_1 crystal;
  247. struct fh_clk_level_2 pll;
  248. struct fh_clk_level_3 peri;
  249. }clk;
  250. rt_uint32_t clk_out_rate;
  251. #define CLK_HAS_NO_GATE (0x80000000)
  252. rt_uint32_t gate;
  253. clk_update update_func;
  254. //struct fh_clk_tree *p_tree;
  255. };
  256. struct fh_clk_tree{
  257. rt_uint32_t c_base_addr;
  258. struct fh_clk **clk_head;
  259. };
  260. /*********
  261. *
  262. *
  263. * clk map....
  264. *
  265. *
  266. ********/
  267. #define CRYSTAL_HZ (24000000)
  268. struct fh_clk clk_in = {
  269. .name = "clk_in",
  270. .level = LEVEL_CRYSTAL,
  271. .parent = ROOT_NODE,
  272. .clk.crystal.clk_in_out = CRYSTAL_HZ,
  273. //.clk_out_rate = clk_in.clk.crystal.clk_in_out,
  274. .clk_out_rate = CRYSTAL_HZ,
  275. .update_func = clk_in_update,
  276. };
  277. #define CIS_PCLK_HZ (108000000)
  278. struct fh_clk cis_pclk = {
  279. .name = "cis_pclk",
  280. .level = LEVEL_CRYSTAL,
  281. .parent = ROOT_NODE,
  282. .clk.crystal.clk_in_out = CIS_PCLK_HZ,
  283. //.clk_out_rate = clk_in.clk.crystal.clk_in_out,
  284. .clk_out_rate = CIS_PCLK_HZ,
  285. .update_func = cis_pclk_update,
  286. };
  287. #define PLL0_HZ (864000000)
  288. struct fh_clk pll0 = {
  289. .name = "pll0",
  290. .level = LEVEL_PLL,
  291. .parent = &clk_in,
  292. .clk.crystal.clk_in_out = PLL0_HZ,
  293. //.clk_out_rate = pll0.clk.crystal.clk_in_out,
  294. .clk_out_rate = PLL0_HZ,
  295. .update_func = pll0_clk_update,
  296. };
  297. #define PLL1_HZ (600000000)
  298. struct fh_clk pll1 = {
  299. .name = "pll1",
  300. .level = LEVEL_PLL,
  301. .parent = &clk_in,
  302. .clk.crystal.clk_in_out = PLL1_HZ,
  303. .clk_out_rate = PLL1_HZ,
  304. .update_func = pll1_clk_update,
  305. };
  306. //NEED_CAUTION parent not fix...
  307. static struct fh_clk ddr_clk_normal = {
  308. .name = "ddr_normal",
  309. .level = LEVEL_PERIPHERAL,
  310. //.parent = &clk_in,
  311. .clk.peri.peri_flag = LEVEL_PERI_DDR,
  312. //0:xtal_clk
  313. //1:pll0_clk
  314. #define MUX0_XTAL_CLK (0)
  315. #define MUX0_PLL0_CLK (1)
  316. .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL,
  317. .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0,
  318. //0:pll0 clk default 864/2M
  319. //1:pll1 clk default 600M
  320. #define MUX1_PLL0_CLK (0)
  321. #define MUX1_PLL1_CLK (1)
  322. .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL,
  323. .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24,
  324. //gate
  325. //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE,
  326. #ifdef FH_CLK_GATE_DEFAULT
  327. .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  328. #else
  329. .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE,
  330. #endif
  331. .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE,
  332. .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE,
  333. .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE,
  334. //div
  335. //clk in maybe cry or pll
  336. .clk.peri.obj.ddr.div.div_flag = DIV_ENABLE,
  337. //.clk.peri.obj.ddr.div.pdiv_value = 2,
  338. #ifdef FH_CLK_DIV_DEFAULT
  339. .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  340. #else
  341. .clk.peri.obj.ddr.div.sw_div_value = 1,
  342. #endif
  343. .clk.peri.obj.ddr.div.sw_div_multi =1,
  344. .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1,
  345. .clk.peri.obj.ddr.div.reg_mask = 0xff <<0,
  346. .update_func = ddr_clk_update,
  347. };
  348. //NEED_CAUTION parent not fix...
  349. static struct fh_clk ddr_clk_div2 = {
  350. .name = "ddr_div2",
  351. .level = LEVEL_PERIPHERAL,
  352. //.parent = &clk_in,
  353. .clk.peri.peri_flag = LEVEL_PERI_DDR,
  354. //0:xtal_clk
  355. //1:pll0_clk
  356. .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL,
  357. .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0,
  358. //0:pll0 clk default 864/2M
  359. //1:pll1 clk default 600M
  360. .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL,
  361. .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24,
  362. //gate
  363. //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE,
  364. #ifdef FH_CLK_GATE_DEFAULT
  365. .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  366. #else
  367. .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE,
  368. #endif
  369. .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE,
  370. .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE,
  371. .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE,
  372. //div
  373. //clk in maybe cry or pll
  374. .clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE,
  375. .clk.peri.obj.ddr.div.pdiv_value = 2,
  376. #ifdef FH_CLK_DIV_DEFAULT
  377. .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  378. #else
  379. .clk.peri.obj.ddr.div.sw_div_value = 1,
  380. #endif
  381. .clk.peri.obj.ddr.div.sw_div_multi =1,
  382. .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1,
  383. .clk.peri.obj.ddr.div.reg_mask = 0xff <<0,
  384. .update_func = ddr_clk_update,
  385. };
  386. static struct fh_clk cpu_fclk = {
  387. .name = "cpu_fclk",
  388. .level = LEVEL_PERIPHERAL,
  389. // //.parent = &clk_in,
  390. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  391. //0:xtal_clk
  392. //1:pll0_clk
  393. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  394. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  395. //gate
  396. .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
  397. //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  398. //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
  399. //div
  400. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  401. #ifdef FH_CLK_DIV_DEFAULT
  402. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  403. #else
  404. .clk.peri.obj.normal.div.sw_div_value = 0,
  405. #endif
  406. .clk.peri.obj.normal.div.sw_div_multi =1,
  407. .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
  408. .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
  409. .update_func = fclk_update,
  410. };
  411. //NEED_CAUTION parent not fix...
  412. static struct fh_clk cpu_aclk = {
  413. .name = "cpu_aclk",
  414. .level = LEVEL_PERIPHERAL,
  415. // //.parent = &clk_in,
  416. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  417. //0:xtal_clk
  418. //1:pll0_clk
  419. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  420. // .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  421. // .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  422. //gate
  423. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  424. #ifdef FH_CLK_GATE_DEFAULT
  425. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  426. #else
  427. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  428. #endif
  429. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  430. .clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
  431. //div
  432. .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
  433. .clk.peri.obj.normal.div.pdiv_value = 2,
  434. // .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
  435. // .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
  436. .update_func = aclk_update,
  437. };
  438. static struct fh_clk cpu_hclk = {
  439. .name = "cpu_hclk",
  440. .level = LEVEL_PERIPHERAL,
  441. // //.parent = &clk_in,
  442. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  443. //0:xtal_clk
  444. //1:pll0_clk
  445. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  446. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  447. //gate
  448. .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
  449. //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  450. //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
  451. //div
  452. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  453. #ifdef FH_CLK_DIV_DEFAULT
  454. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  455. #else
  456. .clk.peri.obj.normal.div.sw_div_value = 1,
  457. #endif
  458. .clk.peri.obj.normal.div.sw_div_multi =1,
  459. .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
  460. .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
  461. .update_func = hclk_update,
  462. };
  463. //NEED_CAUTION parent not fix...
  464. static struct fh_clk cpu_pclk = {
  465. .name = "cpu_pclk",
  466. .level = LEVEL_PERIPHERAL,
  467. // //.parent = &clk_in,
  468. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  469. //0:xtal_clk
  470. //1:pll0_clk
  471. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  472. //gate
  473. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  474. #ifdef FH_CLK_GATE_DEFAULT
  475. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  476. #else
  477. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  478. #endif
  479. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  480. .clk.peri.obj.normal.gate.reg_mask = HCLK_GATE,
  481. //div
  482. .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
  483. .clk.peri.obj.normal.div.pdiv_value = 2,
  484. // .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
  485. // .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
  486. .update_func = pclk_update,
  487. };
  488. //NEED_CAUTION parent not fix...
  489. static struct fh_clk isp_aclk = {
  490. .name = "isp_aclk",
  491. .level = LEVEL_PERIPHERAL,
  492. // //.parent = &clk_in,
  493. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  494. //0:xtal_clk
  495. //1:pll0_clk
  496. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  497. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  498. //gate
  499. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  500. .clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE,
  501. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  502. #ifdef FH_CLK_GATE_DEFAULT
  503. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  504. #else
  505. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  506. #endif
  507. //div
  508. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  509. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0,
  510. .clk.peri.obj.normal.div.reg_mask = 0x03 << 8,
  511. .clk.peri.obj.normal.div.sw_div_multi =1,
  512. #ifdef FH_CLK_DIV_DEFAULT
  513. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  514. #else
  515. .clk.peri.obj.normal.div.sw_div_value = 1,
  516. #endif
  517. .update_func = isp_aclk_update,
  518. };
  519. //
  520. ////NEED_CAUTION parent not fix...
  521. static struct fh_clk vcu_clk = {
  522. .name = "vcu_clk",
  523. .level = LEVEL_PERIPHERAL,
  524. // //.parent = &clk_in,
  525. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  526. //0:xtal_clk
  527. //1:pll0_clk
  528. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  529. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  530. //gate
  531. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  532. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  533. .clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE,
  534. #ifdef FH_CLK_GATE_DEFAULT
  535. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  536. #else
  537. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  538. #endif
  539. //div
  540. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  541. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0,
  542. .clk.peri.obj.normal.div.reg_mask = 0x03 << 24,
  543. .clk.peri.obj.normal.div.sw_div_multi =1,
  544. #ifdef FH_CLK_DIV_DEFAULT
  545. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  546. #else
  547. .clk.peri.obj.normal.div.sw_div_value = 1,
  548. #endif
  549. .update_func = vcu_clk_update,
  550. };
  551. static struct fh_clk vou_clk = {
  552. .name = "vou_clk",
  553. .level = LEVEL_PERIPHERAL,
  554. // //.parent = &clk_in,
  555. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  556. //0:xtal_clk
  557. //1:pll0_clk
  558. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  559. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  560. //gate
  561. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  562. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  563. .clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE,
  564. #ifdef FH_CLK_GATE_DEFAULT
  565. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  566. #else
  567. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  568. #endif
  569. //div
  570. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  571. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1,
  572. .clk.peri.obj.normal.div.reg_mask = 0x3f << 8,
  573. .clk.peri.obj.normal.div.sw_div_multi =1,
  574. #ifdef FH_CLK_DIV_DEFAULT
  575. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  576. #else
  577. .clk.peri.obj.normal.div.sw_div_value = 1,
  578. #endif
  579. .update_func = vou_clk_update,
  580. };
  581. static struct fh_clk mipi_p32_clk = {
  582. .name = "mipi_p32_clk",
  583. .level = LEVEL_PERIPHERAL,
  584. // //.parent = &clk_in,
  585. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  586. //0:xtal_clk
  587. //1:pll0_clk
  588. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  589. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  590. //gate
  591. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  592. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  593. .clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE,
  594. #ifdef FH_CLK_GATE_DEFAULT
  595. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  596. #else
  597. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  598. #endif
  599. //div
  600. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  601. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
  602. .clk.peri.obj.normal.div.reg_mask = 0x0f << 16,
  603. .clk.peri.obj.normal.div.sw_div_multi =1,
  604. #ifdef FH_CLK_DIV_DEFAULT
  605. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  606. #else
  607. .clk.peri.obj.normal.div.sw_div_value = 1,
  608. #endif
  609. .update_func = mipi_p32_clk_update,
  610. };
  611. static struct fh_clk cis_clk_out = {
  612. .name = "cis_clk_out",
  613. .level = LEVEL_PERIPHERAL,
  614. // //.parent = &clk_in,
  615. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  616. //0:xtal_clk
  617. //1:pll0_clk
  618. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  619. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  620. //gate
  621. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  622. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  623. .clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE,
  624. #ifdef FH_CLK_GATE_DEFAULT
  625. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  626. #else
  627. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  628. #endif
  629. //div
  630. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  631. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1,
  632. .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
  633. .clk.peri.obj.normal.div.sw_div_multi =1,
  634. #ifdef FH_CLK_DIV_DEFAULT
  635. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  636. #else
  637. .clk.peri.obj.normal.div.sw_div_value = 3,
  638. #endif
  639. .update_func = cis_clk_out_update,
  640. };
  641. static struct fh_clk pts_clk = {
  642. .name = "pts_clk",
  643. .level = LEVEL_PERIPHERAL,
  644. // //.parent = &clk_in,
  645. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  646. //0:xtal_clk
  647. //1:pll0_clk
  648. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  649. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  650. //gate
  651. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  652. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  653. .clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE,
  654. #ifdef FH_CLK_GATE_DEFAULT
  655. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  656. #else
  657. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  658. #endif
  659. //div
  660. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  661. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
  662. .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
  663. .clk.peri.obj.normal.div.sw_div_multi =1,
  664. #ifdef FH_CLK_DIV_DEFAULT
  665. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  666. #else
  667. .clk.peri.obj.normal.div.sw_div_value = 35,
  668. #endif
  669. .clk.peri.obj.normal.div.pdiv_value = 12,
  670. .update_func = pts_update,
  671. };
  672. static struct fh_clk mipi_pix_clk = {
  673. .name = "mipi_pix_clk_i",
  674. .level = LEVEL_PERIPHERAL,
  675. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  676. //0:xtal_clk
  677. //1:pll0_clk
  678. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
  679. .clk.peri.obj.normal.mux.reg_mask = 1<<0,
  680. //gate
  681. .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
  682. //div
  683. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  684. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
  685. .clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
  686. .clk.peri.obj.normal.div.sw_div_multi =1,
  687. #ifdef FH_CLK_DIV_DEFAULT
  688. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  689. #else
  690. .clk.peri.obj.normal.div.sw_div_value = 3,
  691. #endif
  692. .update_func = mipi_pix_clk_update,
  693. };
  694. static struct fh_clk pix_clk = {
  695. .name = "pix_clk",
  696. .level = LEVEL_PERIPHERAL,
  697. // //.parent = &clk_in,
  698. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  699. //0:xtal_clk
  700. //1:pll0_clk
  701. #define CIS_PIX_CLK (0)
  702. #define CIS_PIX_CLK_OPPOSITE (1)
  703. #define MIPI_PIX_CLK (2)
  704. .clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL,
  705. .clk.peri.obj.normal.mux.reg_mask = 3<<4,
  706. //gate
  707. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  708. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  709. .clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE,
  710. #ifdef FH_CLK_GATE_DEFAULT
  711. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  712. #else
  713. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  714. #endif
  715. //div
  716. .clk.peri.obj.normal.div.div_flag = 0,
  717. .update_func = pix_update,
  718. };
  719. static struct fh_clk spi0_clk = {
  720. .name = "spi0_clk",
  721. .level = LEVEL_PERIPHERAL,
  722. // //.parent = &clk_in,
  723. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  724. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  725. //gate
  726. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  727. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  728. .clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE,
  729. #ifdef FH_CLK_GATE_DEFAULT
  730. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  731. #else
  732. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  733. #endif
  734. //div
  735. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  736. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
  737. .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
  738. .clk.peri.obj.normal.div.sw_div_multi =1,
  739. #ifdef FH_CLK_DIV_DEFAULT
  740. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  741. #else
  742. .clk.peri.obj.normal.div.sw_div_value = 11,
  743. #endif
  744. .update_func = spi0_clk_update,
  745. };
  746. static struct fh_clk spi1_clk = {
  747. .name = "spi1_clk",
  748. .level = LEVEL_PERIPHERAL,
  749. // //.parent = &clk_in,
  750. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  751. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  752. //gate
  753. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  754. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  755. .clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE,
  756. #ifdef FH_CLK_GATE_DEFAULT
  757. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  758. #else
  759. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  760. #endif
  761. //div
  762. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  763. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
  764. .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
  765. .clk.peri.obj.normal.div.sw_div_multi =1,
  766. #ifdef FH_CLK_DIV_DEFAULT
  767. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  768. #else
  769. .clk.peri.obj.normal.div.sw_div_value = 11,
  770. #endif
  771. #ifdef RT_USING_SPI1
  772. .clk.peri.obj.normal.div.sw_div_value = 11,
  773. #endif
  774. .update_func = spi1_clk_update,
  775. };
  776. static struct fh_clk mipi_dphy_clk20m = {
  777. .name = "mipi_dphy_clk20m",
  778. .level = LEVEL_PERIPHERAL,
  779. // //.parent = &clk_in,
  780. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  781. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  782. //gate
  783. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  784. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  785. .clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE,
  786. #ifdef FH_CLK_GATE_DEFAULT
  787. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  788. #else
  789. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  790. #endif
  791. //div
  792. .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
  793. // .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
  794. // .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
  795. .clk.peri.obj.normal.div.sw_div_multi =1,
  796. .clk.peri.obj.normal.div.pdiv_value = 30,
  797. // .clk.peri.obj.normal.div.sw_div_value = 11,
  798. .update_func = mipi_dphy_clk20m_update,
  799. };
  800. static struct fh_clk i2c0_clk = {
  801. .name = "i2c0_clk",
  802. .level = LEVEL_PERIPHERAL,
  803. // //.parent = &clk_in,
  804. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  805. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  806. //gate
  807. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  808. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  809. .clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE,
  810. #ifdef FH_CLK_GATE_DEFAULT
  811. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  812. #else
  813. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  814. #endif
  815. //div
  816. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  817. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
  818. .clk.peri.obj.normal.div.reg_mask = 0x3f << 16,
  819. .clk.peri.obj.normal.div.sw_div_multi = 1,
  820. #ifdef FH_CLK_DIV_DEFAULT
  821. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  822. #else
  823. .clk.peri.obj.normal.div.sw_div_value = 1,
  824. #endif
  825. .clk.peri.obj.normal.div.pdiv_value = 20,
  826. .update_func = i2c0_clk_update,
  827. };
  828. static struct fh_clk i2c1_clk = {
  829. .name = "i2c1_clk",
  830. .level = LEVEL_PERIPHERAL,
  831. // //.parent = &clk_in,
  832. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  833. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  834. //gate
  835. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  836. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  837. .clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE,
  838. #ifdef FH_CLK_GATE_DEFAULT
  839. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  840. #else
  841. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  842. #endif
  843. //div
  844. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  845. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
  846. .clk.peri.obj.normal.div.reg_mask = 0x3f << 24,
  847. .clk.peri.obj.normal.div.sw_div_multi = 1,
  848. #ifdef FH_CLK_DIV_DEFAULT
  849. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  850. #else
  851. .clk.peri.obj.normal.div.sw_div_value = 1,
  852. #endif
  853. .clk.peri.obj.normal.div.pdiv_value = 20,
  854. .update_func = i2c1_clk_update,
  855. };
  856. static struct fh_clk uart0_clk = {
  857. .name = "uart0_clk",
  858. .level = LEVEL_PERIPHERAL,
  859. // //.parent = &clk_in,
  860. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  861. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  862. //gate
  863. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  864. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  865. .clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE,
  866. #ifdef FH_CLK_GATE_DEFAULT
  867. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  868. #else
  869. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  870. #endif
  871. //div
  872. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  873. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
  874. .clk.peri.obj.normal.div.reg_mask = 0x1f << 0,
  875. .clk.peri.obj.normal.div.sw_div_multi = 1,
  876. #ifdef FH_CLK_DIV_DEFAULT
  877. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  878. #else
  879. .clk.peri.obj.normal.div.sw_div_value = 1,
  880. #endif
  881. .clk.peri.obj.normal.div.pdiv_value = 10,
  882. .update_func = uart0_clk_update,
  883. };
  884. static struct fh_clk uart1_clk = {
  885. .name = "uart1_clk",
  886. .level = LEVEL_PERIPHERAL,
  887. // //.parent = &clk_in,
  888. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  889. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  890. //gate
  891. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  892. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  893. .clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE,
  894. #ifdef FH_CLK_GATE_DEFAULT
  895. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  896. #else
  897. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  898. #endif
  899. //div
  900. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  901. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
  902. .clk.peri.obj.normal.div.reg_mask = 0x1f << 8,
  903. .clk.peri.obj.normal.div.sw_div_multi = 1,
  904. #ifdef FH_CLK_DIV_DEFAULT
  905. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  906. #else
  907. .clk.peri.obj.normal.div.sw_div_value = 1,
  908. #endif
  909. .clk.peri.obj.normal.div.pdiv_value = 10,
  910. .update_func = uart1_clk_update,
  911. };
  912. static struct fh_clk pwm_clk = {
  913. .name = "pwm_clk",
  914. .level = LEVEL_PERIPHERAL,
  915. // //.parent = &clk_in,
  916. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  917. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  918. //gate
  919. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  920. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  921. .clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE,
  922. #ifdef FH_CLK_GATE_DEFAULT
  923. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  924. #else
  925. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  926. #endif
  927. //div
  928. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  929. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
  930. .clk.peri.obj.normal.div.reg_mask = 0x3f << 0,
  931. .clk.peri.obj.normal.div.sw_div_multi = 1,
  932. #ifdef FH_CLK_DIV_DEFAULT
  933. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  934. #else
  935. .clk.peri.obj.normal.div.sw_div_value = 29,
  936. #endif
  937. .clk.peri.obj.normal.div.pdiv_value = 20,
  938. .update_func = pwm_clk_update,
  939. };
  940. static struct fh_clk time0_clk = {
  941. .name = "time0_clk",
  942. .level = LEVEL_PERIPHERAL,
  943. // //.parent = &clk_in,
  944. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  945. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  946. //gate
  947. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  948. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  949. .clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE,
  950. #ifdef FH_CLK_GATE_DEFAULT
  951. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  952. #else
  953. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  954. #endif
  955. //div
  956. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  957. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
  958. .clk.peri.obj.normal.div.reg_mask = 0x3f << 16,
  959. .clk.peri.obj.normal.div.sw_div_multi = 1,
  960. #ifdef FH_CLK_DIV_DEFAULT
  961. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  962. #else
  963. .clk.peri.obj.normal.div.sw_div_value = 29,
  964. #endif
  965. .clk.peri.obj.normal.div.pdiv_value = 20,
  966. .update_func = time0_clk_update,
  967. };
  968. static struct fh_clk time1_clk = {
  969. .name = "time1_clk",
  970. .level = LEVEL_PERIPHERAL,
  971. // //.parent = &clk_in,
  972. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  973. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  974. //gate
  975. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  976. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  977. .clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE,
  978. #ifdef FH_CLK_GATE_DEFAULT
  979. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  980. #else
  981. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  982. #endif
  983. //div
  984. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  985. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
  986. .clk.peri.obj.normal.div.reg_mask = 0x3f << 24,
  987. .clk.peri.obj.normal.div.sw_div_multi = 1,
  988. #ifdef FH_CLK_DIV_DEFAULT
  989. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  990. #else
  991. .clk.peri.obj.normal.div.sw_div_value = 29,
  992. #endif
  993. .clk.peri.obj.normal.div.pdiv_value = 20,
  994. .update_func = time1_clk_update,
  995. };
  996. static struct fh_clk sadc_clk = {
  997. .name = "sadc_clk",
  998. .level = LEVEL_PERIPHERAL,
  999. // //.parent = &clk_in,
  1000. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  1001. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  1002. //gate
  1003. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  1004. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  1005. .clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE,
  1006. #ifdef FH_CLK_GATE_DEFAULT
  1007. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  1008. #else
  1009. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  1010. #endif
  1011. //div
  1012. .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
  1013. .clk.peri.obj.normal.div.sw_div_multi = 1,
  1014. .clk.peri.obj.normal.div.pdiv_value = 120,
  1015. .update_func = sadc_clk_update,
  1016. };
  1017. static struct fh_clk sdc0_clk2x = {
  1018. .name = "sdc0_clk2x",
  1019. .level = LEVEL_PERIPHERAL,
  1020. // //.parent = &clk_in,
  1021. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  1022. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  1023. //gate
  1024. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  1025. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  1026. .clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE,
  1027. #ifdef FH_CLK_GATE_DEFAULT
  1028. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  1029. #else
  1030. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  1031. #endif
  1032. //div
  1033. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  1034. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
  1035. .clk.peri.obj.normal.div.reg_mask = 0x0f << 8,
  1036. .clk.peri.obj.normal.div.sw_div_multi = 1,
  1037. #ifdef FH_CLK_DIV_DEFAULT
  1038. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  1039. #else
  1040. .clk.peri.obj.normal.div.sw_div_value = 5,
  1041. #endif
  1042. .clk.peri.obj.normal.div.pdiv_value = 2,
  1043. .update_func = sdc0_clk2x_update,
  1044. };
  1045. static struct fh_clk sdc0_clk = {
  1046. .name = "sdc0_clk",
  1047. .level = LEVEL_PERIPHERAL,
  1048. // //.parent = &clk_in,
  1049. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1050. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE,
  1051. // .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1052. // .clk.peri.obj.sdc.reg_mask = 0x0,
  1053. .update_func = sdc0_clk_update,
  1054. };
  1055. static struct fh_clk sdc0_clk_out = {
  1056. .name = "sdc0_clk_out",
  1057. .level = LEVEL_PERIPHERAL,
  1058. // //.parent = &clk_in,
  1059. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1060. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
  1061. // .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1062. // .clk.peri.obj.sdc.reg_mask = 0x0,
  1063. .update_func = sdc0_clk_out_update,
  1064. };
  1065. static struct fh_clk sdc0_clk_sample = {
  1066. .name = "sdc0_clk_sample",
  1067. .level = LEVEL_PERIPHERAL,
  1068. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1069. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
  1070. .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1071. .clk.peri.obj.sdc.reg_mask = 3<16,
  1072. .update_func = sdc0_clk_sample_update,
  1073. };
  1074. static struct fh_clk sdc0_clk_drive = {
  1075. .name = "sdc0_clk_drive",
  1076. .level = LEVEL_PERIPHERAL,
  1077. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1078. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
  1079. .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1080. .clk.peri.obj.sdc.reg_mask = 3<20,
  1081. .update_func = sdc0_clk_drv_update,
  1082. };
  1083. static struct fh_clk sdc1_clk2x = {
  1084. .name = "sdc1_clk2x",
  1085. .level = LEVEL_PERIPHERAL,
  1086. // //.parent = &clk_in,
  1087. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  1088. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  1089. //gate
  1090. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  1091. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  1092. .clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE,
  1093. #ifdef FH_CLK_GATE_DEFAULT
  1094. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  1095. #else
  1096. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  1097. #endif
  1098. //div
  1099. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  1100. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
  1101. .clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
  1102. .clk.peri.obj.normal.div.sw_div_multi = 1,
  1103. #ifdef FH_CLK_DIV_DEFAULT
  1104. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  1105. #else
  1106. .clk.peri.obj.normal.div.sw_div_value = 5,
  1107. #endif
  1108. .clk.peri.obj.normal.div.pdiv_value = 2,
  1109. .update_func = sdc1_clk2x_update,
  1110. };
  1111. static struct fh_clk sdc1_clk = {
  1112. .name = "sdc1_clk",
  1113. .level = LEVEL_PERIPHERAL,
  1114. // //.parent = &clk_in,
  1115. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1116. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE,
  1117. // .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1118. // .clk.peri.obj.sdc.reg_mask = 0x0,
  1119. .update_func = sdc1_clk_update,
  1120. };
  1121. static struct fh_clk sdc1_clk_out = {
  1122. .name = "sdc1_clk_out",
  1123. .level = LEVEL_PERIPHERAL,
  1124. // //.parent = &clk_in,
  1125. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1126. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
  1127. // .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1128. // .clk.peri.obj.sdc.reg_mask = 0x0,
  1129. .update_func = sdc1_clk_out_update,
  1130. };
  1131. static struct fh_clk sdc1_clk_sample = {
  1132. .name = "sdc1_clk_sample",
  1133. .level = LEVEL_PERIPHERAL,
  1134. // //.parent = &clk_in,
  1135. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1136. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
  1137. .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1138. .clk.peri.obj.sdc.reg_mask = 3<8,
  1139. .update_func = sdc1_clk_sample_update,
  1140. };
  1141. static struct fh_clk sdc1_clk_drive = {
  1142. .name = "sdc1_clk_drive",
  1143. .level = LEVEL_PERIPHERAL,
  1144. // //.parent = &clk_in,
  1145. .clk.peri.peri_flag = LEVEL_PERI_SDC,
  1146. .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
  1147. .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
  1148. .clk.peri.obj.sdc.reg_mask = 3<12,
  1149. .update_func = sdc1_clk_drv_update,
  1150. };
  1151. static struct fh_clk eth_ref_clk = {
  1152. .name = "eth_ref_clk",
  1153. .level = LEVEL_PERIPHERAL,
  1154. // //.parent = &clk_in,
  1155. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  1156. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  1157. //gate
  1158. .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
  1159. .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
  1160. .clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE,
  1161. #ifdef FH_CLK_GATE_DEFAULT
  1162. .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
  1163. #else
  1164. .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
  1165. #endif
  1166. //div
  1167. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
  1168. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6,
  1169. .clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
  1170. .clk.peri.obj.normal.div.sw_div_multi = 1,
  1171. #ifdef FH_CLK_DIV_DEFAULT
  1172. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  1173. #else
  1174. .clk.peri.obj.normal.div.sw_div_value = 5,
  1175. #endif
  1176. .clk.peri.obj.normal.div.pdiv_value = 2,
  1177. .update_func = eth_ref_clk_update,
  1178. };
  1179. static struct fh_clk wdt_clk = {
  1180. .name = "wdt_clk",
  1181. .level = LEVEL_PERIPHERAL,
  1182. // //.parent = &clk_in,
  1183. .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
  1184. .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
  1185. //gate
  1186. .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
  1187. //div
  1188. .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
  1189. .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
  1190. .clk.peri.obj.normal.div.reg_mask = 0x3f << 8,
  1191. .clk.peri.obj.normal.div.sw_div_multi = 1,
  1192. #ifdef FH_CLK_DIV_DEFAULT
  1193. .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
  1194. #else
  1195. .clk.peri.obj.normal.div.sw_div_value = 29,
  1196. #endif
  1197. .update_func = wdt_clk_update,
  1198. };
  1199. struct fh_clk *fh_clk_array[] = {
  1200. &clk_in,
  1201. &cis_pclk,
  1202. &pll0,
  1203. &pll1,
  1204. &ddr_clk_normal,
  1205. &ddr_clk_div2,
  1206. &cpu_fclk,
  1207. &cpu_aclk,
  1208. &cpu_hclk,
  1209. &cpu_pclk,
  1210. &isp_aclk,
  1211. &vcu_clk,
  1212. &vou_clk,
  1213. &mipi_p32_clk,
  1214. &cis_clk_out,
  1215. &pts_clk,
  1216. &mipi_pix_clk,
  1217. &pix_clk,
  1218. //pll1
  1219. &sdc0_clk2x,
  1220. &sdc0_clk,
  1221. &sdc0_clk_out,
  1222. &sdc0_clk_sample,
  1223. &sdc0_clk_drive,
  1224. &sdc1_clk2x,
  1225. &sdc1_clk,
  1226. &sdc1_clk_out,
  1227. &sdc1_clk_sample,
  1228. &sdc1_clk_drive,
  1229. &spi0_clk,
  1230. &spi1_clk,
  1231. &mipi_dphy_clk20m,
  1232. &i2c0_clk,
  1233. &i2c1_clk,
  1234. &uart0_clk,
  1235. &uart1_clk,
  1236. &pwm_clk,
  1237. &time0_clk,
  1238. &time1_clk,
  1239. &sadc_clk,
  1240. &eth_ref_clk,
  1241. &wdt_clk,
  1242. };
  1243. static inline rt_int32_t wrap_read_reg(rt_uint32_t offset, rt_uint32_t mask,
  1244. rt_uint32_t *value)
  1245. {
  1246. rt_uint32_t temp_v, temp_shift;
  1247. /* if(fh_pmu_status() == PMU_STATUS_CLOSE)
  1248. return -1;*/
  1249. temp_v = FH_TIMER_READL(offset);
  1250. temp_v &= mask;
  1251. temp_shift = __rt_ffs(mask);
  1252. temp_v = temp_v >> (temp_shift - 1);
  1253. *value = temp_v;
  1254. return 0;
  1255. }
  1256. static inline rt_int32_t wrap_write_reg(rt_uint32_t offset, rt_uint32_t mask,
  1257. rt_uint32_t value)
  1258. {
  1259. rt_uint32_t temp_v, temp_shift;
  1260. /*
  1261. if(fh_pmu_status() == PMU_STATUS_CLOSE)
  1262. return -1;
  1263. */
  1264. temp_v = FH_TIMER_READL(offset);
  1265. temp_v &= ~mask;
  1266. temp_shift = __rt_ffs(mask);
  1267. temp_v |= value << (temp_shift - 1);
  1268. FH_TIMER_WRITEL(offset, temp_v);
  1269. return 0;
  1270. }
  1271. rt_int32_t check_pix_clk_source(rt_uint32_t offset, rt_uint32_t mask,
  1272. rt_uint32_t *value)
  1273. {
  1274. rt_uint32_t mux0;
  1275. rt_int32_t ret;
  1276. ret = wrap_read_reg(offset, mask, &mux0);
  1277. if (ret != 0) {
  1278. return ret;
  1279. }
  1280. *value = mux0;
  1281. return 0;
  1282. }
  1283. rt_int32_t check_xtal_pll0(rt_uint32_t offset, rt_uint32_t mask,
  1284. rt_uint32_t *value)
  1285. {
  1286. rt_uint32_t mux0;
  1287. rt_int32_t ret;
  1288. ret = wrap_read_reg(offset, mask, &mux0);
  1289. if (ret != 0) {
  1290. return ret;
  1291. }
  1292. if (mux0 == MUX0_PLL0_CLK)
  1293. *value = MUX0_PLL0_CLK;
  1294. else
  1295. *value = MUX0_XTAL_CLK;
  1296. return 0;
  1297. }
  1298. void cal_pll0_prediv(rt_uint32_t *div_flag, rt_uint32_t *pre_value)
  1299. {
  1300. if (!(*div_flag & PRE_DIV_CAL_ALREADY)) {
  1301. //before has got the prediv value..
  1302. if (*div_flag & PRE_DIV_ENABLE) {
  1303. *pre_value *= 2;
  1304. } else {
  1305. *pre_value = 2;
  1306. }
  1307. *div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY;
  1308. }
  1309. }
  1310. rt_int32_t sw_div_process(rt_uint32_t div_flag, rt_uint32_t offset,
  1311. rt_uint32_t mask, rt_uint32_t *div_value)
  1312. {
  1313. //rt_kprintf("----------div go----------\n");
  1314. rt_uint32_t div;
  1315. rt_int32_t ret;
  1316. if (div_flag & DIV_ENABLE) {
  1317. ret = wrap_read_reg(offset, mask, &div);
  1318. if (ret != 0) {
  1319. return ret;
  1320. }
  1321. //
  1322. // rt_kprintf("hw value is %x\n",div);
  1323. // rt_kprintf("sw value is %x\n",div_value);
  1324. //
  1325. // rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000));
  1326. // rt_kprintf("mask is %x\n",mask);
  1327. //if use the hw default value....
  1328. if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) {
  1329. *div_value = div;
  1330. return 0;
  1331. }
  1332. if (div != *div_value) {
  1333. ret = wrap_write_reg(offset, mask, *div_value);
  1334. if (ret != 0) {
  1335. return ret;
  1336. }
  1337. }
  1338. }
  1339. //rt_kprintf("----------div done----------\n");
  1340. return 0;
  1341. //*div_flag |= PRE_DIV_ENABLE;
  1342. }
  1343. void cal_baud_hz(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div,
  1344. rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out)
  1345. {
  1346. //div += 1;
  1347. if (div_flag & PRE_DIV_ENABLE) {
  1348. *baud_out = (clk_in / pre_div);
  1349. } else {
  1350. *baud_out = clk_in;
  1351. }
  1352. if (div_flag & DIV_ENABLE) {
  1353. *baud_out /= ((div + 1) * div_multi);
  1354. }
  1355. }
  1356. void cal_baud_div(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div,
  1357. rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out)
  1358. {
  1359. //div += 1;
  1360. rt_uint32_t temp_baud_hz, temp_baud_div;
  1361. if (div_flag & DIV_ENABLE) {
  1362. if (div_flag & PRE_DIV_ENABLE) {
  1363. temp_baud_hz = (clk_in / pre_div);
  1364. } else {
  1365. temp_baud_hz = clk_in;
  1366. }
  1367. temp_baud_div = temp_baud_hz / baud_out;
  1368. *div = temp_baud_div - 1;
  1369. }
  1370. }
  1371. rt_int32_t process_gate(rt_uint32_t gate_flag, rt_uint32_t reg_offset,
  1372. rt_uint32_t reg_mask, rt_uint32_t *sw_status,
  1373. rt_uint32_t *pclk_status)
  1374. {
  1375. //rt_kprintf("----------gate go----------\n");
  1376. rt_uint32_t hw_gate;
  1377. rt_int32_t ret;
  1378. if (gate_flag == HAS_GATE) {
  1379. ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate);
  1380. if (ret != 0) {
  1381. return ret;
  1382. }
  1383. if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) {
  1384. *sw_status = hw_gate;
  1385. *pclk_status = *sw_status;
  1386. return 0;
  1387. }
  1388. // rt_kprintf("gate hw is :%x\n",hw_gate);
  1389. // rt_kprintf("gate sw is :%x\n",sw_status);
  1390. if (hw_gate != *sw_status) {
  1391. //update the gate..
  1392. // rt_kprintf("gate reg offset is :%x\n",reg_offset);
  1393. // rt_kprintf("gate reg mask is :%x\n",reg_mask);
  1394. // rt_kprintf("gate reg write is :%x\n",sw_status);
  1395. ret = wrap_write_reg(reg_offset, reg_mask, *sw_status);
  1396. if (ret != 0) {
  1397. return ret;
  1398. }
  1399. }
  1400. *pclk_status = *sw_status;
  1401. }
  1402. else {
  1403. *pclk_status |= CLK_HAS_NO_GATE;
  1404. }
  1405. //rt_kprintf("---------gate done---------\n");
  1406. return 0;
  1407. }
  1408. void clk_handle(struct fh_clk* p_clk, struct fh_clk *parent)
  1409. {
  1410. //rt_uint32_t div;
  1411. //rt_uint32_t sw_gate;
  1412. rt_uint32_t phase;
  1413. rt_int32_t ret;
  1414. p_clk->parent = parent;
  1415. // switch
  1416. //fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n ");
  1417. if (p_clk->parent)
  1418. //rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority);
  1419. fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name);
  1420. else
  1421. fh_clk_debug(p_clk, "'root node'\n");
  1422. switch (p_clk->level) {
  1423. case LEVEL_CRYSTAL:
  1424. //fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate);
  1425. break;
  1426. case LEVEL_PLL:
  1427. //fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate);
  1428. break;
  1429. case LEVEL_PERIPHERAL:
  1430. switch (p_clk->clk.peri.peri_flag) {
  1431. case LEVEL_PERI_NORMAL:
  1432. //div = p_clk->clk.peri.obj.normal.div.sw_div_value;
  1433. ret =
  1434. sw_div_process(
  1435. p_clk->clk.peri.obj.normal.div.div_flag,
  1436. p_clk->clk.peri.obj.normal.div.reg_offset,
  1437. p_clk->clk.peri.obj.normal.div.reg_mask,
  1438. &p_clk->clk.peri.obj.normal.div.sw_div_value);
  1439. if (ret != 0) {
  1440. fh_clk_err(p_clk,
  1441. "div process failed.error no:%x\n",
  1442. ret);
  1443. break;
  1444. }
  1445. //fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value);
  1446. // fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value);
  1447. // fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value);
  1448. // fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate);
  1449. // fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag);
  1450. //hw will self add 1..
  1451. cal_baud_hz(p_clk->parent->clk_out_rate,
  1452. p_clk->clk.peri.obj.normal.div.div_flag,
  1453. p_clk->clk.peri.obj.normal.div.pdiv_value,
  1454. p_clk->clk.peri.obj.normal.div.sw_div_value,
  1455. p_clk->clk.peri.obj.normal.div.sw_div_multi,
  1456. &p_clk->clk_out_rate);
  1457. //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
  1458. //fix the gate..
  1459. //sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status;
  1460. ret =
  1461. process_gate(
  1462. p_clk->clk.peri.obj.normal.gate.gate_flag,
  1463. p_clk->clk.peri.obj.normal.gate.reg_offset,
  1464. p_clk->clk.peri.obj.normal.gate.reg_mask,
  1465. &p_clk->clk.peri.obj.normal.gate.sw_status,
  1466. &p_clk->gate);
  1467. if (ret != 0) {
  1468. fh_clk_err(p_clk,
  1469. "gate process failed.error no:%x\n",
  1470. ret);
  1471. break;
  1472. }
  1473. break;
  1474. case LEVEL_PERI_DDR:
  1475. //rt_uint32_t mux0,mux1;
  1476. //div = p_clk->clk.peri.obj.ddr.div.sw_div_value;
  1477. ret =
  1478. sw_div_process(
  1479. p_clk->clk.peri.obj.ddr.div.div_flag,
  1480. p_clk->clk.peri.obj.ddr.div.reg_offset,
  1481. p_clk->clk.peri.obj.ddr.div.reg_mask,
  1482. &p_clk->clk.peri.obj.ddr.div.sw_div_value);
  1483. if (ret != 0) {
  1484. fh_clk_err(p_clk,
  1485. "div process failed.error no:%x\n",
  1486. ret);
  1487. break;
  1488. }
  1489. // fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value);
  1490. // fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value);
  1491. // fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate);
  1492. // fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag);
  1493. cal_baud_hz(p_clk->parent->clk_out_rate,
  1494. p_clk->clk.peri.obj.ddr.div.div_flag,
  1495. p_clk->clk.peri.obj.ddr.div.pdiv_value,
  1496. p_clk->clk.peri.obj.ddr.div.sw_div_value,
  1497. p_clk->clk.peri.obj.ddr.div.sw_div_multi,
  1498. &p_clk->clk_out_rate);
  1499. //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
  1500. //fix the gate..
  1501. //fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask);
  1502. //sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status;
  1503. ret = process_gate(
  1504. p_clk->clk.peri.obj.ddr.gate.gate_flag,
  1505. p_clk->clk.peri.obj.ddr.gate.reg_offset,
  1506. p_clk->clk.peri.obj.ddr.gate.reg_mask,
  1507. &p_clk->clk.peri.obj.ddr.gate.sw_status,
  1508. &p_clk->gate);
  1509. if (ret != 0) {
  1510. fh_clk_err(p_clk,
  1511. "gate process failed.error no:%x\n",
  1512. ret);
  1513. break;
  1514. }
  1515. break;
  1516. case LEVEL_PERI_SDC:
  1517. //just need to handle the phase....
  1518. p_clk->clk_out_rate = p_clk->parent->clk_out_rate;
  1519. if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) {
  1520. //fh_clk_debug(p_clk,"this is the reference..no need to process..\n");
  1521. break;
  1522. }
  1523. //baud ...
  1524. //phase..
  1525. //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
  1526. //hw status..
  1527. ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset,
  1528. p_clk->clk.peri.obj.sdc.reg_mask,
  1529. &phase);
  1530. if (ret != 0) {
  1531. fh_clk_err(p_clk,
  1532. "read pmu failed.error no:%x\n",
  1533. ret);
  1534. break;
  1535. }
  1536. // fh_clk_debug(p_clk,"hw phase is :%x\n",phase);
  1537. // fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff);
  1538. if (phase != p_clk->clk.peri.obj.sdc.phase_diff) {
  1539. //update the hw para..
  1540. ret =
  1541. wrap_write_reg(
  1542. p_clk->clk.peri.obj.sdc.reg_offset,
  1543. p_clk->clk.peri.obj.sdc.reg_mask,
  1544. p_clk->clk.peri.obj.sdc.phase_diff);
  1545. if (ret != 0) {
  1546. fh_clk_err(p_clk,
  1547. "write pmu failed.error no:%x\n",
  1548. ret);
  1549. break;
  1550. }
  1551. }
  1552. break;
  1553. case LEVEL_PERI_GMAC:
  1554. break;
  1555. default:
  1556. break;
  1557. }
  1558. }
  1559. fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate);
  1560. }
  1561. //
  1562. void clk_in_update(struct fh_clk* p_clk)
  1563. {
  1564. clk_handle(p_clk, RT_NULL);
  1565. }
  1566. void cis_pclk_update(struct fh_clk* p_clk)
  1567. {
  1568. clk_handle(p_clk, RT_NULL);
  1569. }
  1570. void pll1_clk_update(struct fh_clk* p_clk)
  1571. {
  1572. clk_handle(p_clk, &clk_in);
  1573. }
  1574. void pll0_clk_update(struct fh_clk* p_clk)
  1575. {
  1576. clk_handle(p_clk, &clk_in);
  1577. }
  1578. void ddr_clk_update(struct fh_clk* p_clk)
  1579. {
  1580. //check if pll0 or pll1
  1581. rt_uint32_t mux0, mux1;
  1582. rt_int32_t ret;
  1583. struct fh_clk* parent;
  1584. //1 step: fix the parent..
  1585. ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset,
  1586. p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1);
  1587. if (ret != 0) {
  1588. fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
  1589. return;
  1590. }
  1591. if (mux1 == MUX1_PLL0_CLK) {
  1592. ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,
  1593. p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0);
  1594. if (ret != 0) {
  1595. fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
  1596. return;
  1597. }
  1598. if (mux0 == MUX0_PLL0_CLK) {
  1599. //ddr normal parent is pll0
  1600. parent = &pll0;
  1601. } else {
  1602. //ddr normal parent is xtal
  1603. parent = &clk_in;
  1604. }
  1605. } else {
  1606. //ddr normal parent is pll1
  1607. parent = &pll1;
  1608. }
  1609. p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX;
  1610. p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX;
  1611. clk_handle(p_clk, parent);
  1612. }
  1613. void fclk_update(struct fh_clk* p_clk)
  1614. {
  1615. //check if pll0 or xtal
  1616. rt_uint32_t mux0;
  1617. rt_int32_t ret;
  1618. struct fh_clk* parent; //1 step: fix the parent..
  1619. //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask);
  1620. ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset,
  1621. p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0);
  1622. if (ret != 0) {
  1623. fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
  1624. return;
  1625. }
  1626. //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0);
  1627. if (mux0 == MUX0_PLL0_CLK) {
  1628. //ddr normal parent is pll0
  1629. parent = &pll0;
  1630. } else {
  1631. //ddr normal parent is xtal
  1632. parent = &clk_in;
  1633. }
  1634. p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX;
  1635. //2 step:fix the div...
  1636. if (mux0 == MUX0_PLL0_CLK) {
  1637. //cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value);
  1638. cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag,
  1639. &p_clk->clk.peri.obj.normal.div.pdiv_value);
  1640. }
  1641. clk_handle(p_clk, parent);
  1642. }
  1643. void pix_update(struct fh_clk* p_clk)
  1644. {
  1645. //check if pll0 or xtal
  1646. rt_uint32_t mux0;
  1647. rt_int32_t ret;
  1648. struct fh_clk* parent; //1 step: fix the parent..
  1649. #if(1)
  1650. //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask);
  1651. ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset,
  1652. p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0);
  1653. if (ret != 0) {
  1654. fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
  1655. return;
  1656. }
  1657. //#define CIS_PIX_CLK (0)
  1658. //#define CIS_PIX_CLK_OPPOSITE (1)
  1659. //#define MIPI_PIX_CLK (2)
  1660. //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0);
  1661. if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) {
  1662. //ddr normal parent is pll0
  1663. parent = &cis_pclk;
  1664. } else {
  1665. parent = &mipi_pix_clk;
  1666. }
  1667. p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX;
  1668. #endif
  1669. clk_handle(p_clk, parent);
  1670. }
  1671. void aclk_update(struct fh_clk* p_clk)
  1672. {
  1673. clk_handle(p_clk, &cpu_fclk);
  1674. }
  1675. void hclk_update(struct fh_clk* p_clk)
  1676. {
  1677. fclk_update(p_clk);
  1678. }
  1679. void pclk_update(struct fh_clk* p_clk)
  1680. {
  1681. clk_handle(p_clk, &cpu_hclk);
  1682. }
  1683. void isp_aclk_update(struct fh_clk* p_clk)
  1684. {
  1685. fclk_update(p_clk);
  1686. }
  1687. void vcu_clk_update(struct fh_clk* p_clk)
  1688. {
  1689. fclk_update(p_clk);
  1690. }
  1691. void vou_clk_update(struct fh_clk* p_clk)
  1692. {
  1693. fclk_update(p_clk);
  1694. }
  1695. void mipi_p32_clk_update(struct fh_clk* p_clk)
  1696. {
  1697. fclk_update(p_clk);
  1698. }
  1699. void cis_clk_out_update(struct fh_clk* p_clk)
  1700. {
  1701. fclk_update(p_clk);
  1702. }
  1703. void pts_update(struct fh_clk* p_clk)
  1704. {
  1705. fclk_update(p_clk);
  1706. }
  1707. void mipi_pix_clk_update(struct fh_clk* p_clk)
  1708. {
  1709. fclk_update(p_clk);
  1710. }
  1711. void spi0_clk_update(struct fh_clk* p_clk)
  1712. {
  1713. clk_handle(p_clk, &pll1);
  1714. }
  1715. void spi1_clk_update(struct fh_clk* p_clk)
  1716. {
  1717. clk_handle(p_clk, &pll1);
  1718. }
  1719. void mipi_dphy_clk20m_update(struct fh_clk* p_clk)
  1720. {
  1721. clk_handle(p_clk, &pll1);
  1722. }
  1723. void i2c0_clk_update(struct fh_clk* p_clk)
  1724. {
  1725. clk_handle(p_clk, &pll1);
  1726. }
  1727. void i2c1_clk_update(struct fh_clk* p_clk)
  1728. {
  1729. clk_handle(p_clk, &pll1);
  1730. }
  1731. void uart0_clk_update(struct fh_clk* p_clk)
  1732. {
  1733. clk_handle(p_clk, &pll1);
  1734. }
  1735. void pwm_clk_update(struct fh_clk* p_clk)
  1736. {
  1737. clk_handle(p_clk, &pll1);
  1738. }
  1739. void time0_clk_update(struct fh_clk* p_clk)
  1740. {
  1741. clk_handle(p_clk, &pll1);
  1742. }
  1743. void time1_clk_update(struct fh_clk* p_clk)
  1744. {
  1745. clk_handle(p_clk, &pll1);
  1746. }
  1747. void uart1_clk_update(struct fh_clk* p_clk)
  1748. {
  1749. clk_handle(p_clk, &pll1);
  1750. }
  1751. void sadc_clk_update(struct fh_clk* p_clk)
  1752. {
  1753. clk_handle(p_clk, &pll1);
  1754. }
  1755. //sdc0...
  1756. void sdc0_clk2x_update(struct fh_clk* p_clk)
  1757. {
  1758. clk_handle(p_clk, &pll1);
  1759. }
  1760. void sdc0_clk_update(struct fh_clk* p_clk)
  1761. {
  1762. clk_handle(p_clk, &sdc0_clk2x);
  1763. }
  1764. void sdc0_clk_out_update(struct fh_clk* p_clk)
  1765. {
  1766. clk_handle(p_clk, &sdc0_clk);
  1767. }
  1768. void sdc0_clk_sample_update(struct fh_clk* p_clk)
  1769. {
  1770. clk_handle(p_clk, &sdc0_clk2x);
  1771. }
  1772. void sdc0_clk_drv_update(struct fh_clk* p_clk)
  1773. {
  1774. clk_handle(p_clk, &sdc0_clk2x);
  1775. }
  1776. void sdc1_clk2x_update(struct fh_clk* p_clk)
  1777. {
  1778. clk_handle(p_clk, &pll1);
  1779. }
  1780. void sdc1_clk_update(struct fh_clk* p_clk)
  1781. {
  1782. clk_handle(p_clk, &sdc1_clk2x);
  1783. }
  1784. void sdc1_clk_out_update(struct fh_clk* p_clk)
  1785. {
  1786. clk_handle(p_clk, &sdc1_clk);
  1787. }
  1788. void sdc1_clk_sample_update(struct fh_clk* p_clk)
  1789. {
  1790. clk_handle(p_clk, &sdc1_clk2x);
  1791. }
  1792. void sdc1_clk_drv_update(struct fh_clk* p_clk)
  1793. {
  1794. clk_handle(p_clk, &sdc1_clk2x);
  1795. }
  1796. void eth_ref_clk_update(struct fh_clk* p_clk)
  1797. {
  1798. clk_handle(p_clk, &pll1);
  1799. }
  1800. void wdt_clk_update(struct fh_clk* p_clk)
  1801. {
  1802. clk_handle(p_clk, &cpu_pclk);
  1803. }
  1804. /**
  1805. * @brief System Clock Configuration
  1806. */
  1807. #define CLK_CONTROL_BASE PMU_REG_BASE
  1808. void rt_hw_clock_init(void)
  1809. {
  1810. struct fh_clk *p;
  1811. int i;
  1812. fh_clk_tree.c_base_addr = CLK_CONTROL_BASE;
  1813. fh_clk_tree.clk_head = fh_clk_array;
  1814. //first open all the clock..
  1815. FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0);
  1816. for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) {
  1817. p = fh_clk_tree.clk_head[i];
  1818. if (p->update_func)
  1819. p->update_func(p);
  1820. }
  1821. }
  1822. /***************
  1823. *
  1824. * new add
  1825. *
  1826. **************/
  1827. /* clocks cannot be de-registered no refcounting necessary */
  1828. struct fh_clk *clk_get(const char *name)
  1829. {
  1830. struct fh_clk *p;
  1831. int i;
  1832. for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) {
  1833. p = fh_clk_tree.clk_head[i];
  1834. if (!strcmp(p->name, name)) {
  1835. return p;
  1836. }
  1837. }
  1838. return RT_NULL;
  1839. }
  1840. //
  1841. //#define HAS_GATE (0)
  1842. //#define HAS_NO_GATE (1)
  1843. // rt_uint32_t gate_flag;
  1844. //#define CLK_UNGATE (0)
  1845. //#define CLK_GATE (1)
  1846. void clk_gate_control(struct fh_clk *p_clk, rt_uint32_t status)
  1847. {
  1848. if (status > CLK_GATE)
  1849. return;
  1850. if (p_clk->level == LEVEL_PERIPHERAL) {
  1851. switch (p_clk->clk.peri.peri_flag) {
  1852. case LEVEL_PERI_NORMAL:
  1853. if (p_clk->clk.peri.obj.normal.gate.gate_flag
  1854. == HAS_GATE) {
  1855. p_clk->clk.peri.obj.normal.gate.sw_status =
  1856. status;
  1857. } else {
  1858. rt_kprintf("[%-16.15s]: no gate...\t\n",
  1859. p_clk->name);
  1860. }
  1861. break;
  1862. case LEVEL_PERI_DDR:
  1863. if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) {
  1864. p_clk->clk.peri.obj.ddr.gate.sw_status = status;
  1865. } else {
  1866. rt_kprintf("[%-16.15s]: no gate...\t\n",
  1867. p_clk->name);
  1868. }
  1869. break;
  1870. default:
  1871. break;
  1872. }
  1873. p_clk->update_func(p_clk);
  1874. }
  1875. }
  1876. void clk_gate(struct fh_clk *p_clk)
  1877. {
  1878. clk_gate_control(p_clk, CLK_GATE);
  1879. }
  1880. void clk_ungate(struct fh_clk *p_clk)
  1881. {
  1882. clk_gate_control(p_clk, CLK_UNGATE);
  1883. }
  1884. rt_uint32_t clk_get_rate(struct fh_clk *p_clk)
  1885. {
  1886. rt_uint32_t rate;
  1887. //first update the status
  1888. p_clk->update_func(p_clk);
  1889. rate = p_clk->clk_out_rate;
  1890. return rate;
  1891. }
  1892. void clk_set_rate(struct fh_clk *p_clk, rt_uint32_t rate_value)
  1893. {
  1894. rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out;
  1895. if (p_clk->level == LEVEL_PERIPHERAL) {
  1896. switch (p_clk->clk.peri.peri_flag) {
  1897. case LEVEL_PERI_NORMAL:
  1898. clk_in = p_clk->parent->clk_out_rate;
  1899. div_flag = p_clk->clk.peri.obj.normal.div.div_flag;
  1900. pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value;
  1901. div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi;
  1902. baud_out = rate_value;
  1903. cal_baud_div(clk_in, div_flag, pre_div,
  1904. &p_clk->clk.peri.obj.normal.div.sw_div_value,
  1905. div_multi, baud_out);
  1906. break;
  1907. case LEVEL_PERI_DDR:
  1908. //rt_uint32_t mux0,mux1;
  1909. clk_in = p_clk->parent->clk_out_rate;
  1910. div_flag = p_clk->clk.peri.obj.ddr.div.div_flag;
  1911. pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value;
  1912. div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi;
  1913. baud_out = rate_value;
  1914. cal_baud_div(clk_in, div_flag, pre_div,
  1915. &p_clk->clk.peri.obj.ddr.div.sw_div_value,
  1916. div_multi, baud_out);
  1917. break;
  1918. case LEVEL_PERI_SDC:
  1919. fh_clk_debug(p_clk,
  1920. "sdc can't set baud,please set the 'sdcx_clk2x'\n");
  1921. break;
  1922. case LEVEL_PERI_GMAC:
  1923. fh_clk_debug(p_clk, "gmac not support set baud\n");
  1924. break;
  1925. default:
  1926. break;
  1927. }
  1928. p_clk->update_func(p_clk);
  1929. }
  1930. }
  1931. rt_uint32_t sdc_get_phase(struct fh_clk *p_clk)
  1932. {
  1933. if (p_clk->level == LEVEL_PERIPHERAL) {
  1934. if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) {
  1935. p_clk->update_func(p_clk);
  1936. return p_clk->clk.peri.obj.sdc.phase_diff;
  1937. }
  1938. }
  1939. return SDC_CLK_PARA_ERROR;
  1940. }
  1941. rt_uint32_t sdc_set_phase(struct fh_clk *p_clk, rt_uint32_t phase)
  1942. {
  1943. if (phase > DIFF_SDC_REFCLK_270)
  1944. return SDC_CLK_PARA_ERROR;
  1945. if (p_clk->level == LEVEL_PERIPHERAL) {
  1946. if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) {
  1947. p_clk->clk.peri.obj.sdc.phase_diff = phase;
  1948. p_clk->update_func(p_clk);
  1949. return SDC_CLK_PARA_OK;
  1950. }
  1951. }
  1952. return SDC_CLK_PARA_ERROR;
  1953. }
  1954. #ifdef FH_DBG_CLK
  1955. int fh_clk_nlist()
  1956. {
  1957. struct fh_clk *p;
  1958. int i;
  1959. for(i = 0;i<sizeof(fh_clk_array)/sizeof(struct fh_clk *);i++) {
  1960. p = fh_clk_tree.clk_head[i];
  1961. //p->update_func(p);
  1962. rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate);
  1963. }
  1964. return 0;
  1965. }
  1966. int fh_clk_glist()
  1967. {
  1968. struct fh_clk *p;
  1969. int i;
  1970. rt_kprintf("first bit set means has no gate..\n");
  1971. for(i = 0;i<sizeof(fh_clk_array)/sizeof(struct fh_clk *);i++) {
  1972. p = fh_clk_tree.clk_head[i];
  1973. //p->update_func(p);
  1974. if(!(p->gate & CLK_HAS_NO_GATE))
  1975. rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate);
  1976. else
  1977. rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name);
  1978. }
  1979. return 0;
  1980. }
  1981. #endif
  1982. #ifdef RT_USING_FINSH
  1983. #include <finsh.h>
  1984. #ifdef FH_DBG_CLK
  1985. FINSH_FUNCTION_EXPORT(fh_clk_nlist, fh_clk_name_list..);
  1986. FINSH_FUNCTION_EXPORT(fh_clk_glist, fh_clk_gate_list..);
  1987. #endif
  1988. #endif