buffers.h 3.6 KB

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  1. /*
  2. * Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without modification,
  6. * are permitted provided that the following conditions are met:
  7. *
  8. * o Redistributions of source code must retain the above copyright notice, this list
  9. * of conditions and the following disclaimer.
  10. *
  11. * o Redistributions in binary form must reproduce the above copyright notice, this
  12. * list of conditions and the following disclaimer in the documentation and/or
  13. * other materials provided with the distribution.
  14. *
  15. * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  16. * contributors may be used to endorse or promote products derived from this
  17. * software without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  20. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  21. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  23. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  25. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. */
  30. /*!
  31. * @file buffers.h
  32. * @definitions for ALL buffer memory space regions used by sdk drivers
  33. */
  34. #define IPU_DEFAULT_WORK_CLOCK 264000000
  35. #define IPU_DMA_MEMORY_START 0x40000000
  36. #define IPU_DMA_MEMORY_END 0x43FFFFFF
  37. #define HDMI_AUDIO_BUF_START 0x4fff0000
  38. #define HDMI_AUDIO_BUF_END 0x4fff4000
  39. #define CH23_EBA0 (IPU_DMA_MEMORY_START + 0x00000000)
  40. #define CH23_EBA1 (IPU_DMA_MEMORY_START + 0x00400000)
  41. #define CH27_EBA0 (IPU_DMA_MEMORY_START + 0x00800000)
  42. #define CH27_EBA1 (IPU_DMA_MEMORY_START + 0x00C00000)
  43. #define CH28_EBA0 (IPU_DMA_MEMORY_START + 0x01000000)
  44. #define CH28_EBA1 (IPU_DMA_MEMORY_START + 0x01400000)
  45. #define CH0_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
  46. #define CH0_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
  47. /*for dual video playback*/
  48. #define IPU1_CH23_EBA0 CH23_EBA0
  49. #define IPU1_CH23_EBA1 CH23_EBA1
  50. #define IPU2_CH23_EBA0 CH27_EBA0
  51. #define IPU2_CH23_EBA1 CH27_EBA1
  52. // for video playback after resizing&rotation
  53. #define CH22_EBA0 (IPU_DMA_MEMORY_START + 0x01800000)
  54. #define CH22_EBA1 (IPU_DMA_MEMORY_START + 0x01C00000)
  55. #define CH21_EBA0 (IPU_DMA_MEMORY_START + 0x02000000)
  56. #define CH21_EBA1 (IPU_DMA_MEMORY_START + 0x02400000)
  57. #define CH20_EBA0 (IPU_DMA_MEMORY_START + 0x02800000)
  58. #define CH20_EBA1 (IPU_DMA_MEMORY_START + 0x02C00000)
  59. /* put the TWO video instance on different CS to
  60. improve the performance.
  61. */
  62. #define VPU_WORK_BUFFERS (0x44100000)
  63. #define VIDEO_BUFFERS_START (0x48000000)
  64. #define VIDEO_BUFFERS_END (0x4FFFFFFF)
  65. /*OCRAM partition table*/
  66. #define VPU_SEC_AXI_START 0x00910000
  67. #define VPU_SEC_AXI_END 0x0091FFFF
  68. /* OCRAM ADMA buffer */
  69. #define USDHC_ADMA_BUFFER1 0x00907000
  70. #define USDHC_ADMA_BUFFER2 0x00908000
  71. #define USDHC_ADMA_BUFFER3 0x00909000
  72. #define USDHC_ADMA_BUFFER4 0x0090A000
  73. // USB buffers
  74. #define QH_BUFFER 0x00908000 // internal RAM
  75. #define TD_BUFFER 0x00908200 // internal RAM
  76. #define SATA_PROTOCOL_BUFFER_BASE 0x0090a000
  77. #define SATA_PROTOCOL_BUFFER_SIZE 0x1000
  78. #define SATA_TRANSFER_BUFFER_BASE 0x0090c000