emac.c 12 KB

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  1. #include "LPC177x_8x.h"
  2. #include "lpc177x_8x_pinsel.h"
  3. #include "emac.h"
  4. #include <rtthread.h>
  5. #include "lwipopts.h"
  6. #include <netif/ethernetif.h>
  7. #define EMAC_PHY_AUTO 0
  8. #define EMAC_PHY_10MBIT 1
  9. #define EMAC_PHY_100MBIT 2
  10. #define MAX_ADDR_LEN 6
  11. struct lpc17xx_emac
  12. {
  13. /* inherit from ethernet device */
  14. struct eth_device parent;
  15. rt_uint8_t phy_mode;
  16. /* interface address info. */
  17. rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
  18. };
  19. static struct lpc17xx_emac lpc17xx_emac_device;
  20. static struct rt_semaphore sem_lock;
  21. static struct rt_event tx_event;
  22. /* Local Function Prototypes */
  23. static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value);
  24. static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
  25. void ENET_IRQHandler(void)
  26. {
  27. rt_uint32_t status;
  28. /* enter interrupt */
  29. rt_interrupt_enter();
  30. status = LPC_EMAC->IntStatus;
  31. if (status & INT_RX_DONE)
  32. {
  33. /* Disable EMAC RxDone interrupts. */
  34. LPC_EMAC->IntEnable = INT_TX_DONE;
  35. /* a frame has been received */
  36. eth_device_ready(&(lpc17xx_emac_device.parent));
  37. }
  38. else if (status & INT_TX_DONE)
  39. {
  40. /* set event */
  41. rt_event_send(&tx_event, 0x01);
  42. }
  43. if (status & INT_RX_OVERRUN)
  44. {
  45. rt_kprintf("rx overrun\n");
  46. }
  47. if (status & INT_TX_UNDERRUN)
  48. {
  49. rt_kprintf("tx underrun\n");
  50. }
  51. /* Clear the interrupt. */
  52. LPC_EMAC->IntClear = status;
  53. /* leave interrupt */
  54. rt_interrupt_leave();
  55. }
  56. /* phy write */
  57. static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
  58. {
  59. unsigned int tout;
  60. LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
  61. LPC_EMAC->MWTD = Value;
  62. /* Wait utill operation completed */
  63. tout = 0;
  64. for (tout = 0; tout < MII_WR_TOUT; tout++)
  65. {
  66. if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
  67. {
  68. break;
  69. }
  70. }
  71. }
  72. /* phy read */
  73. static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
  74. {
  75. rt_uint32_t tout;
  76. LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
  77. LPC_EMAC->MCMD = MCMD_READ;
  78. /* Wait until operation completed */
  79. tout = 0;
  80. for (tout = 0; tout < MII_RD_TOUT; tout++)
  81. {
  82. if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
  83. {
  84. break;
  85. }
  86. }
  87. LPC_EMAC->MCMD = 0;
  88. return (LPC_EMAC->MRDD);
  89. }
  90. /* init rx descriptor */
  91. rt_inline void rx_descr_init (void)
  92. {
  93. rt_uint32_t i;
  94. for (i = 0; i < NUM_RX_FRAG; i++)
  95. {
  96. RX_DESC_PACKET(i) = RX_BUF(i);
  97. RX_DESC_CTRL(i) = RCTRL_INT | (ETH_FRAG_SIZE-1);
  98. RX_STAT_INFO(i) = 0;
  99. RX_STAT_HASHCRC(i) = 0;
  100. }
  101. /* Set EMAC Receive Descriptor Registers. */
  102. LPC_EMAC->RxDescriptor = RX_DESC_BASE;
  103. LPC_EMAC->RxStatus = RX_STAT_BASE;
  104. LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
  105. /* Rx Descriptors Point to 0 */
  106. LPC_EMAC->RxConsumeIndex = 0;
  107. }
  108. /* init tx descriptor */
  109. rt_inline void tx_descr_init (void)
  110. {
  111. rt_uint32_t i;
  112. for (i = 0; i < NUM_TX_FRAG; i++)
  113. {
  114. TX_DESC_PACKET(i) = TX_BUF(i);
  115. TX_DESC_CTRL(i) = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
  116. TX_STAT_INFO(i) = 0;
  117. }
  118. /* Set EMAC Transmit Descriptor Registers. */
  119. LPC_EMAC->TxDescriptor = TX_DESC_BASE;
  120. LPC_EMAC->TxStatus = TX_STAT_BASE;
  121. LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
  122. /* Tx Descriptors Point to 0 */
  123. LPC_EMAC->TxProduceIndex = 0;
  124. }
  125. /*
  126. TX_EN P1_4
  127. TXD0 P1_0
  128. TXD1 P1_1
  129. RXD0 P1_9
  130. RXD1 P1_10
  131. RX_ER P1_14
  132. CRS_DV P1_8
  133. MDC P1_16
  134. MDIO P1_17
  135. PHY_RESET P3_19
  136. REF_CLK P1_15
  137. */
  138. static rt_err_t lpc17xx_emac_init(rt_device_t dev)
  139. {
  140. /* Initialize the EMAC ethernet controller. */
  141. rt_uint32_t regv, tout;
  142. /* Power Up the EMAC controller. */
  143. LPC_SC->PCONP |= (1UL<<30);
  144. /* config RESET */
  145. PINSEL_ConfigPin(3, 19, 0);
  146. PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
  147. LPC_GPIO3->DIR |= 1<<19;
  148. LPC_GPIO3->CLR = 1<<19;
  149. /* Enable P1 Ethernet Pins. */
  150. PINSEL_ConfigPin(1, 0, 1); /**< P1_0 ENET_TXD0 */
  151. PINSEL_ConfigPin(1, 1, 1); /**< P1_1 ENET_TXD1 */
  152. PINSEL_ConfigPin(1, 4, 1); /**< P1_4 ENET_TX_EN */
  153. PINSEL_ConfigPin(1, 8, 1); /**< P1_8 ENET_CRS_DV */
  154. PINSEL_ConfigPin(1, 9, 1); /**< P1_9 ENET_RXD0 */
  155. PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
  156. PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
  157. PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
  158. PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
  159. PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
  160. LPC_GPIO3->SET = 1<<19;
  161. /* Reset all EMAC internal modules. */
  162. LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
  163. MAC1_SIM_RES | MAC1_SOFT_RES;
  164. LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
  165. /* A short delay after reset. */
  166. for (tout = 100; tout; tout--);
  167. /* Initialize MAC control registers. */
  168. LPC_EMAC->MAC1 = MAC1_PASS_ALL;
  169. LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
  170. LPC_EMAC->MAXF = ETH_MAX_FLEN;
  171. LPC_EMAC->CLRT = CLRT_DEF;
  172. LPC_EMAC->IPGR = IPGR_DEF;
  173. /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
  174. /* Enable Reduced MII interface. */
  175. LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
  176. for (tout = 100; tout; tout--);
  177. LPC_EMAC->MCFG = MCFG_CLK_DIV20;
  178. /* Enable Reduced MII interface. */
  179. LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
  180. /* Reset Reduced MII Logic. */
  181. LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
  182. for (tout = 100; tout; tout--);
  183. LPC_EMAC->SUPP = SUPP_SPEED;
  184. /* Put the PHY in reset mode */
  185. write_PHY (PHY_REG_BMCR, 0x8000);
  186. for (tout = 1000; tout; tout--);
  187. // /* Wait for hardware reset to end. */
  188. // for (tout = 0; tout < 0x100000; tout++)
  189. // {
  190. // regv = read_PHY (PHY_REG_BMCR);
  191. // if (!(regv & 0x8000))
  192. // {
  193. // /* Reset complete */
  194. // break;
  195. // }
  196. // }
  197. // if (tout >= 0x100000)
  198. // {
  199. // rt_kprintf("reset failed\r\n");
  200. // return -RT_ERROR; /* reset failed */
  201. // }
  202. // /* Check if this is a DP83848C PHY. */
  203. // id1 = read_PHY (PHY_REG_IDR1);
  204. // id2 = read_PHY (PHY_REG_IDR2);
  205. //
  206. // if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
  207. // return -RT_ERROR;
  208. /* Configure the PHY device */
  209. /* Configure the PHY device */
  210. switch (lpc17xx_emac_device.phy_mode)
  211. {
  212. case EMAC_PHY_AUTO:
  213. /* Use autonegotiation about the link speed. */
  214. write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
  215. /* Wait to complete Auto_Negotiation. */
  216. // for (tout = 0; tout < 0x100000; tout++)
  217. // {
  218. // regv = read_PHY (PHY_REG_BMSR);
  219. // if (regv & 0x0020)
  220. // {
  221. // /* Autonegotiation Complete. */
  222. // break;
  223. // }
  224. // }
  225. break;
  226. case EMAC_PHY_10MBIT:
  227. /* Connect at 10MBit */
  228. write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
  229. break;
  230. case EMAC_PHY_100MBIT:
  231. /* Connect at 100MBit */
  232. write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
  233. break;
  234. }
  235. if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
  236. // /* Check the link status. */
  237. // for (tout = 0; tout < 0x10000; tout++)
  238. // {
  239. // regv = read_PHY (PHY_REG_STS);
  240. // if (regv & 0x0001)
  241. // {
  242. // /* Link is on. */
  243. // break;
  244. // }
  245. // }
  246. // if (tout >= 0x10000) return -RT_ERROR;
  247. regv = 0x0004;
  248. /* Configure Full/Half Duplex mode. */
  249. if (regv & 0x0004)
  250. {
  251. /* Full duplex is enabled. */
  252. LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
  253. LPC_EMAC->Command |= CR_FULL_DUP;
  254. LPC_EMAC->IPGT = IPGT_FULL_DUP;
  255. }
  256. else
  257. {
  258. /* Half duplex mode. */
  259. LPC_EMAC->IPGT = IPGT_HALF_DUP;
  260. }
  261. /* Configure 100MBit/10MBit mode. */
  262. if (regv & 0x0002)
  263. {
  264. /* 10MBit mode. */
  265. LPC_EMAC->SUPP = 0;
  266. }
  267. else
  268. {
  269. /* 100MBit mode. */
  270. LPC_EMAC->SUPP = SUPP_SPEED;
  271. }
  272. /* Set the Ethernet MAC Address registers */
  273. LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
  274. LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
  275. LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
  276. /* Initialize Tx and Rx DMA Descriptors */
  277. rx_descr_init ();
  278. tx_descr_init ();
  279. /* Receive Broadcast and Perfect Match Packets */
  280. LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
  281. /* Reset all interrupts */
  282. LPC_EMAC->IntClear = 0xFFFF;
  283. /* Enable EMAC interrupts. */
  284. LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
  285. /* Enable receive and transmit mode of MAC Ethernet core */
  286. LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN);
  287. LPC_EMAC->MAC1 |= MAC1_REC_EN;
  288. /* Enable the ENET Interrupt */
  289. NVIC_EnableIRQ(ENET_IRQn);
  290. return RT_EOK;
  291. }
  292. static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
  293. {
  294. return RT_EOK;
  295. }
  296. static rt_err_t lpc17xx_emac_close(rt_device_t dev)
  297. {
  298. return RT_EOK;
  299. }
  300. static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  301. {
  302. rt_set_errno(-RT_ENOSYS);
  303. return 0;
  304. }
  305. static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  306. {
  307. rt_set_errno(-RT_ENOSYS);
  308. return 0;
  309. }
  310. static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
  311. {
  312. switch (cmd)
  313. {
  314. case NIOCTL_GADDR:
  315. /* get mac address */
  316. if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
  317. else return -RT_ERROR;
  318. break;
  319. default :
  320. break;
  321. }
  322. return RT_EOK;
  323. }
  324. /* EtherNet Device Interface */
  325. /* transmit packet. */
  326. rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
  327. {
  328. rt_uint32_t Index, IndexNext;
  329. struct pbuf *q;
  330. rt_uint8_t *ptr;
  331. /* calculate next index */
  332. IndexNext = LPC_EMAC->TxProduceIndex + 1;
  333. if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
  334. /* check whether block is full */
  335. while (IndexNext == LPC_EMAC->TxConsumeIndex)
  336. {
  337. rt_err_t result;
  338. rt_uint32_t recved;
  339. /* there is no block yet, wait a flag */
  340. result = rt_event_recv(&tx_event, 0x01,
  341. RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
  342. RT_ASSERT(result == RT_EOK);
  343. }
  344. /* lock EMAC device */
  345. rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
  346. /* get produce index */
  347. Index = LPC_EMAC->TxProduceIndex;
  348. /* calculate next index */
  349. IndexNext = LPC_EMAC->TxProduceIndex + 1;
  350. if(IndexNext > LPC_EMAC->TxDescriptorNumber)
  351. IndexNext = 0;
  352. /* copy data to tx buffer */
  353. q = p;
  354. ptr = (rt_uint8_t*)TX_BUF(Index);
  355. while (q)
  356. {
  357. memcpy(ptr, q->payload, q->len);
  358. ptr += q->len;
  359. q = q->next;
  360. }
  361. TX_DESC_CTRL(Index) &= ~0x7ff;
  362. TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
  363. /* change index to the next */
  364. LPC_EMAC->TxProduceIndex = IndexNext;
  365. /* unlock EMAC device */
  366. rt_sem_release(&sem_lock);
  367. return RT_EOK;
  368. }
  369. /* reception packet. */
  370. struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
  371. {
  372. struct pbuf* p;
  373. rt_uint32_t size;
  374. rt_uint32_t Index;
  375. /* init p pointer */
  376. p = RT_NULL;
  377. /* lock EMAC device */
  378. rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
  379. Index = LPC_EMAC->RxConsumeIndex;
  380. if(Index != LPC_EMAC->RxProduceIndex)
  381. {
  382. size = (RX_STAT_INFO(Index) & 0x7ff)+1;
  383. if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
  384. /* allocate buffer */
  385. p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
  386. if (p != RT_NULL)
  387. {
  388. struct pbuf* q;
  389. rt_uint8_t *ptr;
  390. ptr = (rt_uint8_t*)RX_BUF(Index);
  391. for (q = p; q != RT_NULL; q= q->next)
  392. {
  393. memcpy(q->payload, ptr, q->len);
  394. ptr += q->len;
  395. }
  396. }
  397. /* move Index to the next */
  398. if(++Index > LPC_EMAC->RxDescriptorNumber)
  399. Index = 0;
  400. /* set consume index */
  401. LPC_EMAC->RxConsumeIndex = Index;
  402. }
  403. else
  404. {
  405. /* Enable RxDone interrupt */
  406. LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
  407. }
  408. /* unlock EMAC device */
  409. rt_sem_release(&sem_lock);
  410. return p;
  411. }
  412. void lpc17xx_emac_hw_init(void)
  413. {
  414. rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
  415. rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
  416. /* set autonegotiation mode */
  417. lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
  418. // OUI 00-60-37 NXP Semiconductors
  419. lpc17xx_emac_device.dev_addr[0] = 0x00;
  420. lpc17xx_emac_device.dev_addr[1] = 0x60;
  421. lpc17xx_emac_device.dev_addr[2] = 0x37;
  422. /* set mac address: (only for test) */
  423. lpc17xx_emac_device.dev_addr[3] = 0x12;
  424. lpc17xx_emac_device.dev_addr[4] = 0x34;
  425. lpc17xx_emac_device.dev_addr[5] = 0x56;
  426. lpc17xx_emac_device.parent.parent.init = lpc17xx_emac_init;
  427. lpc17xx_emac_device.parent.parent.open = lpc17xx_emac_open;
  428. lpc17xx_emac_device.parent.parent.close = lpc17xx_emac_close;
  429. lpc17xx_emac_device.parent.parent.read = lpc17xx_emac_read;
  430. lpc17xx_emac_device.parent.parent.write = lpc17xx_emac_write;
  431. lpc17xx_emac_device.parent.parent.control = lpc17xx_emac_control;
  432. lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
  433. lpc17xx_emac_device.parent.eth_rx = lpc17xx_emac_rx;
  434. lpc17xx_emac_device.parent.eth_tx = lpc17xx_emac_tx;
  435. eth_device_init(&(lpc17xx_emac_device.parent), "e0");
  436. }
  437. #ifdef RT_USING_FINSH
  438. #include <finsh.h>
  439. void emac_dump()
  440. {
  441. rt_kprintf("Command : %08x\n", LPC_EMAC->Command);
  442. rt_kprintf("Status : %08x\n", LPC_EMAC->Status);
  443. rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
  444. rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
  445. rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
  446. rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
  447. }
  448. FINSH_FUNCTION_EXPORT(emac_dump, dump emac register);
  449. #endif