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serial.c 8.4 KB

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  1. /*
  2. * File : serial.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://openlab.rt-thread.com/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2006-08-23 Bernard first version
  13. */
  14. #include <rthw.h>
  15. #include <rtthread.h>
  16. #include "LPC24xx.h"
  17. #include "board.h"
  18. /* serial hardware register */
  19. #define REG8(d) (*((volatile unsigned char *)(d)))
  20. #define REG32(d) (*((volatile unsigned long *)(d)))
  21. #define UART_RBR(base) REG8(base + 0x00)
  22. #define UART_THR(base) REG8(base + 0x00)
  23. #define UART_IER(base) REG32(base + 0x04)
  24. #define UART_IIR(base) REG32(base + 0x08)
  25. #define UART_FCR(base) REG8(base + 0x08)
  26. #define UART_LCR(base) REG8(base + 0x0C)
  27. #define UART_MCR(base) REG8(base + 0x10)
  28. #define UART_LSR(base) REG8(base + 0x14)
  29. #define UART_MSR(base) REG8(base + 0x18)
  30. #define UART_SCR(base) REG8(base + 0x1C)
  31. #define UART_DLL(base) REG8(base + 0x00)
  32. #define UART_DLM(base) REG8(base + 0x04)
  33. #define UART_ACR(base) REG32(base + 0x20)
  34. #define UART_FDR(base) REG32(base + 0x28)
  35. #define UART_TER(base) REG8(base + 0x30)
  36. /* LPC serial device */
  37. struct rt_lpcserial
  38. {
  39. /* inherit from device */
  40. struct rt_device parent;
  41. rt_uint32_t hw_base;
  42. rt_uint32_t irqno;
  43. rt_uint32_t baudrate;
  44. /* reception field */
  45. rt_uint16_t save_index, read_index;
  46. rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
  47. };
  48. #ifdef RT_USING_UART1
  49. struct rt_lpcserial serial1;
  50. #endif
  51. #ifdef RT_USING_UART2
  52. struct rt_lpcserial serial2;
  53. #endif
  54. void rt_hw_serial_init(void);
  55. #define U0PINS 0x00000005
  56. void rt_hw_uart_isr(int irqno, void *param)
  57. {
  58. RT_UNUSED rt_uint32_t iir;
  59. struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
  60. RT_ASSERT(lpc_serial != RT_NULL)
  61. if (UART_LSR(lpc_serial->hw_base) & 0x01)
  62. {
  63. rt_base_t level;
  64. while (UART_LSR(lpc_serial->hw_base) & 0x01)
  65. {
  66. /* disable interrupt */
  67. level = rt_hw_interrupt_disable();
  68. /* read character */
  69. lpc_serial->rx_buffer[lpc_serial->save_index] =
  70. UART_RBR(lpc_serial->hw_base);
  71. lpc_serial->save_index ++;
  72. if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
  73. lpc_serial->save_index = 0;
  74. /* if the next position is read index, discard this 'read char' */
  75. if (lpc_serial->save_index == lpc_serial->read_index)
  76. {
  77. lpc_serial->read_index ++;
  78. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  79. lpc_serial->read_index = 0;
  80. }
  81. /* enable interrupt */
  82. rt_hw_interrupt_enable(level);
  83. }
  84. /* invoke callback */
  85. if(lpc_serial->parent.rx_indicate != RT_NULL)
  86. {
  87. lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
  88. }
  89. }
  90. /* clear interrupt source */
  91. iir = UART_IIR(lpc_serial->hw_base);
  92. /* acknowledge Interrupt */
  93. VICVectAddr = 0;
  94. }
  95. /**
  96. * @addtogroup LPC214x
  97. */
  98. /*@{*/
  99. static rt_err_t rt_serial_init (rt_device_t dev)
  100. {
  101. return RT_EOK;
  102. }
  103. static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
  104. {
  105. struct rt_lpcserial* lpc_serial;
  106. lpc_serial = (struct rt_lpcserial*) dev;
  107. RT_ASSERT(lpc_serial != RT_NULL);
  108. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  109. {
  110. /* init UART rx interrupt */
  111. UART_IER(lpc_serial->hw_base) = 0x01;
  112. /* install ISR */
  113. rt_hw_interrupt_install(lpc_serial->irqno,
  114. rt_hw_uart_isr, lpc_serial, RT_NULL);
  115. rt_hw_interrupt_umask(lpc_serial->irqno);
  116. }
  117. return RT_EOK;
  118. }
  119. static rt_err_t rt_serial_close(rt_device_t dev)
  120. {
  121. struct rt_lpcserial* lpc_serial;
  122. lpc_serial = (struct rt_lpcserial*) dev;
  123. RT_ASSERT(lpc_serial != RT_NULL);
  124. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  125. {
  126. /* disable UART rx interrupt */
  127. UART_IER(lpc_serial->hw_base) = 0x00;
  128. }
  129. return RT_EOK;
  130. }
  131. static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
  132. {
  133. return RT_EOK;
  134. }
  135. static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  136. {
  137. rt_uint8_t* ptr;
  138. struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
  139. RT_ASSERT(lpc_serial != RT_NULL);
  140. /* point to buffer */
  141. ptr = (rt_uint8_t*) buffer;
  142. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  143. {
  144. while (size)
  145. {
  146. /* interrupt receive */
  147. rt_base_t level;
  148. /* disable interrupt */
  149. level = rt_hw_interrupt_disable();
  150. if (lpc_serial->read_index != lpc_serial->save_index)
  151. {
  152. *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
  153. lpc_serial->read_index ++;
  154. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  155. lpc_serial->read_index = 0;
  156. }
  157. else
  158. {
  159. /* no data in rx buffer */
  160. /* enable interrupt */
  161. rt_hw_interrupt_enable(level);
  162. break;
  163. }
  164. /* enable interrupt */
  165. rt_hw_interrupt_enable(level);
  166. ptr ++; size --;
  167. }
  168. return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
  169. }
  170. else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
  171. {
  172. /* not support right now */
  173. RT_ASSERT(0);
  174. }
  175. /* polling mode */
  176. while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
  177. {
  178. /* Read Character */
  179. *ptr = UART_RBR(lpc_serial->hw_base);
  180. ptr ++;
  181. size --;
  182. }
  183. return (rt_size_t)ptr - (rt_size_t)buffer;
  184. }
  185. static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  186. {
  187. struct rt_lpcserial* lpc_serial;
  188. char *ptr;
  189. lpc_serial = (struct rt_lpcserial*) dev;
  190. if (dev->flag & RT_DEVICE_FLAG_INT_TX)
  191. {
  192. /* not support */
  193. RT_ASSERT(0);
  194. }
  195. else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
  196. {
  197. /* not support */
  198. RT_ASSERT(0);
  199. }
  200. /* polling write */
  201. ptr = (char *)buffer;
  202. if (dev->flag & RT_DEVICE_FLAG_STREAM)
  203. {
  204. /* stream mode */
  205. while (size)
  206. {
  207. if (*ptr == '\n')
  208. {
  209. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  210. UART_THR(lpc_serial->hw_base) = '\r';
  211. }
  212. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  213. UART_THR(lpc_serial->hw_base) = *ptr;
  214. ptr ++;
  215. size --;
  216. }
  217. }
  218. else
  219. {
  220. while (size)
  221. {
  222. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  223. UART_THR(lpc_serial->hw_base) = *ptr;
  224. ptr ++;
  225. size --;
  226. }
  227. }
  228. return (rt_size_t) ptr - (rt_size_t) buffer;
  229. }
  230. void rt_hw_serial_init(void)
  231. {
  232. struct rt_lpcserial* lpc_serial;
  233. #ifdef RT_USING_UART1
  234. lpc_serial = &serial1;
  235. lpc_serial->parent.type = RT_Device_Class_Char;
  236. lpc_serial->hw_base = 0xE000C000;
  237. lpc_serial->baudrate = 115200;
  238. lpc_serial->irqno = UART0_INT;
  239. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  240. lpc_serial->read_index = lpc_serial->save_index = 0;
  241. /* Enable UART0 RxD and TxD pins */
  242. PINSEL0 |= 0x50;
  243. /* 8 bits, no Parity, 1 Stop bit */
  244. UART_LCR(lpc_serial->hw_base) = 0x83;
  245. /* Setup Baudrate */
  246. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  247. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  248. /* DLAB = 0 */
  249. UART_LCR(lpc_serial->hw_base) = 0x03;
  250. lpc_serial->parent.type = RT_Device_Class_Char;
  251. lpc_serial->parent.init = rt_serial_init;
  252. lpc_serial->parent.open = rt_serial_open;
  253. lpc_serial->parent.close = rt_serial_close;
  254. lpc_serial->parent.read = rt_serial_read;
  255. lpc_serial->parent.write = rt_serial_write;
  256. lpc_serial->parent.control = rt_serial_control;
  257. lpc_serial->parent.user_data = RT_NULL;
  258. rt_device_register(&lpc_serial->parent,
  259. "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
  260. #endif
  261. #ifdef RT_USING_UART2
  262. lpc_serial = &serial2;
  263. lpc_serial->parent.type = RT_Device_Class_Char;
  264. lpc_serial->hw_base = 0xE0010000;
  265. lpc_serial->baudrate = 115200;
  266. lpc_serial->irqno = UART1_INT;
  267. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  268. lpc_serial->read_index = lpc_serial->save_index = 0;
  269. /* Enable UART1 RxD and TxD pins */
  270. PINSEL0 |= 0x05 << 16;
  271. /* 8 bits, no Parity, 1 Stop bit */
  272. UART_LCR(lpc_serial->hw_base) = 0x83;
  273. /* Setup Baudrate */
  274. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  275. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  276. /* DLAB = 0 */
  277. UART_LCR(lpc_serial->hw_base) = 0x03;
  278. lpc_serial->parent.type = RT_Device_Class_Char;
  279. lpc_serial->parent.init = rt_serial_init;
  280. lpc_serial->parent.open = rt_serial_open;
  281. lpc_serial->parent.close = rt_serial_close;
  282. lpc_serial->parent.read = rt_serial_read;
  283. lpc_serial->parent.write = rt_serial_write;
  284. lpc_serial->parent.control = rt_serial_control;
  285. lpc_serial->parent.user_data = RT_NULL;
  286. rt_device_register(&lpc_serial->parent,
  287. "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  288. #endif
  289. }
  290. /*@}*/