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hw_dmaaltd_regs.h

hw_dmaaltd_regs.h 8.8 KB
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  1. /*
    2. 

  2.  * @brief DMA master ROM API declarations and functions
    3. 

  3.  *
    4. 

  4.  * @note
    5. 

  5.  * Copyright(C) NXP Semiconductors, 2014
    6. 

  6.  * All rights reserved.
    7. 

  7.  *
    8. 

  8.  * @par
    9. 

  9.  * Software that is described herein is for illustrative purposes only
    10. 

  10.  * which provides customers with programming information regarding the
    11. 

  11.  * LPC products.  This software is supplied "AS IS" without any warranties of
    12. 

  12.  * any kind, and NXP Semiconductors and its licensor disclaim any and
    13. 

  13.  * all warranties, express or implied, including all implied warranties of
    14. 

  14.  * merchantability, fitness for a particular purpose and non-infringement of
    15. 

  15.  * intellectual property rights.  NXP Semiconductors assumes no responsibility
    16. 

  16.  * or liability for the use of the software, conveys no license or rights under any
    17. 

  17.  * patent, copyright, mask work right, or any other intellectual property rights in
    18. 

  18.  * or to any products. NXP Semiconductors reserves the right to make changes
    19. 

  19.  * in the software without notification. NXP Semiconductors also makes no
    20. 

  20.  * representation or warranty that such application will be suitable for the
    21. 

  21.  * specified use without further testing or modification.
    22. 

  22.  *
    23. 

  23.  * @par
    24. 

  24.  * Permission to use, copy, modify, and distribute this software and its
    25. 

  25.  * documentation is hereby granted, under NXP Semiconductors' and its
    26. 

  26.  * licensor's relevant copyrights in the software, without fee, provided that it
    27. 

  27.  * is used in conjunction with NXP Semiconductors microcontrollers.  This
    28. 

  28.  * copyright, permission, and disclaimer notice must appear in all copies of
    29. 

  29.  * this code.
    30. 

  30.  */
    31. 

  31. 

  32. #ifndef __HW_DMA_REGS_H_
    33. 

  33. #define __HW_DMA_REGS_H_
    34. 

  34. 

  35. /**
    36. 

  36.  * @brief DMA Controller shared registers structure
    37. 

  37.  */
    38. 

  38. typedef struct {					/*!< DMA shared registers structure */
    39. 

  39. 	volatile uint32_t  ENABLESET;		/*!< DMA Channel Enable read and Set for all DMA channels */
    40. 

  40. 	volatile  uint32_t  RESERVED0;
    41. 

  41. 	volatile  uint32_t  ENABLECLR;		/*!< DMA Channel Enable Clear for all DMA channels */
    42. 

  42. 	volatile  uint32_t  RESERVED1;
    43. 

  43. 	volatile  uint32_t  ACTIVE;			/*!< DMA Channel Active status for all DMA channels */
    44. 

  44. 	volatile  uint32_t  RESERVED2;
    45. 

  45. 	volatile  uint32_t  BUSY;			/*!< DMA Channel Busy status for all DMA channels */
    46. 

  46. 	volatile  uint32_t  RESERVED3;
    47. 

  47. 	volatile  uint32_t  ERRINT;			/*!< DMA Error Interrupt status for all DMA channels */
    48. 

  48. 	volatile  uint32_t  RESERVED4;
    49. 

  49. 	volatile  uint32_t  INTENSET;		/*!< DMA Interrupt Enable read and Set for all DMA channels */
    50. 

  50. 	volatile  uint32_t  RESERVED5;
    51. 

  51. 	volatile  uint32_t  INTENCLR;		/*!< DMA Interrupt Enable Clear for all DMA channels */
    52. 

  52. 	volatile  uint32_t  RESERVED6;
    53. 

  53. 	volatile  uint32_t  INTA;			/*!< DMA Interrupt A status for all DMA channels */
    54. 

  54. 	volatile  uint32_t  RESERVED7;
    55. 

  55. 	volatile  uint32_t  INTB;			/*!< DMA Interrupt B status for all DMA channels */
    56. 

  56. 	volatile  uint32_t  RESERVED8;
    57. 

  57. 	volatile  uint32_t  SETVALID;		/*!< DMA Set ValidPending control bits for all DMA channels */
    58. 

  58. 	volatile  uint32_t  RESERVED9;
    59. 

  59. 	volatile  uint32_t  SETTRIG;			/*!< DMA Set Trigger control bits for all DMA channels */
    60. 

  60. 	volatile  uint32_t  RESERVED10;
    61. 

  61. 	volatile  uint32_t  ABORT;			/*!< DMA Channel Abort control for all DMA channels */
    62. 

  62. } LPC_DMA_COMMON_T;
    63. 

  63. 

  64. /**
    65. 

  65.  * @brief DMA Controller shared registers structure
    66. 

  66.  */
    67. 

  67. typedef struct {					/*!< DMA channel register structure */
    68. 

  68. 	volatile  uint32_t  CFG;				/*!< DMA Configuration register */
    69. 

  69. 	volatile  uint32_t  CTLSTAT;			/*!< DMA Control and status register */
    70. 

  70. 	volatile  uint32_t  XFERCFG;			/*!< DMA Transfer configuration register */
    71. 

  71. 	volatile  uint32_t  RESERVED;
    72. 

  72. } LPC_DMA_CHANNEL_T;
    73. 

  73. 

  74. /* On LPC540XX, Max DMA channel is 22 */
    75. 

  75. #define MAX_DMA_CHANNEL         (22)
    76. 

  76. 

  77. /**
    78. 

  78.  * @brief DMA Controller register block structure
    79. 

  79.  */
    80. 

  80. typedef struct {					/*!< DMA Structure */
    81. 

  81. 	volatile  uint32_t  CTRL;			/*!< DMA control register */
    82. 

  82. 	volatile  uint32_t  INTSTAT;			/*!< DMA Interrupt status register */
    83. 

  83. 	volatile  uint32_t  SRAMBASE;		/*!< DMA SRAM address of the channel configuration table */
    84. 

  84. 	volatile  uint32_t  RESERVED2[5];
    85. 

  85. 	LPC_DMA_COMMON_T DMACOMMON[1];	/*!< DMA shared channel (common) registers */
    86. 

  86. 	volatile  uint32_t  RESERVED0[225];
    87. 

  87. 	LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL];	/*!< DMA channel registers */
    88. 

  88. } LPC_DMA_T;
    89. 

  89. 

  90. /* DMA interrupt status bits (common) */
    91. 

  91. #define DMA_INTSTAT_ACTIVEINT       0x2		/*!< Summarizes whether any enabled interrupts are pending */
    92. 

  92. #define DMA_INTSTAT_ACTIVEERRINT    0x4		/*!< Summarizes whether any error interrupts are pending */
    93. 

  93. 

  94. /* Support macro for DMA_CHDESC_T */
    95. 

  95. #define DMA_ADDR(addr)      ((uint32_t) (addr))
    96. 

  96. 

  97. /* Support definitions for setting the configuration of a DMA channel. You
    98. 

  98.    will need to get more information on these options from the User manual. */
    99. 

  99. #define DMA_CFG_PERIPHREQEN     (1 << 0)	/*!< Enables Peripheral DMA requests */
    100. 

  100. #define DMA_CFG_HWTRIGEN        (1 << 1)	/*!< Use hardware triggering via imput mux */
    101. 

  101. #define DMA_CFG_TRIGPOL_LOW     (0 << 4)	/*!< Hardware trigger is active low or falling edge */
    102. 

  102. #define DMA_CFG_TRIGPOL_HIGH    (1 << 4)	/*!< Hardware trigger is active high or rising edge */
    103. 

  103. #define DMA_CFG_TRIGTYPE_EDGE   (0 << 5)	/*!< Hardware trigger is edge triggered */
    104. 

  104. #define DMA_CFG_TRIGTYPE_LEVEL  (1 << 5)	/*!< Hardware trigger is level triggered */
    105. 

  105. #define DMA_CFG_TRIGBURST_SNGL  (0 << 6)	/*!< Single transfer. Hardware trigger causes a single transfer */
    106. 

  106. #define DMA_CFG_TRIGBURST_BURST (1 << 6)	/*!< Burst transfer (see UM) */
    107. 

  107. #define DMA_CFG_BURSTPOWER_1    (0 << 8)	/*!< Set DMA burst size to 1 transfer */
    108. 

  108. #define DMA_CFG_BURSTPOWER_2    (1 << 8)	/*!< Set DMA burst size to 2 transfers */
    109. 

  109. #define DMA_CFG_BURSTPOWER_4    (2 << 8)	/*!< Set DMA burst size to 4 transfers */
    110. 

  110. #define DMA_CFG_BURSTPOWER_8    (3 << 8)	/*!< Set DMA burst size to 8 transfers */
    111. 

  111. #define DMA_CFG_BURSTPOWER_16   (4 << 8)	/*!< Set DMA burst size to 16 transfers */
    112. 

  112. #define DMA_CFG_BURSTPOWER_32   (5 << 8)	/*!< Set DMA burst size to 32 transfers */
    113. 

  113. #define DMA_CFG_BURSTPOWER_64   (6 << 8)	/*!< Set DMA burst size to 64 transfers */
    114. 

  114. #define DMA_CFG_BURSTPOWER_128  (7 << 8)	/*!< Set DMA burst size to 128 transfers */
    115. 

  115. #define DMA_CFG_BURSTPOWER_256  (8 << 8)	/*!< Set DMA burst size to 256 transfers */
    116. 

  116. #define DMA_CFG_BURSTPOWER_512  (9 << 8)	/*!< Set DMA burst size to 512 transfers */
    117. 

  117. #define DMA_CFG_BURSTPOWER_1024 (10 << 8)	/*!< Set DMA burst size to 1024 transfers */
    118. 

  118. #define DMA_CFG_BURSTPOWER(n)   ((n) << 8)	/*!< Set DMA burst size to 2^n transfers, max n=10 */
    119. 

  119. #define DMA_CFG_SRCBURSTWRAP    (1 << 14)	/*!< Source burst wrapping is enabled for this DMA channel */
    120. 

  120. #define DMA_CFG_DSTBURSTWRAP    (1 << 15)	/*!< Destination burst wrapping is enabled for this DMA channel */
    121. 

  121. #define DMA_CFG_CHPRIORITY(p)   ((p) << 16)	/*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */
    122. 

  122. 

  123. /* DMA channel control and status register definitions */
    124. 

  124. #define DMA_CTLSTAT_VALIDPENDING    (1 << 0)	/*!< Valid pending flag for this channel */
    125. 

  125. #define DMA_CTLSTAT_TRIG            (1 << 2)	/*!< Trigger flag. Indicates that the trigger for this channel is currently set */
    126. 

  126. 

  127. /* DMA channel transfer configuration registers definitions */
    128. 

  128. #define DMA_XFERCFG_CFGVALID        (1 << 0)	/*!< Configuration Valid flag */
    129. 

  129. #define DMA_XFERCFG_RELOAD          (1 << 1)	/*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */
    130. 

  130. #define DMA_XFERCFG_SWTRIG          (1 << 2)	/*!< Software Trigger */
    131. 

  131. #define DMA_XFERCFG_CLRTRIG         (1 << 3)	/*!< Clear Trigger */
    132. 

  132. #define DMA_XFERCFG_SETINTA         (1 << 4)	/*!< Set Interrupt flag A for this channel to fire when descriptor is complete */
    133. 

  133. #define DMA_XFERCFG_SETINTB         (1 << 5)	/*!< Set Interrupt flag B for this channel to fire when descriptor is complete */
    134. 

  134. #define DMA_XFERCFG_WIDTH_8         (0 << 8)	/*!< 8-bit transfers are performed */
    135. 

  135. #define DMA_XFERCFG_WIDTH_16        (1 << 8)	/*!< 16-bit transfers are performed */
    136. 

  136. #define DMA_XFERCFG_WIDTH_32        (2 << 8)	/*!< 32-bit transfers are performed */
    137. 

  137. #define DMA_XFERCFG_SRCINC_0        (0 << 12)	/*!< DMA source address is not incremented after a transfer */
    138. 

  138. #define DMA_XFERCFG_SRCINC_1        (1 << 12)	/*!< DMA source address is incremented by 1 (width) after a transfer */
    139. 

  139. #define DMA_XFERCFG_SRCINC_2        (2 << 12)	/*!< DMA source address is incremented by 2 (width) after a transfer */
    140. 

  140. #define DMA_XFERCFG_SRCINC_4        (3 << 12)	/*!< DMA source address is incremented by 4 (width) after a transfer */
    141. 

  141. #define DMA_XFERCFG_DSTINC_0        (0 << 14)	/*!< DMA destination address is not incremented after a transfer */
    142. 

  142. #define DMA_XFERCFG_DSTINC_1        (1 << 14)	/*!< DMA destination address is incremented by 1 (width) after a transfer */
    143. 

  143. #define DMA_XFERCFG_DSTINC_2        (2 << 14)	/*!< DMA destination address is incremented by 2 (width) after a transfer */
    144. 

  144. #define DMA_XFERCFG_DSTINC_4        (3 << 14)	/*!< DMA destination address is incremented by 4 (width) after a transfer */
    145. 

  145. #define DMA_XFERCFG_XFERCOUNT(n)    ((n - 1) << 16)	/*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */
    146. 

  146. 

  147. #endif /* __HW_DMA_REGS_H_ */
    148.