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hw_i2c_common.h

hw_i2c_common.h 11 KB
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  1. /*
    2. 

  2.  * @brief I2C ROM API declarations and functions
    3. 

  3.  *
    4. 

  4.  * @note
    5. 

  5.  * Copyright(C) NXP Semiconductors, 2014
    6. 

  6.  * All rights reserved.
    7. 

  7.  *
    8. 

  8.  * @par
    9. 

  9.  * Software that is described herein is for illustrative purposes only
    10. 

  10.  * which provides customers with programming information regarding the
    11. 

  11.  * LPC products.  This software is supplied "AS IS" without any warranties of
    12. 

  12.  * any kind, and NXP Semiconductors and its licensor disclaim any and
    13. 

  13.  * all warranties, express or implied, including all implied warranties of
    14. 

  14.  * merchantability, fitness for a particular purpose and non-infringement of
    15. 

  15.  * intellectual property rights.  NXP Semiconductors assumes no responsibility
    16. 

  16.  * or liability for the use of the software, conveys no license or rights under any
    17. 

  17.  * patent, copyright, mask work right, or any other intellectual property rights in
    18. 

  18.  * or to any products. NXP Semiconductors reserves the right to make changes
    19. 

  19.  * in the software without notification. NXP Semiconductors also makes no
    20. 

  20.  * representation or warranty that such application will be suitable for the
    21. 

  21.  * specified use without further testing or modification.
    22. 

  22.  *
    23. 

  23.  * @par
    24. 

  24.  * Permission to use, copy, modify, and distribute this software and its
    25. 

  25.  * documentation is hereby granted, under NXP Semiconductors' and its
    26. 

  26.  * licensor's relevant copyrights in the software, without fee, provided that it
    27. 

  27.  * is used in conjunction with NXP Semiconductors microcontrollers.  This
    28. 

  28.  * copyright, permission, and disclaimer notice must appear in all copies of
    29. 

  29.  * this code.
    30. 

  30.  */
    31. 

  31. 

  32. #ifndef __HW_I2C_COMMON_H_
    33. 

  33. #define __HW_I2C_COMMON_H_
    34. 

  34. 

  35. /**
    36. 

  36.  * @brief I2C register block structure
    37. 

  37.  */
    38. 

  38. typedef struct {					/* I2C0 Structure         */
    39. 

  39. 	volatile uint32_t CFG;				/*!< I2C Configuration Register common for Master, Slave and Monitor */
    40. 

  40. 	volatile uint32_t STAT;				/*!< I2C Status Register common for Master, Slave and Monitor */
    41. 

  41. 	volatile uint32_t INTENSET;			/*!< I2C Interrupt Enable Set Register common for Master, Slave and Monitor */
    42. 

  42. 	volatile uint32_t INTENCLR;			/*!< I2C Interrupt Enable Clear Register common for Master, Slave and Monitor */
    43. 

  43. 	volatile uint32_t TIMEOUT;			/*!< I2C Timeout value Register */
    44. 

  44. 	volatile uint32_t CLKDIV;			/*!< I2C Clock Divider Register */
    45. 

  45. 	volatile uint32_t INTSTAT;			/*!< I2C Interrupt Status Register */
    46. 

  46. 	volatile uint32_t RESERVED0;
    47. 

  47. 	volatile uint32_t MSTCTL;			/*!< I2C Master Control Register */
    48. 

  48. 	volatile uint32_t MSTTIME;			/*!< I2C Master Time Register for SCL */
    49. 

  49. 	volatile uint32_t MSTDAT;			/*!< I2C Master Data Register */
    50. 

  50. 	volatile uint32_t RESERVED1[5];
    51. 

  51. 	volatile uint32_t SLVCTL;			/*!< I2C Slave Control Register */
    52. 

  52. 	volatile uint32_t SLVDAT;			/*!< I2C Slave Data Register */
    53. 

  53. 	volatile uint32_t SLVADR[4];		/*!< I2C Slave Address Registers */
    54. 

  54. 	volatile uint32_t SLVQUAL0;			/*!< I2C Slave Address Qualifier 0 Register */
    55. 

  55. 	volatile uint32_t RESERVED2[9];
    56. 

  56. 	volatile uint32_t MONRXDAT;			/*!< I2C Monitor Data Register */
    57. 

  57. } LPC_I2C_T;
    58. 

  58. 

  59. /*
    60. 

  60.  * @brief I2C Configuration register Bit definition
    61. 

  61.  */
    62. 

  62. #define I2C_CFG_MSTEN             (1 << 0)			/*!< Master Enable/Disable Bit */
    63. 

  63. #define I2C_CFG_SLVEN             (1 << 1)			/*!< Slave Enable/Disable Bit */
    64. 

  64. #define I2C_CFG_MONEN             (1 << 2)			/*!< Monitor Enable/Disable Bit */
    65. 

  65. #define I2C_CFG_TIMEOUTEN         (1 << 3)			/*!< Timeout Enable/Disable Bit */
    66. 

  66. #define I2C_CFG_MONCLKSTR         (1 << 4)			/*!< Monitor Clock Stretching Bit */
    67. 

  67. #define I2C_CFG_MASK              ((uint32_t) 0x1F)	/*!< Configuration Register Mask */
    68. 

  68. 

  69. /*
    70. 

  70.  * @brief I2C Status register Bit definition
    71. 

  71.  */
    72. 

  72. #define I2C_STAT_MSTPENDING       (1 << 0)		/*!< Master Pending Status Bit */
    73. 

  73. #define I2C_STAT_MSTSTATE         (0x7 << 1)	/*!< Master State Code */
    74. 

  74. #define I2C_STAT_MSTRARBLOSS      (1 << 4)		/*!< Master Arbitration Loss Bit */
    75. 

  75. #define I2C_STAT_MSTSTSTPERR      (1 << 6)		/*!< Master Start Stop Error Bit */
    76. 

  76. #define I2C_STAT_SLVPENDING       (1 << 8)		/*!< Slave Pending Status Bit */
    77. 

  77. #define I2C_STAT_SLVSTATE         (0x3 << 9)	/*!< Slave State Code */
    78. 

  78. #define I2C_STAT_SLVNOTSTR        (1 << 11)		/*!< Slave not stretching Clock Bit */
    79. 

  79. #define I2C_STAT_SLVIDX           (0x3 << 12)	/*!< Slave Address Index */
    80. 

  80. #define I2C_STAT_SLVSEL           (1 << 14)		/*!< Slave Selected Bit */
    81. 

  81. #define I2C_STAT_SLVDESEL         (1 << 15)		/*!< Slave Deselect Bit */
    82. 

  82. #define I2C_STAT_MONRDY           (1 << 16)		/*!< Monitor Ready Bit */
    83. 

  83. #define I2C_STAT_MONOV            (1 << 17)		/*!< Monitor Overflow Flag */
    84. 

  84. #define I2C_STAT_MONACTIVE        (1 << 18)		/*!< Monitor Active Flag */
    85. 

  85. #define I2C_STAT_MONIDLE          (1 << 19)		/*!< Monitor Idle Flag */
    86. 

  86. #define I2C_STAT_EVENTTIMEOUT     (1 << 24)		/*!< Event Timeout Interrupt Flag */
    87. 

  87. #define I2C_STAT_SCLTIMEOUT       (1 << 25)		/*!< SCL Timeout Interrupt Flag */
    88. 

  88. 

  89. #define I2C_STAT_MSTCODE_IDLE       (0)			/*!< Master Idle State Code */
    90. 

  90. #define I2C_STAT_MSTCODE_RXREADY    (1)			/*!< Master Receive Ready State Code */
    91. 

  91. #define I2C_STAT_MSTCODE_TXREADY    (2)			/*!< Master Transmit Ready State Code */
    92. 

  92. #define I2C_STAT_MSTCODE_NACKADR    (3)			/*!< Master NACK by slave on address State Code */
    93. 

  93. #define I2C_STAT_MSTCODE_NACKDAT    (4)			/*!< Master NACK by slave on data State Code */
    94. 

  94. 

  95. #define I2C_STAT_SLVCODE_ADDR         (0)		/*!< Master Idle State Code */
    96. 

  96. #define I2C_STAT_SLVCODE_RX           (1)		/*!< Received data is available Code */
    97. 

  97. #define I2C_STAT_SLVCODE_TX           (2)		/*!< Data can be transmitted Code */
    98. 

  98. 

  99. /*
    100. 

  100.  * @brief I2C Interrupt Enable Set register Bit definition
    101. 

  101.  */
    102. 

  102. #define I2C_INTENSET_MSTPENDING       (1 << 0)		/*!< Master Pending Interrupt Enable Bit */
    103. 

  103. #define I2C_INTENSET_MSTRARBLOSS      (1 << 4)		/*!< Master Arbitration Loss Interrupt Enable Bit */
    104. 

  104. #define I2C_INTENSET_MSTSTSTPERR      (1 << 6)		/*!< Master Start Stop Error Interrupt Enable Bit */
    105. 

  105. #define I2C_INTENSET_SLVPENDING       (1 << 8)		/*!< Slave Pending Interrupt Enable Bit */
    106. 

  106. #define I2C_INTENSET_SLVNOTSTR        (1 << 11)		/*!< Slave not stretching Clock Interrupt Enable Bit */
    107. 

  107. #define I2C_INTENSET_SLVDESEL         (1 << 15)		/*!< Slave Deselect Interrupt Enable Bit */
    108. 

  108. #define I2C_INTENSET_MONRDY           (1 << 16)		/*!< Monitor Ready Interrupt Enable Bit */
    109. 

  109. #define I2C_INTENSET_MONOV            (1 << 17)		/*!< Monitor Overflow Interrupt Enable Bit */
    110. 

  110. #define I2C_INTENSET_MONIDLE          (1 << 19)		/*!< Monitor Idle Interrupt Enable Bit */
    111. 

  111. #define I2C_INTENSET_EVENTTIMEOUT     (1 << 24)		/*!< Event Timeout Interrupt Enable Bit */
    112. 

  112. #define I2C_INTENSET_SCLTIMEOUT       (1 << 25)		/*!< SCL Timeout Interrupt Enable Bit */
    113. 

  113. 

  114. /*
    115. 

  115.  * @brief I2C Interrupt Enable Clear register Bit definition
    116. 

  116.  */
    117. 

  117. #define I2C_INTENCLR_MSTPENDING       (1 << 0)		/*!< Master Pending Interrupt Clear Bit */
    118. 

  118. #define I2C_INTENCLR_MSTRARBLOSS      (1 << 4)		/*!< Master Arbitration Loss Interrupt Clear Bit */
    119. 

  119. #define I2C_INTENCLR_MSTSTSTPERR      (1 << 6)		/*!< Master Start Stop Error Interrupt Clear Bit */
    120. 

  120. #define I2C_INTENCLR_SLVPENDING       (1 << 8)		/*!< Slave Pending Interrupt Clear Bit */
    121. 

  121. #define I2C_INTENCLR_SLVNOTSTR        (1 << 11)		/*!< Slave not stretching Clock Interrupt Clear Bit */
    122. 

  122. #define I2C_INTENCLR_SLVDESEL         (1 << 15)		/*!< Slave Deselect Interrupt Clear Bit */
    123. 

  123. #define I2C_INTENCLR_MONRDY           (1 << 16)		/*!< Monitor Ready Interrupt Clear Bit */
    124. 

  124. #define I2C_INTENCLR_MONOV            (1 << 17)		/*!< Monitor Overflow Interrupt Clear Bit */
    125. 

  125. #define I2C_INTENCLR_MONIDLE          (1 << 19)		/*!< Monitor Idle Interrupt Clear Bit */
    126. 

  126. #define I2C_INTENCLR_EVENTTIMEOUT     (1 << 24)		/*!< Event Timeout Interrupt Clear Bit */
    127. 

  127. #define I2C_INTENCLR_SCLTIMEOUT       (1 << 25)		/*!< SCL Timeout Interrupt Clear Bit */
    128. 

  128. 

  129. /*
    130. 

  130.  * @brief I2C TimeOut Value Macro
    131. 

  131.  */
    132. 

  132. #define I2C_TIMEOUT_VAL(n)              (((uint32_t) ((n) - 1) & 0xFFF0) | 0x000F)		/*!< Macro for Timeout value register */
    133. 

  133. 

  134. /*
    135. 

  135.  * @brief I2C Interrupt Status register Bit definition
    136. 

  136.  */
    137. 

  137. #define I2C_INTSTAT_MSTPENDING      (1 << 0)		/*!< Master Pending Interrupt Status Bit */
    138. 

  138. #define I2C_INTSTAT_MSTRARBLOSS     (1 << 4)		/*!< Master Arbitration Loss Interrupt Status Bit */
    139. 

  139. #define I2C_INTSTAT_MSTSTSTPERR     (1 << 6)		/*!< Master Start Stop Error Interrupt Status Bit */
    140. 

  140. #define I2C_INTSTAT_SLVPENDING      (1 << 8)		/*!< Slave Pending Interrupt Status Bit */
    141. 

  141. #define I2C_INTSTAT_SLVNOTSTR       (1 << 11)		/*!< Slave not stretching Clock Interrupt Status Bit */
    142. 

  142. #define I2C_INTSTAT_SLVDESEL        (1 << 15)		/*!< Slave Deselect Interrupt Status Bit */
    143. 

  143. #define I2C_INTSTAT_MONRDY          (1 << 16)		/*!< Monitor Ready Interrupt Status Bit */
    144. 

  144. #define I2C_INTSTAT_MONOV           (1 << 17)		/*!< Monitor Overflow Interrupt Status Bit */
    145. 

  145. #define I2C_INTSTAT_MONIDLE         (1 << 19)		/*!< Monitor Idle Interrupt Status Bit */
    146. 

  146. #define I2C_INTSTAT_EVENTTIMEOUT    (1 << 24)		/*!< Event Timeout Interrupt Status Bit */
    147. 

  147. #define I2C_INTSTAT_SCLTIMEOUT      (1 << 25)		/*!< SCL Timeout Interrupt Status Bit */
    148. 

  148. 

  149. /*
    150. 

  150.  * @brief I2C Master Control register Bit definition
    151. 

  151.  */
    152. 

  152. #define I2C_MSTCTL_MSTCONTINUE  (1 << 0)		/*!< Master Continue Bit */
    153. 

  153. #define I2C_MSTCTL_MSTSTART     (1 << 1)		/*!< Master Start Control Bit */
    154. 

  154. #define I2C_MSTCTL_MSTSTOP      (1 << 2)		/*!< Master Stop Control Bit */
    155. 

  155. #define I2C_MSTCTL_MSTDMA       (1 << 3)		/*!< Master DMA Enable Bit */
    156. 

  156. 

  157. /*
    158. 

  158.  * @brief I2C Master Time Register Field definition
    159. 

  159.  */
    160. 

  160. #define I2C_MSTTIME_MSTSCLLOW   (0x07 << 0)		/*!< Master SCL Low Time field */
    161. 

  161. #define I2C_MSTTIME_MSTSCLHIGH  (0x07 << 4)		/*!< Master SCL High Time field */
    162. 

  162. 

  163. /*
    164. 

  164.  * @brief I2C Master Data Mask
    165. 

  165.  */
    166. 

  166. #define I2C_MSTDAT_DATAMASK         ((uint32_t) 0x00FF << 0)	/*!< Master data mask */
    167. 

  167. 

  168. /*
    169. 

  169.  * @brief I2C Slave Control register Bit definition
    170. 

  170.  */
    171. 

  171. #define I2C_SLVCTL_SLVCONTINUE    (1 << 0)		/*!< Slave Continue Bit */
    172. 

  172. #define I2C_SLVCTL_SLVNACK        (1 << 1)		/*!< Slave NACK Bit */
    173. 

  173. #define I2C_SLVCTL_SLVDMA         (1 << 3)		/*!< Slave DMA Enable Bit */
    174. 

  174. 

  175. /*
    176. 

  176.  * @brief I2C Slave Data Mask
    177. 

  177.  */
    178. 

  178. #define I2C_SLVDAT_DATAMASK         ((uint32_t) 0x00FF << 0)	/*!< Slave data mask */
    179. 

  179. 

  180. /*
    181. 

  181.  * @brief I2C Slave Address register Bit definition
    182. 

  182.  */
    183. 

  183. #define I2C_SLVADR_SADISABLE      (1 << 0)		/*!< Slave Address n Disable Bit */
    184. 

  184. #define I2C_SLVADR_SLVADR         (0x7F << 1)	/*!< Slave Address field */
    185. 

  185. #define I2C_SLVADR_MASK           ((uint32_t) 0x00FF)	/*!< Slave Address Mask */
    186. 

  186. 

  187. /*
    188. 

  188.  * @brief I2C Slave Address Qualifier 0 Register Bit definition
    189. 

  189.  */
    190. 

  190. #define I2C_SLVQUAL_QUALMODE0     (1 << 0)		/*!< Slave Qualifier Mode Enable Bit */
    191. 

  191. #define I2C_SLVQUAL_SLVQUAL0      (0x7F << 1)	/*!< Slave Qualifier Address for Address 0 */
    192. 

  192. 

  193. /*
    194. 

  194.  * @brief I2C Monitor Data Register Bit definition
    195. 

  195.  */
    196. 

  196. #define I2C_MONRXDAT_DATA         (0xFF << 0)		/*!< Monitor Function Receive Data Field */
    197. 

  197. #define I2C_MONRXDAT_MONSTART     (1 << 8)			/*!< Monitor Received Start Bit */
    198. 

  198. #define I2C_MONRXDAT_MONRESTART   (1 << 9)			/*!< Monitor Received Repeated Start Bit */
    199. 

  199. #define I2C_MONRXDAT_MONNACK      (1 << 10)			/*!< Monitor Received Nack Bit */
    200. 

  200. 

  201. #endif /* __HW_I2C_COMMON_H_ */
    202.