reg_crc.h 4.6 KB

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  1. /** @file reg_crc.h
  2. * @brief CRC Register Layer Header File
  3. * @date 29.May.2013
  4. * @version 03.05.02
  5. *
  6. * This file contains:
  7. * - Definitions
  8. * - Types
  9. * - Interface Prototypes
  10. * .
  11. * which are relevant for the CRC driver.
  12. */
  13. /* (c) Texas Instruments 2009-2013, All rights reserved. */
  14. #ifndef __REG_CRC_H__
  15. #define __REG_CRC_H__
  16. #include "sys_common.h"
  17. /* USER CODE BEGIN (0) */
  18. /* USER CODE END */
  19. /* Crc Register Frame Definition */
  20. /** @struct crcBase
  21. * @brief CRC Register Frame Definition
  22. *
  23. * This type is used to access the CRC Registers.
  24. */
  25. /** @typedef crcBASE_t
  26. * @brief CRC Register Frame Type Definition
  27. *
  28. * This type is used to access the CRC Registers.
  29. */
  30. typedef volatile struct crcBase
  31. {
  32. uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/
  33. uint32 rsvd1; /**< 0x0004: reserved >**/
  34. uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/
  35. uint32 rsvd2; /**< 0x000C: reserved >**/
  36. uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/
  37. uint32 rsvd3; /**< 0x0014: reserved >**/
  38. uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/
  39. uint32 rsvd4; /**< 0x001C: reserved >**/
  40. uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/
  41. uint32 rsvd5; /**< 0x0024: reserved >**/
  42. uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/
  43. uint32 rsvd6; /**< 0x002C: reserved >**/
  44. uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/
  45. uint32 rsvd7; /**< 0x0034: reserved >**/
  46. uint32 BUSY; /**< 0x0038: CRC Busy Register >**/
  47. uint32 rsvd8; /**< 0x003C: reserved >**/
  48. uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/
  49. uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/
  50. uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/
  51. uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/
  52. uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/
  53. uint32 rsvd9[3]; /**< 0x0054: reserved >**/
  54. uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/
  55. uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/
  56. uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/
  57. uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/
  58. uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/
  59. uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/
  60. uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/
  61. uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/
  62. uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/
  63. uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/
  64. uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/
  65. uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/
  66. uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/
  67. uint32 rsvd10[3]; /**< 0x0094: reserved >**/
  68. uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/
  69. uint32 PSA_SIGREGH2; /**< 0x00A8: Channel 2 PSA signature high register >**/
  70. uint32 REGL2; /**< 0x00AC: Channel 2 CRC value low register >**/
  71. uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/
  72. uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/
  73. uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/
  74. uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/
  75. uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/
  76. }crcBASE_t;
  77. /** @def crcREG
  78. * @brief CRC Register Frame Pointer
  79. *
  80. * This pointer is used by the CRC driver to access the CRC registers.
  81. */
  82. #define crcREG ((crcBASE_t *)0xFE000000U)
  83. /* USER CODE BEGIN (1) */
  84. /* USER CODE END */
  85. #endif