system.h 12 KB

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  1. /** @file system.h
  2. * @brief System Driver Header File
  3. * @date 29.May.2013
  4. * @version 03.05.02
  5. *
  6. * This file contains:
  7. * - Definitions
  8. * - Types
  9. * .
  10. * which are relevant for the System driver.
  11. */
  12. /* (c) Texas Instruments 2009-2013, All rights reserved. */
  13. #ifndef __SYS_SYSTEM_H__
  14. #define __SYS_SYSTEM_H__
  15. #include "reg_system.h"
  16. #include "reg_flash.h"
  17. #include "reg_tcram.h"
  18. #include "gio.h"
  19. /* USER CODE BEGIN (0) */
  20. /* USER CODE END */
  21. /* System General Definitions */
  22. /** @enum systemInterrupt
  23. * @brief Alias names for clock sources
  24. *
  25. * This enumeration is used to provide alias names for the clock sources:
  26. * - IRQ
  27. * - FIQ
  28. */
  29. enum systemInterrupt
  30. {
  31. SYS_IRQ, /**< Alias for IRQ interrupt */
  32. SYS_FIQ /**< Alias for FIQ interrupt */
  33. };
  34. /** @enum systemClockSource
  35. * @brief Alias names for clock sources
  36. *
  37. * This enumeration is used to provide alias names for the clock sources:
  38. * - Oscillator
  39. * - Pll1
  40. * - External1
  41. * - Low Power Oscillator Low
  42. * - Low Power Oscillator High
  43. * - PLL2
  44. * - External2
  45. * - Synchronous VCLK1
  46. */
  47. enum systemClockSource
  48. {
  49. SYS_OSC = 0U, /**< Alias for oscillator clock Source */
  50. SYS_PLL1 = 1U, /**< Alias for Pll1 clock Source */
  51. SYS_EXTERNAL1 = 3U, /**< Alias for external clock Source */
  52. SYS_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */
  53. SYS_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */
  54. SYS_PLL2 = 6U, /**< Alias for Pll2 clock Source */
  55. SYS_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */
  56. SYS_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */
  57. };
  58. #define SYS_DOZE_MODE 0x000F3F02U
  59. #define SYS_SNOOZE_MODE 0x000F3F03U
  60. #define SYS_SLEEP_MODE 0x000FFFFFU
  61. #define LPO_TRIM_VALUE (((*(volatile uint32 *)0xF00801B4U) & 0xFFFF0000U)>>16U)
  62. #define SYS_EXCEPTION (*(volatile uint32 *)0xFFFFFFE4U)
  63. #define POWERON_RESET 0x8000U
  64. #define OSC_FAILURE_RESET 0x4000U
  65. #define WATCHDOG_RESET 0x2000U
  66. #define ICEPICK_RESET 0x2000U
  67. #define CPU_RESET 0x0020U
  68. #define SW_RESET 0x0010U
  69. #define WATCHDOG_STATUS (*(volatile uint32 *)0xFFFFFC98U)
  70. #define DEVICE_ID_REV (*(volatile uint32 *)0xFFFFFFF0U)
  71. /** @def OSC_FREQ
  72. * @brief Oscillator clock source exported from HALCoGen GUI
  73. *
  74. * Oscillator clock source exported from HALCoGen GUI
  75. */
  76. #define OSC_FREQ 16.0F
  77. /** @def PLL1_FREQ
  78. * @brief PLL 1 clock source exported from HALCoGen GUI
  79. *
  80. * PLL 1 clock source exported from HALCoGen GUI
  81. */
  82. #define PLL1_FREQ 200.00F
  83. /** @def LPO_LF_FREQ
  84. * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI
  85. *
  86. * LPO Low Freq Oscillator source exported from HALCoGen GUI
  87. */
  88. #define LPO_LF_FREQ 0.080F
  89. /** @def LPO_HF_FREQ
  90. * @brief LPO High Freq Oscillator source exported from HALCoGen GUI
  91. *
  92. * LPO High Freq Oscillator source exported from HALCoGen GUI
  93. */
  94. #define LPO_HF_FREQ 10.000F
  95. /** @def PLL1_FREQ
  96. * @brief PLL 2 clock source exported from HALCoGen GUI
  97. *
  98. * PLL 2 clock source exported from HALCoGen GUI
  99. */
  100. #define PLL2_FREQ 200.00F
  101. /** @def GCLK_FREQ
  102. * @brief GCLK domain frequency exported from HALCoGen GUI
  103. *
  104. * GCLK domain frequency exported from HALCoGen GUI
  105. */
  106. #define GCLK_FREQ 200.000F
  107. /** @def HCLK_FREQ
  108. * @brief HCLK domain frequency exported from HALCoGen GUI
  109. *
  110. * HCLK domain frequency exported from HALCoGen GUI
  111. */
  112. #define HCLK_FREQ 200.000F
  113. /** @def RTI_FREQ
  114. * @brief RTI Clock frequency exported from HALCoGen GUI
  115. *
  116. * RTI Clock frequency exported from HALCoGen GUI
  117. */
  118. #define RTI_FREQ 100.000F
  119. /** @def AVCLK1_FREQ
  120. * @brief AVCLK1 Domain frequency exported from HALCoGen GUI
  121. *
  122. * AVCLK Domain frequency exported from HALCoGen GUI
  123. */
  124. #define AVCLK1_FREQ 100.000F
  125. /** @def AVCLK2_FREQ
  126. * @brief AVCLK2 Domain frequency exported from HALCoGen GUI
  127. *
  128. * AVCLK2 Domain frequency exported from HALCoGen GUI
  129. */
  130. #define AVCLK2_FREQ 100.0F
  131. /** @def AVCLK3_FREQ
  132. * @brief AVCLK3 Domain frequency exported from HALCoGen GUI
  133. *
  134. * AVCLK3 Domain frequency exported from HALCoGen GUI
  135. */
  136. #define AVCLK3_FREQ 100.000F
  137. /** @def VCLK1_FREQ
  138. * @brief VCLK1 Domain frequency exported from HALCoGen GUI
  139. *
  140. * VCLK1 Domain frequency exported from HALCoGen GUI
  141. */
  142. #define VCLK1_FREQ 100.000F
  143. /** @def VCLK2_FREQ
  144. * @brief VCLK2 Domain frequency exported from HALCoGen GUI
  145. *
  146. * VCLK2 Domain frequency exported from HALCoGen GUI
  147. */
  148. #define VCLK2_FREQ 100.000F
  149. /** @def SYS_PRE1
  150. * @brief Alias name for RTI1CLK PRE clock source
  151. *
  152. * This is an alias name for the RTI1CLK pre clock source.
  153. * This can be either:
  154. * - Oscillator
  155. * - Pll
  156. * - 32 kHz Oscillator
  157. * - External
  158. * - Low Power Oscillator Low
  159. * - Low Power Oscillator High
  160. * - Flexray Pll
  161. */
  162. /*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
  163. #define SYS_PRE1 SYS_PLL1
  164. /** @def SYS_PRE2
  165. * @brief Alias name for RTI2CLK pre clock source
  166. *
  167. * This is an alias name for the RTI2CLK pre clock source.
  168. * This can be either:
  169. * - Oscillator
  170. * - Pll
  171. * - 32 kHz Oscillator
  172. * - External
  173. * - Low Power Oscillator Low
  174. * - Low Power Oscillator High
  175. * - Flexray Pll
  176. */
  177. /*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
  178. #define SYS_PRE2 SYS_PLL1
  179. /* Configuration registers */
  180. typedef struct system_config_reg
  181. {
  182. uint32 CONFIG_SYSPC1;
  183. uint32 CONFIG_SYSPC2;
  184. uint32 CONFIG_SYSPC7;
  185. uint32 CONFIG_SYSPC8;
  186. uint32 CONFIG_SYSPC9;
  187. uint32 CONFIG_CSDIS;
  188. uint32 CONFIG_CDDIS;
  189. uint32 CONFIG_GHVSRC;
  190. uint32 CONFIG_VCLKASRC;
  191. uint32 CONFIG_RCLKSRC;
  192. uint32 CONFIG_MSTGCR;
  193. uint32 CONFIG_MINITGCR;
  194. uint32 CONFIG_MSINENA;
  195. uint32 CONFIG_PLLCTL1;
  196. uint32 CONFIG_PLLCTL2;
  197. uint32 CONFIG_UERFLAG;
  198. uint32 CONFIG_LPOMONCTL;
  199. uint32 CONFIG_CLKTEST;
  200. uint32 CONFIG_DFTCTRLREG1;
  201. uint32 CONFIG_DFTCTRLREG2;
  202. uint32 CONFIG_GPREG1;
  203. uint32 CONFIG_RAMGCR;
  204. uint32 CONFIG_BMMCR1;
  205. uint32 CONFIG_MMUGCR;
  206. uint32 CONFIG_CLKCNTL;
  207. uint32 CONFIG_ECPCNTL;
  208. uint32 CONFIG_DEVCR1;
  209. uint32 CONFIG_SYSECR;
  210. uint32 CONFIG_PLLCTL3;
  211. uint32 CONFIG_STCCLKDIV;
  212. uint32 CONFIG_CLK2CNTL;
  213. uint32 CONFIG_VCLKACON1;
  214. uint32 CONFIG_CLKSLIP;
  215. uint32 CONFIG_EFC_CTLEN;
  216. } system_config_reg_t;
  217. /* Configuration registers initial value */
  218. #define SYS_SYSPC1_CONFIGVALUE 0U
  219. #define SYS_SYSPC2_CONFIGVALUE 1U
  220. #define SYS_SYSPC7_CONFIGVALUE 0U
  221. #define SYS_SYSPC8_CONFIGVALUE 0U
  222. #define SYS_SYSPC9_CONFIGVALUE 1U
  223. #define SYS_CSDIS_CONFIGVALUE 0x00000000U\
  224. | 0x00000000U \
  225. | 0x00000008U \
  226. | 0x00000080U \
  227. | 0x00000000U \
  228. | 0x00000000U \
  229. | 0x00000000U\
  230. | (1U << 2U)
  231. #define SYS_CDDIS_CONFIGVALUE (FALSE << 4U )\
  232. |(TRUE << 5U )\
  233. |(FALSE << 8U )\
  234. |(FALSE << 10U)\
  235. |(FALSE << 11U)
  236. #define SYS_GHVSRC_CONFIGVALUE (SYS_PLL1 << 24U) \
  237. | (SYS_PLL1 << 16U) \
  238. | SYS_PLL1
  239. #define SYS_VCLKASRC_CONFIGVALUE (SYS_VCLK << 8U)\
  240. | SYS_VCLK
  241. #define SYS_RCLKSRC_CONFIGVALUE (1U << 24U)\
  242. | (SYS_VCLK << 16U)\
  243. | (1U << 8U)\
  244. | SYS_VCLK
  245. #define SYS_MSTGCR_CONFIGVALUE 0x00000105U
  246. #define SYS_MINITGCR_CONFIGVALUE 0x5U
  247. #define SYS_MSINENA_CONFIGVALUE 0U
  248. #define SYS_PLLCTL1_CONFIGVALUE_1 0x00000000U \
  249. | 0x20000000U \
  250. | ((0x1FU)<< 24U) \
  251. | 0x00000000U \
  252. | ((6U - 1U)<< 16U)\
  253. | ((150U - 1U)<< 8U)
  254. #define SYS_PLLCTL1_CONFIGVALUE_2 ( (SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U)
  255. #define SYS_PLLCTL2_CONFIGVALUE 0x00000000U\
  256. | (255U << 22U)\
  257. | (7U << 12U)\
  258. | ((2U - 1U)<< 9U)\
  259. | 61U
  260. #define SYS_UERFLAG_CONFIGVALUE 0U
  261. #define SYS_LPOMONCTL_CONFIGVALUE_1 (1U << 24U) | LPO_TRIM_VALUE
  262. #define SYS_LPOMONCTL_CONFIGVALUE_2 (1U << 24U) | (16U << 8U) | 8U
  263. #define SYS_CLKTEST_CONFIGVALUE 0x000A0000U
  264. #define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U
  265. #define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U
  266. #define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU
  267. #define SYS_RAMGCR_CONFIGVALUE 0x00050000U
  268. #define SYS_BMMCR1_CONFIGVALUE 0xAU
  269. #define SYS_MMUGCR_CONFIGVALUE 0U
  270. #define SYS_CLKCNTL_CONFIGVALUE (1U << 8U) \
  271. | (1U << 16U) \
  272. | (1U << 24U)
  273. #define SYS_ECPCNTL_CONFIGVALUE (0U << 24U)\
  274. | (0U << 23U)\
  275. | ((8U - 1U) & 0xFFFFU)
  276. #define SYS_DEVCR1_CONFIGVALUE 0xAU
  277. #define SYS_SYSECR_CONFIGVALUE 0x00004000U
  278. #define SYS2_PLLCTL3_CONFIGVALUE_1 ((2U - 1U) << 29U)\
  279. | ((0x1FU)<< 24U) \
  280. | ((6U - 1U)<< 16U) \
  281. | ((150U - 1U) << 8U)
  282. #define SYS2_PLLCTL3_CONFIGVALUE_2 ((SYS2_PLLCTL3_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U)
  283. #define SYS2_STCCLKDIV_CONFIGVALUE 0U
  284. #define SYS2_CLK2CNTL_CONFIGVALUE (1U) \
  285. | (1U << 8U)
  286. #define SYS2_VCLKACON1_CONFIGVALUE (1U << 24U) \
  287. | (1U << 20U) \
  288. | (SYS_VCLK << 16U)\
  289. | (1U << 8U)\
  290. | (1U << 4U) \
  291. | SYS_VCLK
  292. #define SYS2_CLKSLIP_CONFIGVALUE 0x5U
  293. #define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U
  294. void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type);
  295. /* USER CODE BEGIN (1) */
  296. /* USER CODE END */
  297. /* FlashW General Definitions */
  298. /** @enum flashWPowerModes
  299. * @brief Alias names for flash bank power modes
  300. *
  301. * This enumeration is used to provide alias names for the flash bank power modes:
  302. * - sleep
  303. * - standby
  304. * - active
  305. */
  306. enum flashWPowerModes
  307. {
  308. SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
  309. SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
  310. SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
  311. };
  312. /* USER CODE BEGIN (2) */
  313. /* USER CODE END */
  314. #define FSM_WR_ENA_HL (*(volatile uint32 *)0xFFF87288U)
  315. #define EEPROM_CONFIG_HL (*(volatile uint32 *)0xFFF872B8U)
  316. /* Configuration registers */
  317. typedef struct tcmflash_config_reg
  318. {
  319. uint32 CONFIG_FRDCNTL;
  320. uint32 CONFIG_FEDACCTRL1;
  321. uint32 CONFIG_FEDACCTRL2;
  322. uint32 CONFIG_FEDACSDIS;
  323. uint32 CONFIG_FBPROT;
  324. uint32 CONFIG_FBSE;
  325. uint32 CONFIG_FBAC;
  326. uint32 CONFIG_FBFALLBACK;
  327. uint32 CONFIG_FPAC1;
  328. uint32 CONFIG_FPAC2;
  329. uint32 CONFIG_FMAC;
  330. uint32 CONFIG_FLOCK;
  331. uint32 CONFIG_FDIAGCTRL;
  332. uint32 CONFIG_FEDACSDIS2;
  333. } tcmflash_config_reg_t;
  334. /* Configuration registers initial value */
  335. #define TCMFLASH_FRDCNTL_CONFIGVALUE 0x00000000U | (3U << 8U) | (1U << 4U) | 1U
  336. #define TCMFLASH_FEDACCTRL1_CONFIGVALUE 0x000A0005U
  337. #define TCMFLASH_FEDACCTRL2_CONFIGVALUE 0U
  338. #define TCMFLASH_FEDACSDIS_CONFIGVALUE 0U
  339. #define TCMFLASH_FBPROT_CONFIGVALUE 0U
  340. #define TCMFLASH_FBSE_CONFIGVALUE 0U
  341. #define TCMFLASH_FBAC_CONFIGVALUE 0xFU
  342. #define TCMFLASH_FBFALLBACK_CONFIGVALUE 0x00000000U\
  343. | (SYS_ACTIVE << 14U) \
  344. | (SYS_SLEEP << 12U) \
  345. | (SYS_SLEEP << 10U) \
  346. | (SYS_SLEEP << 8U) \
  347. | (SYS_SLEEP << 6U) \
  348. | (SYS_SLEEP << 4U) \
  349. | (SYS_ACTIVE << 2U) \
  350. | SYS_ACTIVE \
  351. #define TCMFLASH_FPAC1_CONFIGVALUE 0x00C80001U
  352. #define TCMFLASH_FPAC2_CONFIGVALUE 0U
  353. #define TCMFLASH_FMAC_CONFIGVALUE 0U
  354. #define TCMFLASH_FLOCK_CONFIGVALUE 0x55AAU
  355. #define TCMFLASH_FDIAGCTRL_CONFIGVALUE 0x000A0000U
  356. #define TCMFLASH_FEDACSDIS2_CONFIGVALUE 0U
  357. void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type);
  358. /* USER CODE BEGIN (3) */
  359. /* USER CODE END */
  360. /* System Interface Functions */
  361. void setupPLL(void);
  362. void trimLPO(void);
  363. void setupFlash(void);
  364. void periphInit(void);
  365. void mapClocks(void);
  366. void systemInit(void);
  367. void systemPowerDown(uint32 mode);
  368. /*Configuration registers
  369. * index 0: Even RAM
  370. * index 1: Odd RAM
  371. */
  372. typedef struct sram_config_reg
  373. {
  374. uint32 CONFIG_RAMCTRL[2U];
  375. uint32 CONFIG_RAMTHRESHOLD[2U];
  376. uint32 CONFIG_RAMINTCTRL[2U];
  377. uint32 CONFIG_RAMTEST[2U];
  378. uint32 CONFIG_RAMADDRDECVECT[2U];
  379. } sram_config_reg_t;
  380. /* Configuration registers initial value */
  381. #define SRAM_RAMCTRL_CONFIGVALUE 0x0005000AU
  382. #define SRAM_RAMTHRESHOLD_CONFIGVALUE 1U
  383. #define SRAM_RAMINTCTRL_CONFIGVALUE 1U
  384. #define SRAM_RAMTEST_CONFIGVALUE 0x5U
  385. #define SRAM_RAMADDRDECVECT_CONFIGVALUE 0U
  386. void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type);
  387. #endif