stm32l4xx_ll_spi.c 12 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_ll_spi.c
  4. * @author MCD Application Team
  5. * @version V1.7.2
  6. * @date 16-June-2017
  7. * @brief SPI LL module driver.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12. *
  13. * Redistribution and use in source and binary forms, with or without modification,
  14. * are permitted provided that the following conditions are met:
  15. * 1. Redistributions of source code must retain the above copyright notice,
  16. * this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright notice,
  18. * this list of conditions and the following disclaimer in the documentation
  19. * and/or other materials provided with the distribution.
  20. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  21. * may be used to endorse or promote products derived from this software
  22. * without specific prior written permission.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. ******************************************************************************
  36. */
  37. #if defined(USE_FULL_LL_DRIVER)
  38. /* Includes ------------------------------------------------------------------*/
  39. #include "stm32l4xx_ll_spi.h"
  40. #include "stm32l4xx_ll_bus.h"
  41. #ifdef USE_FULL_ASSERT
  42. #include "stm32_assert.h"
  43. #else
  44. #define assert_param(expr) ((void)0U)
  45. #endif
  46. /** @addtogroup STM32L4xx_LL_Driver
  47. * @{
  48. */
  49. #if defined (SPI1) || defined (SPI2) || defined (SPI3)
  50. /** @addtogroup SPI_LL
  51. * @{
  52. */
  53. /* Private types -------------------------------------------------------------*/
  54. /* Private variables ---------------------------------------------------------*/
  55. /* Private constants ---------------------------------------------------------*/
  56. /** @defgroup SPI_LL_Private_Constants SPI Private Constants
  57. * @{
  58. */
  59. /* SPI registers Masks */
  60. #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
  61. SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
  62. SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
  63. SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
  64. SPI_CR1_BIDIMODE)
  65. /**
  66. * @}
  67. */
  68. /* Private macros ------------------------------------------------------------*/
  69. /** @defgroup SPI_LL_Private_Macros SPI Private Macros
  70. * @{
  71. */
  72. #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
  73. || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
  74. || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
  75. || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
  76. #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
  77. || ((__VALUE__) == LL_SPI_MODE_SLAVE))
  78. #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
  79. || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
  80. || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
  81. || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
  82. || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
  83. || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
  84. || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
  85. || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
  86. || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
  87. || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
  88. || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
  89. || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
  90. || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
  91. #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
  92. || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
  93. #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
  94. || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
  95. #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
  96. || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
  97. || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
  98. #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
  99. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
  100. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
  101. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
  102. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
  103. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
  104. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
  105. || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
  106. #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
  107. || ((__VALUE__) == LL_SPI_MSB_FIRST))
  108. #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
  109. || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
  110. #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
  111. /**
  112. * @}
  113. */
  114. /* Private function prototypes -----------------------------------------------*/
  115. /* Exported functions --------------------------------------------------------*/
  116. /** @addtogroup SPI_LL_Exported_Functions
  117. * @{
  118. */
  119. /** @addtogroup SPI_LL_EF_Init
  120. * @{
  121. */
  122. /**
  123. * @brief De-initialize the SPI registers to their default reset values.
  124. * @param SPIx SPI Instance
  125. * @retval An ErrorStatus enumeration value:
  126. * - SUCCESS: SPI registers are de-initialized
  127. * - ERROR: SPI registers are not de-initialized
  128. */
  129. ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
  130. {
  131. ErrorStatus status = ERROR;
  132. /* Check the parameters */
  133. assert_param(IS_SPI_ALL_INSTANCE(SPIx));
  134. #if defined(SPI1)
  135. if (SPIx == SPI1)
  136. {
  137. /* Force reset of SPI clock */
  138. LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
  139. /* Release reset of SPI clock */
  140. LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
  141. status = SUCCESS;
  142. }
  143. #endif /* SPI1 */
  144. #if defined(SPI2)
  145. if (SPIx == SPI2)
  146. {
  147. /* Force reset of SPI clock */
  148. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
  149. /* Release reset of SPI clock */
  150. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
  151. status = SUCCESS;
  152. }
  153. #endif /* SPI2 */
  154. #if defined(SPI3)
  155. if (SPIx == SPI3)
  156. {
  157. /* Force reset of SPI clock */
  158. LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
  159. /* Release reset of SPI clock */
  160. LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
  161. status = SUCCESS;
  162. }
  163. #endif /* SPI3 */
  164. return status;
  165. }
  166. /**
  167. * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
  168. * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
  169. * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
  170. * @param SPIx SPI Instance
  171. * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
  172. * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
  173. */
  174. ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
  175. {
  176. ErrorStatus status = ERROR;
  177. /* Check the SPI Instance SPIx*/
  178. assert_param(IS_SPI_ALL_INSTANCE(SPIx));
  179. /* Check the SPI parameters from SPI_InitStruct*/
  180. assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
  181. assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
  182. assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
  183. assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
  184. assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
  185. assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
  186. assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
  187. assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
  188. assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
  189. if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
  190. {
  191. /*---------------------------- SPIx CR1 Configuration ------------------------
  192. * Configure SPIx CR1 with parameters:
  193. * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
  194. * - Master/Slave Mode: SPI_CR1_MSTR bit
  195. * - ClockPolarity: SPI_CR1_CPOL bit
  196. * - ClockPhase: SPI_CR1_CPHA bit
  197. * - NSS management: SPI_CR1_SSM bit
  198. * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
  199. * - BitOrder: SPI_CR1_LSBFIRST bit
  200. * - CRCCalculation: SPI_CR1_CRCEN bit
  201. */
  202. MODIFY_REG(SPIx->CR1,
  203. SPI_CR1_CLEAR_MASK,
  204. SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
  205. SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
  206. SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
  207. SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
  208. /*---------------------------- SPIx CR2 Configuration ------------------------
  209. * Configure SPIx CR2 with parameters:
  210. * - DataWidth: DS[3:0] bits
  211. * - NSS management: SSOE bit
  212. */
  213. MODIFY_REG(SPIx->CR2,
  214. SPI_CR2_DS | SPI_CR2_SSOE,
  215. SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
  216. /*---------------------------- SPIx CRCPR Configuration ----------------------
  217. * Configure SPIx CRCPR with parameters:
  218. * - CRCPoly: CRCPOLY[15:0] bits
  219. */
  220. if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
  221. {
  222. assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
  223. LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
  224. }
  225. status = SUCCESS;
  226. }
  227. return status;
  228. }
  229. /**
  230. * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
  231. * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
  232. * whose fields will be set to default values.
  233. * @retval None
  234. */
  235. void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
  236. {
  237. /* Set SPI_InitStruct fields to default values */
  238. SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
  239. SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
  240. SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
  241. SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
  242. SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
  243. SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
  244. SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
  245. SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
  246. SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
  247. SPI_InitStruct->CRCPoly = 7U;
  248. }
  249. /**
  250. * @}
  251. */
  252. /**
  253. * @}
  254. */
  255. /**
  256. * @}
  257. */
  258. #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
  259. /**
  260. * @}
  261. */
  262. #endif /* USE_FULL_LL_DRIVER */
  263. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/