x1000_intc.h 4.2 KB

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  1. /*
  2. * File : x1000_intc.h
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * Change Logs:
  21. * Date Author Notes
  22. * 2017-02-03 Urey the first version
  23. */
  24. #ifndef _X1000_INTC_H_
  25. #define _X1000_INTC_H_
  26. /*
  27. * INTC (Interrupt Controller)
  28. */
  29. #define INTC_ISR(n) (INTC_BASE + 0x00 + (n) * 0x20)
  30. #define INTC_IMR(n) (INTC_BASE + 0x04 + (n) * 0x20)
  31. #define INTC_IMSR(n) (INTC_BASE + 0x08 + (n) * 0x20)
  32. #define INTC_IMCR(n) (INTC_BASE + 0x0c + (n) * 0x20)
  33. #define INTC_IPR(n) (INTC_BASE + 0x10 + (n) * 0x20)
  34. #define REG_INTC_ISR(n) REG32(INTC_ISR((n)))
  35. #define REG_INTC_IMR(n) REG32(INTC_IMR((n)))
  36. #define REG_INTC_IMSR(n) REG32(INTC_IMSR((n)))
  37. #define REG_INTC_IMCR(n) REG32(INTC_IMCR((n)))
  38. #define REG_INTC_IPR(n) REG32(INTC_IPR((n)))
  39. // interrupt controller interrupts
  40. #define IRQ_DMIC 0
  41. #define IRQ_AIC0 1
  42. #define IRQ_RESERVED2 2
  43. #define IRQ_RESERVED3 3
  44. #define IRQ_RESERVED4 4
  45. #define IRQ_RESERVED5 5
  46. #define IRQ_RESERVED6 6
  47. #define IRQ_SFC 7
  48. #define IRQ_SSI0 8
  49. #define IRQ_RESERVED9 9
  50. #define IRQ_PDMA 10
  51. #define IRQ_PDMAD 11
  52. #define IRQ_RESERVED12 12
  53. #define IRQ_RESERVED13 13
  54. #define IRQ_GPIO3 14
  55. #define IRQ_GPIO2 15
  56. #define IRQ_GPIO1 16
  57. #define IRQ_GPIO0 17
  58. #define IRQ_RESERVED18 18
  59. #define IRQ_RESERVED19 19
  60. #define IRQ_RESERVED20 20
  61. #define IRQ_OTG 21
  62. #define IRQ_RESERVED22 22
  63. #define IRQ_AES 23
  64. #define IRQ_RESERVED24 24
  65. #define IRQ_TCU2 25
  66. #define IRQ_TCU1 26
  67. #define IRQ_TCU0 27
  68. #define IRQ_RESERVED28 28
  69. #define IRQ_RESERVED29 29
  70. #define IRQ_CIM 30
  71. #define IRQ_LCD 31
  72. #define IRQ_RTC 32
  73. #define IRQ_RESERVED33 33
  74. #define IRQ_RESERVED34 34
  75. #define IRQ_RESERVED35 35
  76. #define IRQ_MSC1 36
  77. #define IRQ_MSC0 37
  78. #define IRQ_SCC 38
  79. #define IRQ_RESERVED39 39
  80. #define IRQ_PCM0 40
  81. #define IRQ_RESERVED41 41
  82. #define IRQ_RESERVED42 42
  83. #define IRQ_RESERVED43 43
  84. #define IRQ_HARB2 44
  85. #define IRQ_RESERVED45 45
  86. #define IRQ_HARB0 46
  87. #define IRQ_CPM 47
  88. #define IRQ_RESERVED48 48
  89. #define IRQ_UART2 49
  90. #define IRQ_UART1 50
  91. #define IRQ_UART0 51
  92. #define IRQ_DDR 52
  93. #define IRQ_RESERVED53 53
  94. #define IRQ_EFUSE 54
  95. #define IRQ_MAC 55
  96. #define IRQ_RESERVED56 56
  97. #define IRQ_RESERVED57 57
  98. #define IRQ_I2C2 58
  99. #define IRQ_I2C1 59
  100. #define IRQ_I2C0 60
  101. #define IRQ_PDMAM 61
  102. #define IRQ_JPEG 62
  103. #define IRQ_RESERVED63 63
  104. #define IRQ_INTC_MAX 63
  105. #ifndef __ASSEMBLY__
  106. #define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
  107. #define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
  108. #define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as the Pending Register is Read Only. Should we remove __intc_ack_irq() */
  109. #endif /* !__ASSEMBLY__ */
  110. #endif /* _X1000_INTC_H_ */