drv_i2c.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463
  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2017-08-08 Yang the first version
  9. * 2018-03-24 LaiYiKeTang add hardware iic
  10. * 2019-03-11 JiCheng Adapt RT1020's IO MAP
  11. */
  12. #include <rtthread.h>
  13. #include <rtdevice.h>
  14. #include "board.h"
  15. #include "fsl_gpio.h"
  16. #include "fsl_lpi2c.h"
  17. #include "drv_i2c.h"
  18. //#define DRV_I2C_DEBUG
  19. #ifdef RT_USING_I2C
  20. #define I2C1BUS_NAME "i2c1"
  21. #define I2C2BUS_NAME "i2c2"
  22. #define I2C3BUS_NAME "i2c3"
  23. #define I2C4BUS_NAME "i2c4"
  24. #define LPI2C_CLOCK_SOURCE_DIVIDER 4
  25. /* Get frequency of lpi2c clock */
  26. #define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER))
  27. #ifdef RT_USING_HW_I2C1
  28. static struct rt1021_i2c_bus lpi2c1 =
  29. {
  30. .I2C = LPI2C1,
  31. .device_name = I2C1BUS_NAME,
  32. };
  33. #endif /* RT_USING_HW_I2C1 */
  34. #ifdef RT_USING_HW_I2C2
  35. static struct rt1021_i2c_bus lpi2c2 =
  36. {
  37. .I2C = LPI2C2,
  38. .device_name = I2C2BUS_NAME,
  39. };
  40. #endif /* RT_USING_HW_I2C2 */
  41. #ifdef RT_USING_HW_I2C3
  42. static struct rt1021_i2c_bus lpi2c3 =
  43. {
  44. .I2C = LPI2C3,
  45. .device_name = I2C3BUS_NAME,
  46. };
  47. #endif /* RT_USING_HW_I2C3 */
  48. #ifdef RT_USING_HW_I2C4
  49. static struct rt1021_i2c_bus lpi2c4 =
  50. {
  51. .I2C = LPI2C4,
  52. .device_name = I2C4BUS_NAME,
  53. };
  54. #endif /* RT_USING_HW_I2C4 */
  55. #if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4))
  56. static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
  57. struct rt_i2c_msg msgs[],
  58. rt_uint32_t num);
  59. static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
  60. struct rt_i2c_msg msgs[],
  61. rt_uint32_t num);
  62. static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
  63. rt_uint32_t,
  64. rt_uint32_t);
  65. static const struct rt_i2c_bus_device_ops imxrt_i2c_ops =
  66. {
  67. imxrt_i2c_mst_xfer,
  68. imxrt_i2c_slv_xfer,
  69. imxrt_i2c_bus_control,
  70. };
  71. void imxrt_lpi2c_gpio_init(struct rt1021_i2c_bus *bus)
  72. {
  73. if (bus->I2C == LPI2C1)
  74. {
  75. IOMUXC_SetPinMux(
  76. IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL,
  77. 1U);
  78. IOMUXC_SetPinMux(
  79. IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA,
  80. 1U);
  81. IOMUXC_SetPinConfig(
  82. IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL,
  83. 0xD8B0u);
  84. IOMUXC_SetPinConfig(
  85. IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA,
  86. 0xD8B0u);
  87. }
  88. else if (bus->I2C == LPI2C2)
  89. {
  90. IOMUXC_SetPinMux(
  91. IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL,
  92. 1U);
  93. IOMUXC_SetPinMux(
  94. IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA,
  95. 1U);
  96. IOMUXC_SetPinConfig(
  97. IOMUXC_GPIO_AD_B1_08_LPI2C2_SCL,
  98. 0xD8B0u);
  99. IOMUXC_SetPinConfig(
  100. IOMUXC_GPIO_AD_B1_09_LPI2C2_SDA,
  101. 0xD8B0u);
  102. }
  103. else if (bus->I2C == LPI2C3)
  104. {
  105. IOMUXC_SetPinMux(
  106. IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL,
  107. 1U);
  108. IOMUXC_SetPinMux(
  109. IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA,
  110. 1U);
  111. IOMUXC_SetPinConfig(
  112. IOMUXC_GPIO_AD_B0_08_LPI2C3_SCL,
  113. 0xD8B0u);
  114. IOMUXC_SetPinConfig(
  115. IOMUXC_GPIO_AD_B0_09_LPI2C3_SDA,
  116. 0xD8B0u);
  117. }
  118. else if (bus->I2C == LPI2C4)
  119. {
  120. IOMUXC_SetPinMux(
  121. IOMUXC_GPIO_EMC_11_LPI2C4_SCL,
  122. 1U);
  123. IOMUXC_SetPinMux(
  124. IOMUXC_GPIO_EMC_10_LPI2C4_SDA,
  125. 1U);
  126. IOMUXC_SetPinConfig(
  127. IOMUXC_GPIO_EMC_11_LPI2C4_SCL,
  128. 0xD8B0u);
  129. IOMUXC_SetPinConfig(
  130. IOMUXC_GPIO_EMC_10_LPI2C4_SDA,
  131. 0xD8B0u);
  132. }
  133. else
  134. {
  135. RT_ASSERT(RT_NULL);
  136. }
  137. }
  138. static rt_err_t imxrt_lpi2c_configure(struct rt1021_i2c_bus *bus, lpi2c_master_config_t *cfg)
  139. {
  140. RT_ASSERT(bus != RT_NULL);
  141. RT_ASSERT(cfg != RT_NULL);
  142. imxrt_lpi2c_gpio_init(bus);
  143. bus->parent.ops = &imxrt_i2c_ops;
  144. LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY);
  145. return RT_EOK;
  146. }
  147. status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status)
  148. {
  149. status_t result = kStatus_Success;
  150. /* Check for error. These errors cause a stop to automatically be sent. We must */
  151. /* clear the errors before a new transfer can start. */
  152. status &= 0x3c00;
  153. if (status)
  154. {
  155. /* Select the correct error code. Ordered by severity, with bus issues first. */
  156. if (status & kLPI2C_MasterPinLowTimeoutFlag)
  157. {
  158. result = kStatus_LPI2C_PinLowTimeout;
  159. }
  160. else if (status & kLPI2C_MasterArbitrationLostFlag)
  161. {
  162. result = kStatus_LPI2C_ArbitrationLost;
  163. }
  164. else if (status & kLPI2C_MasterNackDetectFlag)
  165. {
  166. result = kStatus_LPI2C_Nak;
  167. }
  168. else if (status & kLPI2C_MasterFifoErrFlag)
  169. {
  170. result = kStatus_LPI2C_FifoError;
  171. }
  172. else
  173. {
  174. assert(false);
  175. }
  176. /* Clear the flags. */
  177. LPI2C_MasterClearStatusFlags(base, status);
  178. /* Reset fifos. These flags clear automatically. */
  179. base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
  180. }
  181. return result;
  182. }
  183. /*!
  184. * @brief Wait until the tx fifo all empty.
  185. * @param base The LPI2C peripheral base address.
  186. * @retval #kStatus_Success
  187. * @retval #kStatus_LPI2C_PinLowTimeout
  188. * @retval #kStatus_LPI2C_ArbitrationLost
  189. * @retval #kStatus_LPI2C_Nak
  190. * @retval #kStatus_LPI2C_FifoError
  191. */
  192. static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base)
  193. {
  194. uint32_t status;
  195. size_t txCount;
  196. do
  197. {
  198. status_t result;
  199. /* Get the number of words in the tx fifo and compute empty slots. */
  200. LPI2C_MasterGetFifoCounts(base, NULL, &txCount);
  201. /* Check for error flags. */
  202. status = LPI2C_MasterGetStatusFlags(base);
  203. result = LPI2C_MasterCheck(base, status);
  204. if (result)
  205. {
  206. return result;
  207. }
  208. }
  209. while (txCount);
  210. return kStatus_Success;
  211. }
  212. static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
  213. struct rt_i2c_msg msgs[],
  214. rt_uint32_t num)
  215. {
  216. struct rt1021_i2c_bus *rt1021_i2c;
  217. rt_size_t i;
  218. RT_ASSERT(bus != RT_NULL);
  219. rt1021_i2c = (struct rt1021_i2c_bus *) bus;
  220. rt1021_i2c->msg = msgs;
  221. rt1021_i2c->msg_ptr = 0;
  222. rt1021_i2c->msg_cnt = num;
  223. rt1021_i2c->dptr = 0;
  224. for (i = 0; i < num; i++)
  225. {
  226. if (rt1021_i2c->msg[i].flags & RT_I2C_RD)
  227. {
  228. if (LPI2C_MasterStart(rt1021_i2c->I2C, rt1021_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
  229. {
  230. i = 0;
  231. break;
  232. }
  233. if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1021_i2c->I2C) != kStatus_Success)
  234. {
  235. i = 0;
  236. break;
  237. }
  238. if (LPI2C_MasterReceive(rt1021_i2c->I2C, rt1021_i2c->msg[i].buf, rt1021_i2c->msg[i].len) != kStatus_Success)
  239. {
  240. i = 0;
  241. break;
  242. }
  243. if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1021_i2c->I2C) != kStatus_Success)
  244. {
  245. i = 0;
  246. break;
  247. }
  248. }
  249. else
  250. {
  251. if (LPI2C_MasterStart(rt1021_i2c->I2C, rt1021_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
  252. {
  253. i = 0;
  254. break;
  255. }
  256. if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1021_i2c->I2C) != kStatus_Success)
  257. {
  258. i = 0;
  259. break;
  260. }
  261. if (LPI2C_MasterSend(rt1021_i2c->I2C, rt1021_i2c->msg[i].buf, rt1021_i2c->msg[i].len) != kStatus_Success)
  262. {
  263. i = 0;
  264. break;
  265. }
  266. if (LPI2C_MasterWaitForTxFifoAllEmpty(rt1021_i2c->I2C) != kStatus_Success)
  267. {
  268. i = 0;
  269. break;
  270. }
  271. }
  272. }
  273. i2c_dbg("send stop condition\n");
  274. if (LPI2C_MasterStop(rt1021_i2c->I2C) != kStatus_Success)
  275. {
  276. i = 0;
  277. }
  278. rt1021_i2c->msg = RT_NULL;
  279. rt1021_i2c->msg_ptr = 0;
  280. rt1021_i2c->msg_cnt = 0;
  281. rt1021_i2c->dptr = 0;
  282. return i;
  283. }
  284. static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
  285. struct rt_i2c_msg msgs[],
  286. rt_uint32_t num)
  287. {
  288. return 0;
  289. }
  290. static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
  291. rt_uint32_t cmd,
  292. rt_uint32_t arg)
  293. {
  294. return RT_ERROR;
  295. }
  296. #endif
  297. int rt_hw_i2c_init(void)
  298. {
  299. #if (defined(RT_USING_HW_I2C1) || defined(RT_USING_HW_I2C2) || defined(RT_USING_HW_I2C3) || defined(RT_USING_HW_I2C4))
  300. lpi2c_master_config_t masterConfig = {0};
  301. /*Clock setting for LPI2C*/
  302. CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
  303. CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER - 1);
  304. #endif
  305. #if defined(RT_USING_HW_I2C1)
  306. LPI2C_MasterGetDefaultConfig(&masterConfig);
  307. #if defined(HW_I2C1_BADURATE_400kHZ)
  308. masterConfig.baudRate_Hz = 400000U;
  309. #elif defined(HW_I2C1_BADURATE_100kHZ)
  310. masterConfig.baudRate_Hz = 100000U;
  311. #endif
  312. imxrt_lpi2c_configure(&lpi2c1, &masterConfig);
  313. rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name);
  314. #endif
  315. #if defined(RT_USING_HW_I2C2)
  316. LPI2C_MasterGetDefaultConfig(&masterConfig);
  317. #if defined(HW_I2C2_BADURATE_400kHZ)
  318. masterConfig.baudRate_Hz = 400000U;
  319. #elif defined(HW_I2C2_BADURATE_100kHZ)
  320. masterConfig.baudRate_Hz = 100000U;
  321. #endif
  322. imxrt_lpi2c_configure(&lpi2c2, &masterConfig);
  323. rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name);
  324. #endif
  325. #if defined(RT_USING_HW_I2C3)
  326. LPI2C_MasterGetDefaultConfig(&masterConfig);
  327. #if defined(HW_I2C3_BADURATE_400kHZ)
  328. masterConfig.baudRate_Hz = 400000U;
  329. #elif defined(HW_I2C3_BADURATE_100kHZ)
  330. masterConfig.baudRate_Hz = 100000U;
  331. #endif
  332. imxrt_lpi2c_configure(&lpi2c3, &masterConfig);
  333. rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name);
  334. #endif
  335. #if defined(RT_USING_HW_I2C4)
  336. LPI2C_MasterGetDefaultConfig(&masterConfig);
  337. #if defined(HW_I2C4_BADURATE_400kHZ)
  338. masterConfig.baudRate_Hz = 400000U;
  339. #elif defined(HW_I2C4_BADURATE_100kHZ)
  340. masterConfig.baudRate_Hz = 100000U;
  341. #endif
  342. imxrt_lpi2c_configure(&lpi2c4, &masterConfig);
  343. rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name);
  344. #endif
  345. return 0;
  346. }
  347. INIT_DEVICE_EXPORT(rt_hw_i2c_init);
  348. #if defined(RT_USING_FINSH) && defined(DRV_I2C_DEBUG)
  349. #include <finsh.h>
  350. static rt_device_t _i2c_find(const char *name)
  351. {
  352. rt_device_t dev;
  353. dev = rt_device_find(name);
  354. if (!dev)
  355. {
  356. rt_kprintf("search device failed: %s\n", name);
  357. return RT_NULL;
  358. }
  359. if (rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) != RT_EOK)
  360. {
  361. rt_kprintf("open device failed: %s\n", name);
  362. return RT_NULL;
  363. }
  364. rt_kprintf("open i2c bus: %s\n", name);
  365. return dev;
  366. }
  367. static void _search_i2c_device(rt_device_t dev, uint8_t cmd)
  368. {
  369. int count = 0;
  370. struct rt_i2c_msg msgs[2];
  371. uint8_t buf = 0;
  372. msgs[0].flags = RT_I2C_WR;
  373. msgs[0].buf = &cmd;
  374. msgs[0].len = sizeof(cmd);
  375. msgs[1].flags = RT_I2C_RD;
  376. msgs[1].buf = &buf;
  377. msgs[1].len = 1;
  378. for (int i = 0; i <= 0x7f; i++)
  379. {
  380. int len;
  381. msgs[0].addr = i;
  382. msgs[1].addr = i;
  383. len = rt_i2c_transfer((struct rt_i2c_bus_device *)dev, msgs, 2);
  384. if (len == 2)
  385. {
  386. count++;
  387. rt_kprintf("add:%02X transfer success, id: %02X\n", i, buf);
  388. }
  389. }
  390. rt_kprintf("i2c device: %d\n", count);
  391. }
  392. static int i2c_test(const char *name, uint8_t cmd)
  393. {
  394. rt_device_t dev = _i2c_find(name);
  395. if (dev == RT_NULL)
  396. {
  397. rt_kprintf("search i2c device faild\n");
  398. return -1;
  399. }
  400. _search_i2c_device(dev, cmd);
  401. rt_device_close(dev);
  402. return 0;
  403. }
  404. FINSH_FUNCTION_EXPORT(i2c_test, e.g: i2c_test("i2c1", 0xA3));
  405. #endif
  406. #endif /* RT_USING_I2C */