drv_uart.c 13 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2017-10-10 Tanek the first version
  9. * 2018-03-17 laiyiketang Add other uart.
  10. * 2019-03-11 JiCheng Adapt RT1021's IO MAP
  11. */
  12. #include <rtthread.h>
  13. #include "drv_uart.h"
  14. #include "fsl_common.h"
  15. #include "fsl_lpuart.h"
  16. #include "fsl_iomuxc.h"
  17. #ifdef RT_USING_SERIAL
  18. #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
  19. #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
  20. #endif
  21. #if !defined(RT_USING_UART1) && !defined(RT_USING_UART2) && \
  22. !defined(RT_USING_UART3) && !defined(RT_USING_UART4) && \
  23. !defined(RT_USING_UART5) && !defined(RT_USING_UART6) && \
  24. !defined(RT_USING_UART7) && !defined(RT_USING_UART8)
  25. #error "Please define at least one UARTx"
  26. #endif
  27. #include <rtdevice.h>
  28. /* imxrt uart driver */
  29. struct imxrt_uart
  30. {
  31. LPUART_Type *uart_base;
  32. IRQn_Type irqn;
  33. struct rt_serial_device *serial;
  34. char *device_name;
  35. };
  36. static void uart_isr(struct rt_serial_device *serial);
  37. #if defined(RT_USING_UART1)
  38. struct rt_serial_device serial1;
  39. void LPUART1_IRQHandler(void)
  40. {
  41. uart_isr(&serial1);
  42. }
  43. #endif /* RT_USING_UART1 */
  44. #if defined(RT_USING_UART2)
  45. struct rt_serial_device serial2;
  46. void LPUART2_IRQHandler(void)
  47. {
  48. uart_isr(&serial2);
  49. }
  50. #endif /* RT_USING_UART2 */
  51. #if defined(RT_USING_UART3)
  52. struct rt_serial_device serial3;
  53. void LPUART3_IRQHandler(void)
  54. {
  55. uart_isr(&serial3);
  56. }
  57. #endif /* RT_USING_UART3 */
  58. #if defined(RT_USING_UART4)
  59. struct rt_serial_device serial4;
  60. void LPUART4_IRQHandler(void)
  61. {
  62. uart_isr(&serial4);
  63. }
  64. #endif /* RT_USING_UART4 */
  65. #if defined(RT_USING_UART5)
  66. struct rt_serial_device serial5;
  67. void LPUART5_IRQHandler(void)
  68. {
  69. uart_isr(&serial5);
  70. }
  71. #endif /* RT_USING_UART5 */
  72. #if defined(RT_USING_UART6)
  73. struct rt_serial_device serial6;
  74. void LPUART6_IRQHandler(void)
  75. {
  76. uart_isr(&serial6);
  77. }
  78. #endif /* RT_USING_UART6 */
  79. #if defined(RT_USING_UART7)
  80. struct rt_serial_device serial7;
  81. void LPUART7_IRQHandler(void)
  82. {
  83. uart_isr(&serial7);
  84. }
  85. #endif /* RT_USING_UART7 */
  86. #if defined(RT_USING_UART8)
  87. struct rt_serial_device serial8;
  88. void LPUART8_IRQHandler(void)
  89. {
  90. uart_isr(&serial8);
  91. }
  92. #endif /* RT_USING_UART8 */
  93. static const struct imxrt_uart uarts[] =
  94. {
  95. #ifdef RT_USING_UART1
  96. {
  97. LPUART1,
  98. LPUART1_IRQn,
  99. &serial1,
  100. "uart1",
  101. },
  102. #endif
  103. #ifdef RT_USING_UART2
  104. {
  105. LPUART2,
  106. LPUART2_IRQn,
  107. &serial2,
  108. "uart2",
  109. },
  110. #endif
  111. #ifdef RT_USING_UART3
  112. {
  113. LPUART3,
  114. LPUART3_IRQn,
  115. &serial3,
  116. "uart3",
  117. },
  118. #endif
  119. #ifdef RT_USING_UART4
  120. {
  121. LPUART4,
  122. LPUART4_IRQn,
  123. &serial4,
  124. "uart4",
  125. },
  126. #endif
  127. #ifdef RT_USING_UART5
  128. {
  129. LPUART5,
  130. LPUART5_IRQn,
  131. &serial5,
  132. "uart5",
  133. },
  134. #endif
  135. #ifdef RT_USING_UART6
  136. {
  137. LPUART6,
  138. LPUART6_IRQn,
  139. &serial6,
  140. "uart6",
  141. },
  142. #endif
  143. #ifdef RT_USING_UART7
  144. {
  145. LPUART7,
  146. LPUART7_IRQn,
  147. &serial7,
  148. "uart7",
  149. },
  150. #endif
  151. #ifdef RT_USING_UART8
  152. {
  153. LPUART8,
  154. LPUART8_IRQn,
  155. &serial8,
  156. "uart8",
  157. },
  158. #endif
  159. };
  160. /* Get debug console frequency. */
  161. uint32_t GetUartSrcFreq(void)
  162. {
  163. uint32_t freq;
  164. /* To make it simple, we assume default PLL and divider settings, and the only variable
  165. from application is use PLL3 source or OSC source */
  166. if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
  167. {
  168. freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
  169. }
  170. else
  171. {
  172. freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
  173. }
  174. return freq;
  175. }
  176. /**
  177. * @brief UART MSP Initialization
  178. * This function configures the hardware resources used in this example:
  179. * - Peripheral's clock enable
  180. * - Peripheral's GPIO Configuration
  181. * - NVIC configuration for UART interrupt request enable
  182. * @param huart: UART handle pointer
  183. * @retval None
  184. */
  185. void imxrt_uart_gpio_init(struct imxrt_uart *uart)
  186. {
  187. if (uart->uart_base != RT_NULL)
  188. {
  189. #ifdef RT_USING_UART1
  190. IOMUXC_SetPinMux(
  191. IOMUXC_GPIO_AD_B0_06_LPUART1_TX, /* GPIO_AD_B0_06 is configured as LPUART1_TX */
  192. 0U); /* Software Input On Field: Input Path is determined by functionality */
  193. IOMUXC_SetPinMux(
  194. IOMUXC_GPIO_AD_B0_07_LPUART1_RX, /* GPIO_AD_B0_07 is configured as LPUART1_RX */
  195. 0U); /* Software Input On Field: Input Path is determined by functionality */
  196. IOMUXC_SetPinConfig(
  197. IOMUXC_GPIO_AD_B0_06_LPUART1_TX, /* GPIO_AD_B0_06 PAD functional properties : */
  198. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  199. Drive Strength Field: R0/6
  200. Speed Field: medium(100MHz)
  201. Open Drain Enable Field: Open Drain Disabled
  202. Pull / Keep Enable Field: Pull/Keeper Enabled
  203. Pull / Keep Select Field: Keeper
  204. Pull Up / Down Config. Field: 100K Ohm Pull Down
  205. Hyst. Enable Field: Hysteresis Disabled */
  206. IOMUXC_SetPinConfig(
  207. IOMUXC_GPIO_AD_B0_07_LPUART1_RX, /* GPIO_AD_B0_07 PAD functional properties : */
  208. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  209. Drive Strength Field: R0/6
  210. Speed Field: medium(100MHz)
  211. Open Drain Enable Field: Open Drain Disabled
  212. Pull / Keep Enable Field: Pull/Keeper Enabled
  213. Pull / Keep Select Field: Keeper
  214. Pull Up / Down Config. Field: 100K Ohm Pull Down
  215. Hyst. Enable Field: Hysteresis Disabled */
  216. #endif
  217. #ifdef RT_USING_UART2
  218. IOMUXC_SetPinMux(
  219. IOMUXC_GPIO_AD_B1_08_LPUART2_TX,
  220. 0U);
  221. IOMUXC_SetPinMux(
  222. IOMUXC_GPIO_AD_B1_09_LPUART2_RX,
  223. 0U);
  224. IOMUXC_SetPinConfig(
  225. IOMUXC_GPIO_AD_B1_08_LPUART2_TX,
  226. 0x10B0u);
  227. IOMUXC_SetPinConfig(
  228. IOMUXC_GPIO_AD_B1_09_LPUART2_RX,
  229. 0x10B0u);
  230. #endif
  231. #ifdef RT_USING_UART3
  232. IOMUXC_SetPinMux(
  233. IOMUXC_GPIO_AD_B0_14_LPUART3_TX,
  234. 0U);
  235. IOMUXC_SetPinMux(
  236. IOMUXC_GPIO_AD_B0_15_LPUART3_RX,
  237. 0U);
  238. IOMUXC_SetPinConfig(
  239. IOMUXC_GPIO_AD_B0_14_LPUART3_TX,
  240. 0x10B0u);
  241. IOMUXC_SetPinConfig(
  242. IOMUXC_GPIO_AD_B0_15_LPUART3_RX,
  243. 0x10B0u);
  244. #endif
  245. #ifdef RT_USING_UART4
  246. IOMUXC_SetPinMux(
  247. IOMUXC_GPIO_AD_B1_10_LPUART4_TX,
  248. 0U);
  249. IOMUXC_SetPinMux(
  250. IOMUXC_GPIO_AD_B1_11_LPUART4_RX,
  251. 0U);
  252. IOMUXC_SetPinConfig(
  253. IOMUXC_GPIO_AD_B1_10_LPUART4_TX,
  254. 0x10B0u);
  255. IOMUXC_SetPinConfig(
  256. IOMUXC_GPIO_AD_B1_11_LPUART4_RX,
  257. 0x10B0u);
  258. #endif
  259. #ifdef RT_USING_UART5
  260. IOMUXC_SetPinMux(
  261. IOMUXC_GPIO_AD_B0_10_LPUART5_TX,
  262. 0U);
  263. IOMUXC_SetPinMux(
  264. IOMUXC_GPIO_AD_B0_11_LPUART5_RX,
  265. 0U);
  266. IOMUXC_SetPinConfig(
  267. IOMUXC_GPIO_AD_B0_10_LPUART5_TX,
  268. 0x10B0u);
  269. IOMUXC_SetPinConfig(
  270. IOMUXC_GPIO_AD_B0_11_LPUART5_RX,
  271. 0x10B0u);
  272. #endif
  273. #ifdef RT_USING_UART6
  274. IOMUXC_SetPinMux(
  275. IOMUXC_GPIO_SD_B1_00_LPUART6_TX,
  276. 0U);
  277. IOMUXC_SetPinMux(
  278. IOMUXC_GPIO_SD_B1_01_LPUART6_RX,
  279. 0U);
  280. IOMUXC_SetPinConfig(
  281. IOMUXC_GPIO_SD_B1_00_LPUART6_TX,
  282. 0x10B0u);
  283. IOMUXC_SetPinConfig(
  284. IOMUXC_GPIO_SD_B1_01_LPUART6_RX,
  285. 0x10B0u);
  286. #endif
  287. #ifdef RT_USING_UART7
  288. IOMUXC_SetPinMux(
  289. IOMUXC_GPIO_EMC_34_LPUART7_TX,
  290. 0U);
  291. IOMUXC_SetPinMux(
  292. IOMUXC_GPIO_EMC_35_LPUART7_RX,
  293. 0U);
  294. IOMUXC_SetPinConfig(
  295. IOMUXC_GPIO_EMC_34_LPUART7_TX,
  296. 0x10B0u);
  297. IOMUXC_SetPinConfig(
  298. IOMUXC_GPIO_EMC_35_LPUART7_RX,
  299. 0x10B0u);
  300. #endif
  301. #ifdef RT_USING_UART8
  302. IOMUXC_SetPinMux(
  303. IOMUXC_GPIO_SD_B1_02_LPUART8_TX,
  304. 0U);
  305. IOMUXC_SetPinMux(
  306. IOMUXC_GPIO_SD_B1_03_LPUART8_RX,
  307. 0U);
  308. IOMUXC_SetPinConfig(
  309. IOMUXC_GPIO_SD_B1_02_LPUART8_TX,
  310. 0x10B0u);
  311. IOMUXC_SetPinConfig(
  312. IOMUXC_GPIO_SD_B1_03_LPUART8_RX,
  313. 0x10B0u);
  314. #endif
  315. }
  316. else
  317. {
  318. RT_ASSERT(RT_NULL);
  319. }
  320. }
  321. static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  322. {
  323. struct imxrt_uart *uart;
  324. lpuart_config_t config;
  325. RT_ASSERT(serial != RT_NULL);
  326. RT_ASSERT(cfg != RT_NULL);
  327. uart = (struct imxrt_uart *)serial->parent.user_data;
  328. imxrt_uart_gpio_init(uart);
  329. LPUART_GetDefaultConfig(&config);
  330. config.baudRate_Bps = cfg->baud_rate;
  331. switch (cfg->data_bits)
  332. {
  333. case DATA_BITS_7:
  334. config.dataBitsCount = kLPUART_SevenDataBits;
  335. break;
  336. default:
  337. config.dataBitsCount = kLPUART_EightDataBits;
  338. break;
  339. }
  340. switch (cfg->stop_bits)
  341. {
  342. case STOP_BITS_2:
  343. config.stopBitCount = kLPUART_TwoStopBit;
  344. break;
  345. default:
  346. config.stopBitCount = kLPUART_OneStopBit;
  347. break;
  348. }
  349. switch (cfg->parity)
  350. {
  351. case PARITY_ODD:
  352. config.parityMode = kLPUART_ParityOdd;
  353. break;
  354. case PARITY_EVEN:
  355. config.parityMode = kLPUART_ParityEven;
  356. break;
  357. default:
  358. config.parityMode = kLPUART_ParityDisabled;
  359. break;
  360. }
  361. config.enableTx = true;
  362. config.enableRx = true;
  363. LPUART_Init(uart->uart_base, &config, GetUartSrcFreq());
  364. LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
  365. return RT_EOK;
  366. }
  367. static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *arg)
  368. {
  369. struct imxrt_uart *uart;
  370. RT_ASSERT(serial != RT_NULL);
  371. uart = (struct imxrt_uart *)serial->parent.user_data;
  372. switch (cmd)
  373. {
  374. case RT_DEVICE_CTRL_CLR_INT:
  375. /* disable rx irq */
  376. DisableIRQ(uart->irqn);
  377. break;
  378. case RT_DEVICE_CTRL_SET_INT:
  379. /* enable rx irq */
  380. EnableIRQ(uart->irqn);
  381. break;
  382. }
  383. return RT_EOK;
  384. }
  385. static int imxrt_putc(struct rt_serial_device *serial, char ch)
  386. {
  387. struct imxrt_uart *uart;
  388. RT_ASSERT(serial != RT_NULL);
  389. uart = (struct imxrt_uart *)serial->parent.user_data;
  390. LPUART_WriteByte(uart->uart_base, ch);
  391. while (!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
  392. return 1;
  393. }
  394. static int imxrt_getc(struct rt_serial_device *serial)
  395. {
  396. int ch;
  397. struct imxrt_uart *uart;
  398. RT_ASSERT(serial != RT_NULL);
  399. uart = (struct imxrt_uart *)serial->parent.user_data;
  400. ch = -1;
  401. if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
  402. ch = LPUART_ReadByte(uart->uart_base);
  403. return ch;
  404. }
  405. /**
  406. * Uart common interrupt process. This need add to uart ISR.
  407. *
  408. * @param serial serial device
  409. */
  410. static void uart_isr(struct rt_serial_device *serial)
  411. {
  412. struct imxrt_uart *uart;
  413. LPUART_Type *base;
  414. RT_ASSERT(serial != RT_NULL);
  415. uart = (struct imxrt_uart *) serial->parent.user_data;
  416. RT_ASSERT(uart != RT_NULL);
  417. base = uart->uart_base;
  418. RT_ASSERT(base != RT_NULL);
  419. /* enter interrupt */
  420. rt_interrupt_enter();
  421. /* UART in mode Receiver -------------------------------------------------*/
  422. if (LPUART_GetStatusFlags(base) & kLPUART_RxDataRegFullFlag)
  423. {
  424. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  425. }
  426. /* If RX overrun. */
  427. if (LPUART_STAT_OR_MASK & base->STAT)
  428. {
  429. /* Clear overrun flag, otherwise the RX does not work. */
  430. base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
  431. }
  432. /* leave interrupt */
  433. rt_interrupt_leave();
  434. }
  435. static const struct rt_uart_ops imxrt_uart_ops =
  436. {
  437. imxrt_configure,
  438. imxrt_control,
  439. imxrt_putc,
  440. imxrt_getc,
  441. };
  442. int imxrt_hw_uart_init(void)
  443. {
  444. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  445. int i;
  446. /* Configure UART divider to default */
  447. CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
  448. CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
  449. for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
  450. {
  451. uarts[i].serial->ops = &imxrt_uart_ops;
  452. uarts[i].serial->config = config;
  453. /* register UART device */
  454. rt_hw_serial_register(uarts[i].serial,
  455. uarts[i].device_name,
  456. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  457. (void *)&uarts[i]);
  458. }
  459. return 0;
  460. }
  461. INIT_BOARD_EXPORT(imxrt_hw_uart_init);
  462. #endif /*RT_USING_SERIAL */