display_controller.c 6.6 KB

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  1. /*
  2. * File : display_controller.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2011-08-09 lgnq first version for LS1B DC
  13. */
  14. #include <rtthread.h>
  15. #include "display_controller.h"
  16. struct vga_struct vga_mode[] =
  17. {
  18. {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
  19. {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
  20. {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
  21. {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
  22. {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
  23. {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
  24. {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
  25. {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
  26. {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
  27. {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
  28. {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
  29. {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
  30. {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
  31. {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
  32. {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
  33. {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
  34. {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
  35. {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
  36. };
  37. ALIGN(16)
  38. volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
  39. static struct rt_device_graphic_info _dc_info;
  40. #define abs(x) ((x<0)?(-x):x)
  41. #define min(a,b) ((a<b)?a:b)
  42. int caclulate_freq(long long XIN, long long PCLK)
  43. {
  44. int i;
  45. long long clk, clk1;
  46. int start, end;
  47. int mi;
  48. int pll,ctrl,div,div1,frac;
  49. pll = PLL_FREQ;
  50. ctrl = PLL_DIV_PARAM;
  51. rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
  52. // rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
  53. start = -1;
  54. end = 1;
  55. for (i=start; i<=end; i++)
  56. {
  57. clk = (12+i+(pll&0x3f))*33333333/2;
  58. div = clk/(long)PCLK/1000;
  59. clk1 = (12+i+1+(pll&0x3f))*33333333/2;
  60. div1 = clk1/(long)PCLK/1000;
  61. if (div!=div1)
  62. break;
  63. }
  64. if (div!=div1)
  65. {
  66. frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
  67. pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
  68. ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
  69. }
  70. else
  71. {
  72. clk = (12+start+(pll&0x3f))*33333333/2;
  73. clk1 = (12+end+(pll&0x3f))*33333333/2;
  74. if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
  75. {
  76. pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
  77. ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
  78. }
  79. else
  80. {
  81. pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
  82. ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
  83. }
  84. }
  85. rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
  86. ctrl |= 0x2a00;
  87. PLL_DIV_PARAM = ctrl;
  88. PLL_FREQ = pll;
  89. rt_thread_delay(10);
  90. // initserial(0);
  91. // _probe_frequencies();
  92. // rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
  93. return 0;
  94. }
  95. static rt_err_t rt_dc_init(rt_device_t dev)
  96. {
  97. int i, out, mode=-1;
  98. int val;
  99. for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
  100. {
  101. if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
  102. {
  103. mode=i;
  104. #ifdef LS1FSOC
  105. // out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
  106. // rt_kprintf("out=%x\n",out);
  107. /*inner gpu dc logic fifo pll ctrl,must large then outclk*/
  108. // *(volatile int *)0xbfd00414 = out+1;
  109. /*output pix1 clock pll ctrl*/
  110. // *(volatile int *)0xbfd00410 = out;
  111. /*output pix2 clock pll ctrl */
  112. // *(volatile int *)0xbfd00424 = out;
  113. #else
  114. caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
  115. #endif
  116. break;
  117. }
  118. }
  119. if (mode<0)
  120. {
  121. rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
  122. return;
  123. }
  124. DC_FB_CONFIG = 0x0;
  125. DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
  126. DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
  127. DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
  128. DC_DITHER_CONFIG = 0x0;
  129. DC_DITHER_TABLE_LOW = 0x0;
  130. DC_DITHER_TABLE_HIGH = 0x0;
  131. DC_PANEL_CONFIG = 0x80001311;
  132. DC_PANEL_TIMING = 0x0;
  133. DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
  134. DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
  135. DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
  136. DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
  137. #if defined(CONFIG_VIDEO_32BPP)
  138. DC_FB_CONFIG = 0x00100104;
  139. DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
  140. #elif defined(CONFIG_VIDEO_16BPP)
  141. DC_FB_CONFIG = 0x00100103;
  142. DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
  143. #elif defined(CONFIG_VIDEO_15BPP)
  144. DC_FB_CONFIG = 0x00100102;
  145. DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
  146. #elif defined(CONFIG_VIDEO_12BPP)
  147. DC_FB_CONFIG = 0x00100101;
  148. DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
  149. #else //640x480-32Bits
  150. DC_FB_CONFIG = 0x00100104;
  151. DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
  152. #endif //32Bits
  153. #ifdef LS1GSOC
  154. /*fix ls1g dc
  155. *first switch to tile mode
  156. *change origin register to 0
  157. *goback nomal mode
  158. */
  159. {
  160. val = DC_FB_CONFIG;
  161. DC_FB_CONFIG = val | 0x10;
  162. DC_FB_BUFFER_ORIGIN = 0;
  163. DC_FB_BUFFER_ORIGIN;
  164. rt_thread_delay(10);
  165. DC_FB_CONFIG;
  166. DC_FB_CONFIG = val;
  167. }
  168. #endif
  169. return RT_EOK;
  170. }
  171. static rt_err_t rt_dc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
  172. {
  173. switch (cmd)
  174. {
  175. case RTGRAPHIC_CTRL_RECT_UPDATE:
  176. break;
  177. case RTGRAPHIC_CTRL_POWERON:
  178. break;
  179. case RTGRAPHIC_CTRL_POWEROFF:
  180. break;
  181. case RTGRAPHIC_CTRL_GET_INFO:
  182. rt_memcpy(args, &_dc_info, sizeof(_dc_info));
  183. break;
  184. case RTGRAPHIC_CTRL_SET_MODE:
  185. break;
  186. }
  187. return RT_EOK;
  188. }
  189. void rt_hw_dc_init(void)
  190. {
  191. rt_device_t dc = rt_malloc(sizeof(struct rt_device));
  192. if (dc == RT_NULL)
  193. {
  194. rt_kprintf("dc == RT_NULL\n");
  195. return; /* no memory yet */
  196. }
  197. _dc_info.bits_per_pixel = 16;
  198. _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
  199. _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
  200. _dc_info.width = FB_XSIZE;
  201. _dc_info.height = FB_YSIZE;
  202. /* init device structure */
  203. dc->type = RT_Device_Class_Graphic;
  204. dc->init = rt_dc_init;
  205. dc->open = RT_NULL;
  206. dc->close = RT_NULL;
  207. dc->control = rt_dc_control;
  208. dc->user_data = (void*)&_dc_info;
  209. /* register Display Controller device to RT-Thread */
  210. rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
  211. }