drv_common.h 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374
  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2020-12-12 Wayne First version
  10. *
  11. ******************************************************************************/
  12. #ifndef __DRV_COMMON_H__
  13. #define __DRV_COMMON_H__
  14. #include <rtthread.h>
  15. #include "NuMicro.h"
  16. #include "interrupt.h"
  17. #if !defined(USE_MA35D1_SUBM)
  18. #include "gic.h"
  19. #include "mmu.h"
  20. #if defined(USE_MA35D1_AARCH32)
  21. #include "cp15.h"
  22. #endif
  23. #include "gtimer.h"
  24. #define __REG32(x) (*((volatile unsigned int*)((rt_ubase_t)x)))
  25. #define GIC_ACK_INTID_MASK 0x000003ff
  26. #define ARM_GIC_NR_IRQS 256
  27. #define MAX_HANDLERS ARM_GIC_NR_IRQS
  28. #define ARM_GIC_MAX_NR 1
  29. #define GIC_IRQ_START 0
  30. #define DDR_LIMIT_SIZE 0xC0000000u
  31. #define UNCACHEABLE 0x40000000u
  32. /* the basic constants needed by gic */
  33. rt_inline rt_uint32_t platform_get_gic_dist_base(void)
  34. {
  35. return GIC_DISTRIBUTOR_BASE;
  36. }
  37. rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
  38. {
  39. return GIC_INTERFACE_BASE;
  40. }
  41. rt_inline rt_uint32_t nu_cpu_dcache_line_size(void)
  42. {
  43. rt_uint32_t ctr = 0;
  44. #if defined(USE_MA35D1_AARCH32)
  45. asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r"(ctr));
  46. #elif defined(USE_MA35D1_AARCH64)
  47. asm volatile("mrs %0, ctr_el0" : "=r"(ctr));
  48. #endif
  49. return 4 << ((ctr >> 16) & 0xF);
  50. }
  51. extern void rt_hw_cpu_dcache_clean(void *addr, int size);
  52. extern void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
  53. extern void rt_hw_cpu_dcache_invalidate(void *addr, int size);
  54. #else
  55. #define UNCACHEABLE 0
  56. #endif
  57. #define REGION_ADDR_SRAM0 0x24000000
  58. #define REGION_ADDR_DDR (0x80020000|UNCACHEABLE)
  59. #define REGION_MAXSIZE_SRAM0 (128*1024)
  60. #define REGION_MAXSIZE_DDR (4*1024*1024-REGION_MAXSIZE_SRAM0)
  61. #define REGION_MAXSIZE_LIMIT (REGION_MAXSIZE_SRAM0+REGION_MAXSIZE_DDR)
  62. #endif /* __DRV_COMMON_H__ */