drv_i2s.c 18 KB

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  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2020-2-7 Wayne Lin First version
  10. *
  11. ******************************************************************************/
  12. #include <rtconfig.h>
  13. #if defined(BSP_USING_I2S)
  14. #include <rtdevice.h>
  15. #include "drv_pdma.h"
  16. #include "drv_i2s.h"
  17. #include "drv_common.h"
  18. /* Private define ---------------------------------------------------------------*/
  19. #define DBG_ENABLE
  20. #define DBG_LEVEL DBG_LOG
  21. #define DBG_SECTION_NAME "i2s"
  22. #define DBG_COLOR
  23. #include <rtdbg.h>
  24. enum
  25. {
  26. I2S_START = -1,
  27. #if defined(BSP_USING_I2S0)
  28. I2S0_IDX,
  29. #endif
  30. #if defined(BSP_USING_I2S1)
  31. I2S1_IDX,
  32. #endif
  33. I2S_CNT
  34. };
  35. /* Private functions ------------------------------------------------------------*/
  36. static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps);
  37. static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps);
  38. static rt_err_t nu_i2s_init(struct rt_audio_device *audio);
  39. static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream);
  40. static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream);
  41. static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
  42. /* Public functions -------------------------------------------------------------*/
  43. rt_err_t nu_i2s_acodec_register(nu_acodec_ops_t);
  44. /* Private variables ------------------------------------------------------------*/
  45. static struct nu_i2s nu_i2s_arr[] =
  46. {
  47. #if defined(BSP_USING_I2S0)
  48. {
  49. .name = "sound0",
  50. .i2s_base = I2S0,
  51. .i2s_rst = I2S0_RST,
  52. .i2s_dais = {
  53. [NU_I2S_DAI_PLAYBACK] = {
  54. .pdma_perp = PDMA_I2S0_TX,
  55. },
  56. [NU_I2S_DAI_CAPTURE] = {
  57. .pdma_perp = PDMA_I2S0_RX,
  58. }
  59. }
  60. },
  61. #endif
  62. #if defined(BSP_USING_I2S1)
  63. {
  64. .name = "sound1",
  65. .i2s_base = I2S1,
  66. .i2s_rst = I2S1_RST,
  67. .i2s_dais = {
  68. [NU_I2S_DAI_PLAYBACK] = {
  69. .pdma_perp = PDMA_I2S1_TX,
  70. },
  71. [NU_I2S_DAI_CAPTURE] = {
  72. .pdma_perp = PDMA_I2S1_RX,
  73. }
  74. }
  75. },
  76. #endif
  77. };
  78. static void nu_pdma_i2s_rx_cb(void *pvUserData, uint32_t u32EventFilter)
  79. {
  80. nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData;
  81. nu_i2s_dai_t psNuI2sDai;
  82. RT_ASSERT(psNuI2s != RT_NULL);
  83. psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE];
  84. if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
  85. {
  86. /* Report uncacheable memory address to upper layer. */
  87. rt_uint8_t *pbuf_old = (rt_uint8_t *)((uint32_t)&psNuI2sDai->fifo[psNuI2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] | UNCACHEABLE) ;
  88. psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
  89. /* Report upper layer. */
  90. rt_audio_rx_done(&psNuI2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE);
  91. }
  92. }
  93. static void nu_pdma_i2s_tx_cb(void *pvUserData, uint32_t u32EventFilter)
  94. {
  95. nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData;
  96. nu_i2s_dai_t psNuI2sDai;
  97. RT_ASSERT(psNuI2s != RT_NULL);
  98. psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
  99. if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
  100. {
  101. rt_audio_tx_complete(&psNuI2s->audio);
  102. psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
  103. }
  104. }
  105. static rt_err_t nu_i2s_pdma_sc_config(nu_i2s_t psNuI2s, E_NU_I2S_DAI dai)
  106. {
  107. rt_err_t result = RT_EOK;
  108. I2S_T *i2s_base;
  109. nu_i2s_dai_t psNuI2sDai;
  110. int i;
  111. uint32_t u32Src, u32Dst;
  112. nu_pdma_cb_handler_t pfm_pdma_cb;
  113. struct nu_pdma_chn_cb sChnCB;
  114. RT_ASSERT(psNuI2s != RT_NULL);
  115. /* Get base address of i2s register */
  116. i2s_base = psNuI2s->i2s_base;
  117. psNuI2sDai = &psNuI2s->i2s_dais[dai];
  118. switch ((int)dai)
  119. {
  120. case NU_I2S_DAI_PLAYBACK:
  121. pfm_pdma_cb = nu_pdma_i2s_tx_cb;
  122. u32Src = (uint32_t)&psNuI2sDai->fifo[0];
  123. u32Dst = (uint32_t)&i2s_base->TXFIFO;
  124. break;
  125. case NU_I2S_DAI_CAPTURE:
  126. pfm_pdma_cb = nu_pdma_i2s_rx_cb;
  127. u32Src = (uint32_t)&i2s_base->RXFIFO;
  128. u32Dst = (uint32_t)&psNuI2sDai->fifo[0];
  129. break;
  130. default:
  131. return -RT_EINVAL;
  132. }
  133. /* Register ISR callback function */
  134. sChnCB.m_eCBType = eCBType_Event;
  135. sChnCB.m_pfnCBHandler = pfm_pdma_cb;
  136. sChnCB.m_pvUserData = (void *)psNuI2s;
  137. nu_pdma_filtering_set(psNuI2sDai->pdma_chanid, NU_PDMA_EVENT_TRANSFER_DONE);
  138. result = nu_pdma_callback_register(psNuI2sDai->pdma_chanid, &sChnCB);
  139. RT_ASSERT(result == RT_EOK);
  140. for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++)
  141. {
  142. /* Setup dma descriptor entry */
  143. result = nu_pdma_desc_setup(psNuI2sDai->pdma_chanid, // Channel ID
  144. psNuI2sDai->pdma_descs[i], // this descriptor
  145. 32, // 32-bits
  146. (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO
  147. (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory
  148. (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4, // Transfer count
  149. psNuI2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER], // Next descriptor
  150. 0); // Interrupt assert when every SG-table done.
  151. RT_ASSERT(result == RT_EOK);
  152. }
  153. /* Assign head descriptor */
  154. result = nu_pdma_sg_transfer(psNuI2sDai->pdma_chanid, psNuI2sDai->pdma_descs[0], 0);
  155. RT_ASSERT(result == RT_EOK);
  156. return result;
  157. }
  158. static rt_bool_t nu_i2s_capacity_check(struct rt_audio_configure *pconfig)
  159. {
  160. switch (pconfig->samplebits)
  161. {
  162. case 8:
  163. case 16:
  164. /* case 24: PDMA constrain */
  165. case 32:
  166. break;
  167. default:
  168. goto exit_nu_i2s_capacity_check;
  169. }
  170. switch (pconfig->channels)
  171. {
  172. case 1:
  173. case 2:
  174. break;
  175. default:
  176. goto exit_nu_i2s_capacity_check;
  177. }
  178. return RT_TRUE;
  179. exit_nu_i2s_capacity_check:
  180. return RT_FALSE;
  181. }
  182. static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pconfig)
  183. {
  184. rt_err_t result = RT_EOK;
  185. nu_acodec_ops_t pNuACodecOps = RT_NULL;
  186. RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
  187. pNuACodecOps = psNuI2s->AcodecOps;
  188. rt_uint32_t real_samplerate;
  189. /* Open I2S */
  190. if (nu_i2s_capacity_check(pconfig) == RT_TRUE)
  191. {
  192. /* Reset audio codec */
  193. if (pNuACodecOps->nu_acodec_reset)
  194. result = pNuACodecOps->nu_acodec_reset();
  195. if (result != RT_EOK)
  196. goto exit_nu_i2s_dai_setup;
  197. /* Setup audio codec */
  198. if (pNuACodecOps->nu_acodec_init)
  199. result = pNuACodecOps->nu_acodec_init();
  200. if (!pNuACodecOps->nu_acodec_init || result != RT_EOK)
  201. goto exit_nu_i2s_dai_setup;
  202. /* Setup acodec samplerate/samplebit/channel */
  203. if (pNuACodecOps->nu_acodec_dsp_control)
  204. result = pNuACodecOps->nu_acodec_dsp_control(pconfig);
  205. if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK)
  206. goto exit_nu_i2s_dai_setup;
  207. real_samplerate = I2S_Open(psNuI2s->i2s_base,
  208. (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? I2S_MODE_SLAVE : I2S_MODE_MASTER,
  209. pconfig->samplerate,
  210. (((pconfig->samplebits / 8) - 1) << I2S_CTL0_DATWIDTH_Pos),
  211. (pconfig->channels == 1) ? I2S_ENABLE_MONO : I2S_DISABLE_MONO,
  212. I2S_FORMAT_I2S);
  213. LOG_I("Open I2S.");
  214. /* Open I2S0 interface and set to slave mode, stereo channel, I2S format */
  215. if (pconfig->samplerate != real_samplerate)
  216. {
  217. LOG_W("Real sample rate: %d Hz != preferred sample rate: %d Hz\n", real_samplerate, pconfig->samplerate);
  218. }
  219. /* Set MCLK and enable MCLK */
  220. /* The target MCLK is related to audio codec setting. */
  221. I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
  222. /* Set unmute */
  223. if (pNuACodecOps->nu_acodec_mixer_control)
  224. pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE);
  225. }
  226. else
  227. result = -RT_EINVAL;
  228. exit_nu_i2s_dai_setup:
  229. return result;
  230. }
  231. static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
  232. {
  233. rt_err_t result = RT_EOK;
  234. nu_i2s_t psNuI2s;
  235. nu_acodec_ops_t pNuACodecOps = RT_NULL;
  236. RT_ASSERT(audio != RT_NULL);
  237. RT_ASSERT(caps != RT_NULL);
  238. psNuI2s = (nu_i2s_t)audio;
  239. RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
  240. pNuACodecOps = psNuI2s->AcodecOps;
  241. switch (caps->main_type)
  242. {
  243. case AUDIO_TYPE_QUERY:
  244. switch (caps->sub_type)
  245. {
  246. case AUDIO_TYPE_QUERY:
  247. caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
  248. break;
  249. default:
  250. result = -RT_ERROR;
  251. break;
  252. } // switch (caps->sub_type)
  253. break;
  254. case AUDIO_TYPE_MIXER:
  255. if (pNuACodecOps->nu_acodec_mixer_query)
  256. {
  257. switch (caps->sub_type)
  258. {
  259. case AUDIO_MIXER_QUERY:
  260. return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask);
  261. default:
  262. return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value);
  263. } // switch (caps->sub_type)
  264. } // if (pNuACodecOps->nu_acodec_mixer_query)
  265. result = -RT_ERROR;
  266. break;
  267. case AUDIO_TYPE_INPUT:
  268. case AUDIO_TYPE_OUTPUT:
  269. switch (caps->sub_type)
  270. {
  271. case AUDIO_DSP_PARAM:
  272. caps->udata.config.channels = psNuI2s->config.channels;
  273. caps->udata.config.samplebits = psNuI2s->config.samplebits;
  274. caps->udata.config.samplerate = psNuI2s->config.samplerate;
  275. break;
  276. case AUDIO_DSP_SAMPLERATE:
  277. caps->udata.config.samplerate = psNuI2s->config.samplerate;
  278. break;
  279. case AUDIO_DSP_CHANNELS:
  280. caps->udata.config.channels = psNuI2s->config.channels;
  281. break;
  282. case AUDIO_DSP_SAMPLEBITS:
  283. caps->udata.config.samplebits = psNuI2s->config.samplebits;
  284. break;
  285. default:
  286. result = -RT_ERROR;
  287. break;
  288. } // switch (caps->sub_type)
  289. break;
  290. default:
  291. result = -RT_ERROR;
  292. break;
  293. } // switch (caps->main_type)
  294. return result;
  295. }
  296. static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
  297. {
  298. rt_err_t result = RT_EOK;
  299. nu_i2s_t psNuI2s;
  300. nu_acodec_ops_t pNuACodecOps = RT_NULL;
  301. int stream = -1;
  302. RT_ASSERT(audio != RT_NULL);
  303. RT_ASSERT(caps != RT_NULL);
  304. psNuI2s = (nu_i2s_t)audio;
  305. RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
  306. pNuACodecOps = psNuI2s->AcodecOps;
  307. switch (caps->main_type)
  308. {
  309. case AUDIO_TYPE_MIXER:
  310. if (psNuI2s->AcodecOps->nu_acodec_mixer_control)
  311. psNuI2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value);
  312. break;
  313. case AUDIO_TYPE_INPUT:
  314. stream = AUDIO_STREAM_RECORD;
  315. case AUDIO_TYPE_OUTPUT:
  316. {
  317. rt_bool_t bNeedReset = RT_FALSE;
  318. if (stream < 0)
  319. stream = AUDIO_STREAM_REPLAY;
  320. switch (caps->sub_type)
  321. {
  322. case AUDIO_DSP_PARAM:
  323. if (rt_memcmp(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0)
  324. {
  325. rt_memcpy(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure));
  326. bNeedReset = RT_TRUE;
  327. }
  328. break;
  329. case AUDIO_DSP_SAMPLEBITS:
  330. if (psNuI2s->config.samplerate != caps->udata.config.samplebits)
  331. {
  332. psNuI2s->config.samplerate = caps->udata.config.samplebits;
  333. bNeedReset = RT_TRUE;
  334. }
  335. break;
  336. case AUDIO_DSP_CHANNELS:
  337. if (psNuI2s->config.channels != caps->udata.config.channels)
  338. {
  339. pNuACodecOps->config.channels = caps->udata.config.channels;
  340. bNeedReset = RT_TRUE;
  341. }
  342. break;
  343. case AUDIO_DSP_SAMPLERATE:
  344. if (psNuI2s->config.samplerate != caps->udata.config.samplerate)
  345. {
  346. psNuI2s->config.samplerate = caps->udata.config.samplerate;
  347. bNeedReset = RT_TRUE;
  348. }
  349. break;
  350. default:
  351. result = -RT_ERROR;
  352. break;
  353. } // switch (caps->sub_type)
  354. if (bNeedReset)
  355. {
  356. return nu_i2s_start(audio, stream);
  357. }
  358. }
  359. break;
  360. default:
  361. result = -RT_ERROR;
  362. break;
  363. } // switch (caps->main_type)
  364. return result;
  365. }
  366. static rt_err_t nu_i2s_init(struct rt_audio_device *audio)
  367. {
  368. rt_err_t result = RT_EOK;
  369. nu_i2s_t psNuI2s;
  370. RT_ASSERT(audio != RT_NULL);
  371. psNuI2s = (nu_i2s_t)audio;
  372. /* Reset this module */
  373. SYS_ResetModule(psNuI2s->i2s_rst);
  374. return -(result);
  375. }
  376. static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream)
  377. {
  378. nu_i2s_t psNuI2s;
  379. RT_ASSERT(audio != RT_NULL);
  380. psNuI2s = (nu_i2s_t)audio;
  381. /* Restart all: I2S and codec. */
  382. nu_i2s_stop(audio, stream);
  383. if (nu_i2s_dai_setup(psNuI2s, &psNuI2s->config) != RT_EOK)
  384. return -RT_ERROR;
  385. switch (stream)
  386. {
  387. case AUDIO_STREAM_REPLAY:
  388. {
  389. nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_PLAYBACK);
  390. /* Start TX DMA */
  391. I2S_ENABLE_TXDMA(psNuI2s->i2s_base);
  392. /* Enable I2S Tx function */
  393. I2S_ENABLE_TX(psNuI2s->i2s_base);
  394. LOG_I("Start replay.");
  395. }
  396. break;
  397. case AUDIO_STREAM_RECORD:
  398. {
  399. nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_CAPTURE);
  400. /* Start RX DMA */
  401. I2S_ENABLE_RXDMA(psNuI2s->i2s_base);
  402. /* Enable I2S Rx function */
  403. I2S_ENABLE_RX(psNuI2s->i2s_base);
  404. LOG_I("Start record.");
  405. }
  406. break;
  407. default:
  408. return -RT_ERROR;
  409. }
  410. return RT_EOK;
  411. }
  412. static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream)
  413. {
  414. nu_i2s_t psNuI2s;
  415. nu_i2s_dai_t psNuI2sDai = RT_NULL;
  416. RT_ASSERT(audio != RT_NULL);
  417. psNuI2s = (nu_i2s_t)audio;
  418. switch (stream)
  419. {
  420. case AUDIO_STREAM_REPLAY:
  421. psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
  422. // Disable TX
  423. I2S_DISABLE_TXDMA(psNuI2s->i2s_base);
  424. I2S_DISABLE_TX(psNuI2s->i2s_base);
  425. LOG_I("Stop replay.");
  426. break;
  427. case AUDIO_STREAM_RECORD:
  428. psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE];
  429. // Disable RX
  430. I2S_DISABLE_RXDMA(psNuI2s->i2s_base);
  431. I2S_DISABLE_RX(psNuI2s->i2s_base);
  432. LOG_I("Stop record.");
  433. break;
  434. default:
  435. return -RT_EINVAL;
  436. }
  437. /* Stop DMA transfer. */
  438. nu_pdma_channel_terminate(psNuI2sDai->pdma_chanid);
  439. /* Close I2S */
  440. if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk)))
  441. {
  442. I2S_DisableMCLK(psNuI2s->i2s_base);
  443. I2S_Close(psNuI2s->i2s_base);
  444. LOG_I("Close I2S.");
  445. }
  446. /* Silence */
  447. rt_memset((void *)psNuI2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE);
  448. psNuI2sDai->fifo_block_idx = 0;
  449. return RT_EOK;
  450. }
  451. static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
  452. {
  453. nu_i2s_t psNuI2s;
  454. RT_ASSERT(audio != RT_NULL);
  455. RT_ASSERT(info != RT_NULL);
  456. psNuI2s = (nu_i2s_t)audio;
  457. /* Report uncacheable memory address to upper layer. */
  458. info->buffer = (rt_uint8_t *)((uint32_t)psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo | UNCACHEABLE);
  459. info->total_size = NU_I2S_DMA_FIFO_SIZE;
  460. info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE;
  461. info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER;
  462. //rt_kprintf("info->buffer=%08x\n", (uint32_t)info->buffer);
  463. //rt_kprintf("info->total_size=%d\n", (uint32_t)info->total_size);
  464. //rt_kprintf("info->block_size=%d\n", (uint32_t)info->block_size);
  465. //rt_kprintf("info->block_count=%d\n", (uint32_t)info->block_count);
  466. return;
  467. }
  468. static struct rt_audio_ops nu_i2s_audio_ops =
  469. {
  470. .getcaps = nu_i2s_getcaps,
  471. .configure = nu_i2s_configure,
  472. .init = nu_i2s_init,
  473. .start = nu_i2s_start,
  474. .stop = nu_i2s_stop,
  475. .transmit = RT_NULL,
  476. .buffer_info = nu_i2s_buffer_info
  477. };
  478. static rt_err_t nu_hw_i2s_pdma_allocate(nu_i2s_dai_t psNuI2sDai)
  479. {
  480. /* Allocate I2S nu_dma channel */
  481. if ((psNuI2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuI2sDai->pdma_perp)) < 0)
  482. {
  483. goto nu_hw_i2s_pdma_allocate;
  484. }
  485. return RT_EOK;
  486. nu_hw_i2s_pdma_allocate:
  487. return -(RT_ERROR);
  488. }
  489. int rt_hw_i2s_init(void)
  490. {
  491. int i, j;
  492. nu_i2s_dai_t psNuI2sDai;
  493. for (j = (I2S_START + 1); j < I2S_CNT; j++)
  494. {
  495. for (i = 0; i < NU_I2S_DAI_CNT; i++)
  496. {
  497. uint8_t *pu8ptr = rt_malloc_align(NU_I2S_DMA_FIFO_SIZE, 64);
  498. psNuI2sDai = &nu_i2s_arr[j].i2s_dais[i];
  499. psNuI2sDai->fifo = pu8ptr;
  500. rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE);
  501. RT_ASSERT(psNuI2sDai->fifo != RT_NULL);
  502. rt_kprintf("psNuI2sDai->fifo=%08x\n", (uint32_t)psNuI2sDai->fifo);
  503. psNuI2sDai->pdma_chanid = -1;
  504. psNuI2sDai->fifo_block_idx = 0;
  505. RT_ASSERT(nu_hw_i2s_pdma_allocate(psNuI2sDai) == RT_EOK);
  506. RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuI2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK);
  507. }
  508. /* Register ops of audio device */
  509. nu_i2s_arr[j].audio.ops = &nu_i2s_audio_ops;
  510. /* Register device, RW: it is with replay and record functions. */
  511. rt_audio_register(&nu_i2s_arr[j].audio, nu_i2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &nu_i2s_arr[j]);
  512. }
  513. return RT_EOK;
  514. }
  515. INIT_DEVICE_EXPORT(rt_hw_i2s_init);
  516. #endif //#if defined(BSP_USING_I2S)